From 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:07:36 -0700 Subject: Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with CARRY_WRAPPER in the same way since I0 and I3 could be used --- techlibs/ice40/ice40_opt.cc | 45 --------------------------------------------- 1 file changed, 45 deletions(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index d5106b805..f528607d6 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module) } continue; } - - if (cell->type == "$__ICE40_FULL_ADDER") - { - SigSpec non_const_inputs, replacement_output; - int count_zeros = 0, count_ones = 0; - - SigBit inbit[3] = { - cell->getPort("\\A"), - cell->getPort("\\B"), - cell->getPort("\\CI") - }; - for (int i = 0; i < 3; i++) - if (inbit[i].wire == nullptr) { - if (inbit[i] == State::S1) - count_ones++; - else - count_zeros++; - } else - non_const_inputs.append(inbit[i]); - - if (count_zeros >= 2) - replacement_output = State::S0; - else if (count_ones >= 2) - replacement_output = State::S1; - else if (GetSize(non_const_inputs) == 1) - replacement_output = non_const_inputs; - - if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); - module->connect(cell->getPort("\\CO")[0], replacement_output); - module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", - log_id(module), log_id(cell), log_signal(replacement_output)); - cell->type = "$lut"; - cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); - cell->setPort("\\Y", cell->getPort("\\O")); - cell->unsetPort("\\B"); - cell->unsetPort("\\CI"); - cell->unsetPort("\\CO"); - cell->unsetPort("\\O"); - cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); - cell->setParam("\\WIDTH", 4); - } - continue; - } } for (auto cell : sb_lut_cells) -- cgit v1.2.3 From e569f138704a28654cc52c917bba4decffa29f54 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:22:44 -0700 Subject: Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f. --- techlibs/ice40/ice40_opt.cc | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index f528607d6..d5106b805 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module) } continue; } + + if (cell->type == "$__ICE40_FULL_ADDER") + { + SigSpec non_const_inputs, replacement_output; + int count_zeros = 0, count_ones = 0; + + SigBit inbit[3] = { + cell->getPort("\\A"), + cell->getPort("\\B"), + cell->getPort("\\CI") + }; + for (int i = 0; i < 3; i++) + if (inbit[i].wire == nullptr) { + if (inbit[i] == State::S1) + count_ones++; + else + count_zeros++; + } else + non_const_inputs.append(inbit[i]); + + if (count_zeros >= 2) + replacement_output = State::S0; + else if (count_ones >= 2) + replacement_output = State::S1; + else if (GetSize(non_const_inputs) == 1) + replacement_output = non_const_inputs; + + if (GetSize(replacement_output)) { + optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); + module->connect(cell->getPort("\\CO")[0], replacement_output); + module->design->scratchpad_set_bool("opt.did_something", true); + log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", + log_id(module), log_id(cell), log_signal(replacement_output)); + cell->type = "$lut"; + cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\Y", cell->getPort("\\O")); + cell->unsetPort("\\B"); + cell->unsetPort("\\CI"); + cell->unsetPort("\\CO"); + cell->unsetPort("\\O"); + cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); + cell->setParam("\\WIDTH", 4); + } + continue; + } } for (auto cell : sb_lut_cells) -- cgit v1.2.3 From f5b4bc847c02d6c3e06c086a1375840ccac936cd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:25:05 -0700 Subject: Adapt to $__ICE40_CARRY_WRAPPER --- techlibs/ice40/ice40_opt.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index d5106b805..58f106f7c 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module) continue; } - if (cell->type == "$__ICE40_FULL_ADDER") + if (cell->type == "$__ICE40_CARRY_WRAPPER") { SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; @@ -114,13 +114,15 @@ static void run_ice40_opts(Module *module) optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", + log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); + cell->unsetPort("\\I0"); + cell->unsetPort("\\I3"); cell->unsetPort("\\CO"); cell->unsetPort("\\O"); cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); -- cgit v1.2.3 From a4f641f2303bc6f04751a15ec49cf2658ea8eb63 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 18:45:09 -0700 Subject: Do not overwrite LUT param --- techlibs/ice40/ice40_opt.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 58f106f7c..ea56d3f4d 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\I3"); cell->unsetPort("\\CO"); cell->unsetPort("\\O"); - cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); cell->setParam("\\WIDTH", 4); } continue; -- cgit v1.2.3