From c5d28f5d6b20a42e6f3a4b1a4e3be341a352e5e3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 4 Jan 2020 19:00:44 +0100 Subject: Valid to have attribute starting with SB_CARRY. --- techlibs/ice40/ice40_opt.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 371ceb623..9bee0444b 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -128,6 +128,8 @@ static void run_ice40_opts(Module *module) new_attr.insert(std::make_pair(a.first, a.second)); else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) continue; + else if (a.first.begins_with("\\SB_CARRY.\\")) + continue; else log_abort(); cell->attributes = std::move(new_attr); -- cgit v1.2.3 From b1787615514f84c83c27d08011427e90c9bd0f4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Jan 2020 11:59:48 -0800 Subject: ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 --- techlibs/ice40/ice40_opt.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 9bee0444b..df10a2842 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,7 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") }); + auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); + cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); @@ -148,6 +149,7 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\CO"); cell->unsetPort("\\O"); cell->setParam("\\WIDTH", 4); + cell->unsetParam("\\I3_IS_CI"); } continue; } -- cgit v1.2.3 From cfb0366a18b0f3cab254636fdf534a3de76af8d5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 Jan 2020 13:56:16 -0800 Subject: Import tests from #1628 --- techlibs/ice40/ice40_opt.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index df10a2842..940a11063 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,8 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); + auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); + cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); -- cgit v1.2.3 From e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 Jan 2020 14:02:13 -0800 Subject: Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards Just like Verilog... --- techlibs/ice40/ice40_opt.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 940a11063..925ab31bb 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module) log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); - cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 }); + cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); -- cgit v1.2.3