From 0f5bddcd792ed2da2b9a3eb12e775537f394e771 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Jul 2019 00:52:31 -0700 Subject: ice40_opt to handle this box and opt back to SB_LUT4 --- techlibs/ice40/ice40_opt.cc | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index f528607d6..b22fc83fe 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -83,6 +83,54 @@ static void run_ice40_opts(Module *module) } continue; } + + if (cell->type == "$__ICE40_CARRY_LUT4") + { + SigSpec non_const_inputs, replacement_output; + int count_zeros = 0, count_ones = 0; + + SigBit inbit[3] = { + cell->getPort("\\A"), + cell->getPort("\\B"), + cell->getPort("\\CI") + }; + for (int i = 0; i < 3; i++) + if (inbit[i].wire == nullptr) { + if (inbit[i] == State::S1) + count_ones++; + else + count_zeros++; + } else + non_const_inputs.append(inbit[i]); + + if (count_zeros >= 2) + replacement_output = State::S0; + else if (count_ones >= 2) + replacement_output = State::S1; + else if (GetSize(non_const_inputs) == 1) + replacement_output = non_const_inputs; + + if (GetSize(replacement_output)) { + optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); + module->connect(cell->getPort("\\CO")[0], replacement_output); + module->design->scratchpad_set_bool("opt.did_something", true); + log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n", + log_id(module), log_id(cell), log_signal(replacement_output)); + cell->type = "\\SB_LUT4"; + sb_lut_cells.push_back(cell); + cell->setPort("\\I0", RTLIL::S0); + cell->setPort("\\I1", inbit[0]); + cell->setPort("\\I2", inbit[1]); + cell->setPort("\\I3", inbit[2]); + cell->unsetPort("\\A"); + cell->unsetPort("\\B"); + cell->unsetPort("\\CI"); + cell->unsetPort("\\CO"); + cell->setParam("\\LUT_INIT", std::string("0110100110010110")); + sb_lut_cells.push_back(cell); + } + continue; + } } for (auto cell : sb_lut_cells) -- cgit v1.2.3 From 4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Jul 2019 01:08:48 -0700 Subject: Remove double push --- techlibs/ice40/ice40_opt.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index b22fc83fe..4e50b250e 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -117,7 +117,6 @@ static void run_ice40_opts(Module *module) log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "\\SB_LUT4"; - sb_lut_cells.push_back(cell); cell->setPort("\\I0", RTLIL::S0); cell->setPort("\\I1", inbit[0]); cell->setPort("\\I2", inbit[1]); -- cgit v1.2.3 From 7a912f22b2c3976d72a25ffd605a1cf598b67983 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Jul 2019 01:32:10 -0700 Subject: Use Const::from_string() not its constructor... --- techlibs/ice40/ice40_opt.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 4e50b250e..67e8771b4 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -125,7 +125,7 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\B"); cell->unsetPort("\\CI"); cell->unsetPort("\\CO"); - cell->setParam("\\LUT_INIT", std::string("0110100110010110")); + cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110")); sb_lut_cells.push_back(cell); } continue; -- cgit v1.2.3 From d032198facc05634bd617328e1865e7f0d8d953c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 13 Jul 2019 01:11:00 -0700 Subject: ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT --- techlibs/ice40/ice40_opt.cc | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 67e8771b4..38910dffa 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -114,19 +114,17 @@ static void run_ice40_opts(Module *module) optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n", + log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); - cell->type = "\\SB_LUT4"; - cell->setPort("\\I0", RTLIL::S0); - cell->setPort("\\I1", inbit[0]); - cell->setPort("\\I2", inbit[1]); - cell->setPort("\\I3", inbit[2]); - cell->unsetPort("\\A"); + cell->type = "$lut"; + cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); cell->unsetPort("\\CO"); - cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110")); - sb_lut_cells.push_back(cell); + cell->unsetPort("\\O"); + cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); + cell->setParam("\\WIDTH", 4); } continue; } -- cgit v1.2.3 From 5fb27c071bb072644dbb38cf8a516628c2afe15b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 12:03:51 -0700 Subject: $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark --- techlibs/ice40/ice40_opt.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/ice40/ice40_opt.cc') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 38910dffa..e492454fb 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module) continue; } - if (cell->type == "$__ICE40_CARRY_LUT4") + if (cell->type == "$__ICE40_FULL_ADDER") { SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; @@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module) optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n", + log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] }); -- cgit v1.2.3