From 082cbcb4c7c4fa6984f86f8edb2e1d16e8ad3a41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Thu, 20 Aug 2020 21:59:37 +0200 Subject: synth_intel: Remove incomplete Arria 10 GX support. The techmap rules for this target do not work in the first place (note lack of >2-input LUT mappings), and if proper support is ever added, it'd be better placed in the synth_intel_alm backend. --- techlibs/intel/arria10gx/cells_arith.v | 71 ---------------------------------- techlibs/intel/arria10gx/cells_map.v | 54 -------------------------- techlibs/intel/arria10gx/cells_sim.v | 59 ---------------------------- 3 files changed, 184 deletions(-) delete mode 100644 techlibs/intel/arria10gx/cells_arith.v delete mode 100644 techlibs/intel/arria10gx/cells_map.v delete mode 100644 techlibs/intel/arria10gx/cells_sim.v (limited to 'techlibs/intel/arria10gx') diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v deleted file mode 100644 index 6a52a0f95..000000000 --- a/techlibs/intel/arria10gx/cells_arith.v +++ /dev/null @@ -1,71 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// NOTE: This is still WIP. -(* techmap_celltype = "$alu" *) -module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - (* force_downto *) - input [A_WIDTH-1:0] A; - (* force_downto *) - input [B_WIDTH-1:0] B; - (* force_downto *) - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - //output [Y_WIDTH-1:0] CO; - output CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; - - (* force_downto *) - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - (* force_downto *) - wire [Y_WIDTH-1:0] AA = A_buf; - (* force_downto *) - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - //wire [Y_WIDTH:0] C = {CO, CI}; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; - - /* Start implementation */ - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - - genvar i; - generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); - assign CO = COx[Y_WIDTH]; - end - else - fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); - end: slice - endgenerate - /* End implementation */ - assign X = AA ^ BB; - -endmodule diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v deleted file mode 100644 index 83f5881da..000000000 --- a/techlibs/intel/arria10gx/cells_map.v +++ /dev/null @@ -1,54 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -// Input buffer map -module \$__inpad (input I, output O); - twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); -endmodule - -// Output buffer map -module \$__outpad (input I, output O); - twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); -endmodule - -// LUT Map -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - (* force_downto *) - input [WIDTH-1:0] A; - output Y; - generate - if (WIDTH == 1) begin - assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end else - if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); - end /*else - if(WIDTH == 3) begin - fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1)); - end else - if(WIDTH == 4) begin - fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3])); - end*/ else - wire _TECHMAP_FAIL_ = 1; - endgenerate -endmodule // - - diff --git a/techlibs/intel/arria10gx/cells_sim.v b/techlibs/intel/arria10gx/cells_sim.v deleted file mode 100644 index e892b377e..000000000 --- a/techlibs/intel/arria10gx/cells_sim.v +++ /dev/null @@ -1,59 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -module VCC (output V); - assign V = 1'b1; -endmodule // VCC - -module GND (output G); - assign G = 1'b0; -endmodule // GND - -/* Altera Arria 10 GX devices Input Buffer Primitive */ -module twentynm_io_ibuf (output o, input i, input ibar); - assign ibar = ibar; - assign o = i; -endmodule // twentynm_io_ibuf - -/* Altera Arria 10 GX devices Output Buffer Primitive */ -module twentynm_io_obuf (output o, input i, input oe); - assign o = i; - assign oe = oe; -endmodule // twentynm_io_obuf - -/* Altera Arria 10 GX LUT Primitive */ -module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, - input datae, dataf, datag, cin, - input sharein); - -parameter lut_mask = 64'hFFFFFFFFFFFFFFFF; -parameter dont_touch = "off"; -parameter lpm_type = "twentynm_lcell_comb"; -parameter shared_arith = "off"; -parameter extended_lut = "off"; - -// TODO: This is still WIP -initial begin - $display("Simulation model is still under investigation\n"); -end - -endmodule // twentynm_lcell_comb - - - -- cgit v1.2.3