From 50bcd9a728ff89f220873b3345c4e18a65c4a37f Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Wed, 4 Oct 2017 17:01:30 -0700 Subject: Clean whitespace and permissions in techlibs/intel --- techlibs/intel/max10/cells_arith.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) mode change 100755 => 100644 techlibs/intel/max10/cells_arith.v (limited to 'techlibs/intel/max10/cells_arith.v') diff --git a/techlibs/intel/max10/cells_arith.v b/techlibs/intel/max10/cells_arith.v old mode 100755 new mode 100644 index 9ef073f7c..e2194cbd7 --- a/techlibs/intel/max10/cells_arith.v +++ b/techlibs/intel/max10/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule -- cgit v1.2.3