From 50bcd9a728ff89f220873b3345c4e18a65c4a37f Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Wed, 4 Oct 2017 17:01:30 -0700 Subject: Clean whitespace and permissions in techlibs/intel --- techlibs/intel/max10/cells_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) mode change 100755 => 100644 techlibs/intel/max10/cells_map.v (limited to 'techlibs/intel/max10/cells_map.v') diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v old mode 100755 new mode 100644 index b74007ff8..9229fae51 --- a/techlibs/intel/max10/cells_map.v +++ b/techlibs/intel/max10/cells_map.v @@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -62,7 +62,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function -- cgit v1.2.3