From 5b779f7f4ef0bf2c4ad3a412da24fad30b078626 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Thu, 16 Apr 2020 12:24:04 +0100 Subject: intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of _mlab_cell gets ignored by Quartus. --- techlibs/intel_alm/common/bram_m10k_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/intel_alm/common/bram_m10k_map.v') diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v index e5566010d..061463c3e 100644 --- a/techlibs/intel_alm/common/bram_m10k_map.v +++ b/techlibs/intel_alm/common/bram_m10k_map.v @@ -28,4 +28,4 @@ altsyncram #( .clock1(CLK1) ); -endmodule +endmodule -- cgit v1.2.3