From 5b779f7f4ef0bf2c4ad3a412da24fad30b078626 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Thu, 16 Apr 2020 12:24:04 +0100 Subject: intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of _mlab_cell gets ignored by Quartus. --- techlibs/intel_alm/common/lutram_mlab_map.v | 29 ----------------------------- 1 file changed, 29 deletions(-) delete mode 100644 techlibs/intel_alm/common/lutram_mlab_map.v (limited to 'techlibs/intel_alm/common/lutram_mlab_map.v') diff --git a/techlibs/intel_alm/common/lutram_mlab_map.v b/techlibs/intel_alm/common/lutram_mlab_map.v deleted file mode 100644 index 3a9c8590e..000000000 --- a/techlibs/intel_alm/common/lutram_mlab_map.v +++ /dev/null @@ -1,29 +0,0 @@ -module __MISTRAL_MLAB(CLK1, CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA); - -parameter CFG_ABITS = 5; -parameter CFG_DBITS = 20; - -input CLK1, CLK2; -input [CFG_ABITS-1:0] A1ADDR, B1ADDR; -input [CFG_DBITS-1:0] A1DATA; -input A1EN; -output [CFG_DBITS-1:0] B1DATA; - -altsyncram #( - .operation_mode("dual_port"), - .ram_block_type("mlab"), - .widthad_a(CFG_ABITS), - .width_a(CFG_DBITS), - .widthad_b(CFG_ABITS), - .width_b(CFG_DBITS), -) _TECHMAP_REPLACE_ ( - .address_a(A1ADDR), - .data_a(A1DATA), - .wren_a(A1EN), - .address_b(B1ADDR), - .q_b(B1DATA), - .clock0(CLK1), - .clock1(CLK1), -); - -endmodule -- cgit v1.2.3