From eb106732d94322fb5b48fbff0420ce5a6fc83eb9 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 14:34:48 +0100 Subject: intel_alm: Add global buffer insertion Signed-off-by: gatecat --- techlibs/intel_alm/common/misc_sim.v | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'techlibs/intel_alm/common/misc_sim.v') diff --git a/techlibs/intel_alm/common/misc_sim.v b/techlibs/intel_alm/common/misc_sim.v index e9494a8ee..b1f970a21 100644 --- a/techlibs/intel_alm/common/misc_sim.v +++ b/techlibs/intel_alm/common/misc_sim.v @@ -10,3 +10,12 @@ module MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output assign PAD = OE ? I : 1'bz; assign O = PAD; endmodule + +// Eventually, we should support clock enables and model them here too. +// For now, CLKENA is used as a basic entry point to global routing. +module MISTRAL_CLKBUF ( + input A, + (* clkbuf_driver *) output Q +); + assign Q = A; +endmodule \ No newline at end of file -- cgit v1.2.3