From dce037a62c5bda9a8256d271d39b06be366120e8 Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 12 Apr 2021 10:33:40 +0100 Subject: quicklogic: ABC9 synthesis --- techlibs/quicklogic/abc9_map.v | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 techlibs/quicklogic/abc9_map.v (limited to 'techlibs/quicklogic/abc9_map.v') diff --git a/techlibs/quicklogic/abc9_map.v b/techlibs/quicklogic/abc9_map.v new file mode 100644 index 000000000..46c11d675 --- /dev/null +++ b/techlibs/quicklogic/abc9_map.v @@ -0,0 +1,26 @@ +// This file exists to map purely-synchronous flops to ABC9 flops, while +// mapping flops with asynchronous-set/clear as boxes, this is because ABC9 +// doesn't support asynchronous-set/clear flops in sequential synthesis. + +module dffepc ( + output Q, + input D, + input CLK, + input EN, + input CLR, + input PRE +); + +parameter INIT = 1'b0; + +parameter _TECHMAP_CONSTMSK_CLR_ = 1'b0; +parameter _TECHMAP_CONSTMSK_PRE_ = 1'b0; +parameter _TECHMAP_CONSTVAL_CLR_ = 1'b0; +parameter _TECHMAP_CONSTVAL_PRE_ = 1'b0; + +if (_TECHMAP_CONSTMSK_CLR_ != 1'b0 && _TECHMAP_CONSTMSK_PRE_ != 1'b0 && _TECHMAP_CONSTVAL_CLR_ == 1'b0 && _TECHMAP_CONSTVAL_PRE_ == 1'b0) + $__PP3_DFFEPC_SYNCONLY _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN)); +else + wire _TECHMAP_FAIL_ = 1; + +endmodule -- cgit v1.2.3