From dce037a62c5bda9a8256d271d39b06be366120e8 Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 12 Apr 2021 10:33:40 +0100 Subject: quicklogic: ABC9 synthesis --- techlibs/quicklogic/abc9_unmap.v | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 techlibs/quicklogic/abc9_unmap.v (limited to 'techlibs/quicklogic/abc9_unmap.v') diff --git a/techlibs/quicklogic/abc9_unmap.v b/techlibs/quicklogic/abc9_unmap.v new file mode 100644 index 000000000..1681e01bb --- /dev/null +++ b/techlibs/quicklogic/abc9_unmap.v @@ -0,0 +1,14 @@ +module $__PP3_DFFEPC_SYNCONLY ( + output Q, + input D, + input CLK, + input EN, +); + +// For some reason ABC9 adds init attributes to wires even though they were removed before mapping. +// As a workaround, remove any init attributes that get reintroduced. +wire _TECHMAP_REMOVEINIT_Q_ = 1; + +dffepc _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0)); + +endmodule -- cgit v1.2.3