From 82f60ba938749ab20694f9070f1046e393f16f3c Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Sat, 19 Oct 2019 14:04:52 +0800 Subject: Makefile: don't assume python is called `python3` On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross --- techlibs/xilinx/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 0ae67d9e7..1e59f0a1b 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -13,7 +13,7 @@ EXTRA_OBJS += techlibs/xilinx/brams_init.mk techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py $(Q) mkdir -p techlibs/xilinx - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch $@ techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk -- cgit v1.2.3 From 7b350cacd410b16fdac5a6933aea1bb009b83621 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 8 Oct 2019 17:00:30 +0000 Subject: xilinx: Support multiplier mapping for all families. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. --- techlibs/xilinx/Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 1e59f0a1b..3354605ef 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -42,7 +42,13 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v)) -- cgit v1.2.3 From 6769d31ddbab341940af9b42b538fca60797fdf4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 18 Oct 2019 13:24:19 +0100 Subject: xilinx: Add support for UltraScale[+] BRAM mapping Signed-off-by: David Shah --- techlibs/xilinx/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 3354605ef..6fc41f591 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -32,9 +32,11 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) -- cgit v1.2.3 From 3506eaf2904cddf5132c598a527e050a79a181d5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 18 Oct 2019 14:02:57 +0100 Subject: xilinx: Add URAM288 mapping for xcup Signed-off-by: David Shah --- techlibs/xilinx/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 6fc41f591..debe8a6a0 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -37,6 +37,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) -- cgit v1.2.3 From c4bd318e76240d3e6a95109c19641cdfd86517b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 1 Nov 2019 14:00:15 +0000 Subject: synth_xilinx: Merge blackbox primitive libraries. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. --- techlibs/xilinx/Makefile.inc | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index debe8a6a0..3ebc72fe8 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -25,18 +25,12 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) -- cgit v1.2.3