From 30854b9c7f23e2817a445761022668d6b0f7c0ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 4 Feb 2020 15:35:47 +0100 Subject: xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. --- techlibs/xilinx/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'techlibs/xilinx/Makefile.inc') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 60b4ace1c..7785bf81c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -27,6 +27,9 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sa_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) -- cgit v1.2.3