From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:16:37 -0700
Subject: Remove sequential extension

---
 techlibs/xilinx/abc_map.v | 97 -----------------------------------------------
 1 file changed, 97 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index a760b3d6d..121862692 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -20,103 +20,6 @@
 
 // ============================================================================
 
-module FDRE (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE_1 #(
-      .INIT(|0),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-
-module FDCE (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(
-    .INIT(INIT),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-
-module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE_1 #(
-    .INIT(INIT),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-
 module RAM32X1D (
   output DPO, SPO,
   input  D,
-- 
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