From 6bb8e6a7267b4e3d8c1717cde87d41d04fdac82d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Sep 2019 17:11:01 -0700
Subject: Initial DSP48E1 box support

---
 techlibs/xilinx/abc_map.v | 216 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 216 insertions(+)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 0c85d6656..be69ae256 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -121,3 +121,219 @@ module SRLC32E (
   );
   \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
 endmodule
+
+module DSP48E1 (
+    output [29:0] ACOUT,
+    output [17:0] BCOUT,
+    output reg CARRYCASCOUT,
+    output reg [3:0] CARRYOUT,
+    output reg MULTSIGNOUT,
+    output OVERFLOW,
+    output reg signed [47:0] P,
+    output PATTERNBDETECT,
+    output PATTERNDETECT,
+    output [47:0] PCOUT,
+    output UNDERFLOW,
+    input signed [29:0] A,
+    input [29:0] ACIN,
+    input [3:0] ALUMODE,
+    input signed [17:0] B,
+    input [17:0] BCIN,
+    input [47:0] C,
+    input CARRYCASCIN,
+    input CARRYIN,
+    input [2:0] CARRYINSEL,
+    input CEA1,
+    input CEA2,
+    input CEAD,
+    input CEALUMODE,
+    input CEB1,
+    input CEB2,
+    input CEC,
+    input CECARRYIN,
+    input CECTRL,
+    input CED,
+    input CEINMODE,
+    input CEM,
+    input CEP,
+    input CLK,
+    input [24:0] D,
+    input [4:0] INMODE,
+    input MULTSIGNIN,
+    input [6:0] OPMODE,
+    input [47:0] PCIN,
+    input RSTA,
+    input RSTALLCARRYIN,
+    input RSTALUMODE,
+    input RSTB,
+    input RSTC,
+    input RSTCTRL,
+    input RSTD,
+    input RSTINMODE,
+    input RSTM,
+    input RSTP
+);
+    parameter integer ACASCREG = 1;
+    parameter integer ADREG = 1;
+    parameter integer ALUMODEREG = 1;
+    parameter integer AREG = 1;
+    parameter AUTORESET_PATDET = "NO_RESET";
+    parameter A_INPUT = "DIRECT";
+    parameter integer BCASCREG = 1;
+    parameter integer BREG = 1;
+    parameter B_INPUT = "DIRECT";
+    parameter integer CARRYINREG = 1;
+    parameter integer CARRYINSELREG = 1;
+    parameter integer CREG = 1;
+    parameter integer DREG = 1;
+    parameter integer INMODEREG = 1;
+    parameter integer MREG = 1;
+    parameter integer OPMODEREG = 1;
+    parameter integer PREG = 1;
+    parameter SEL_MASK = "MASK";
+    parameter SEL_PATTERN = "PATTERN";
+    parameter USE_DPORT = "FALSE";
+    parameter USE_MULT = "MULTIPLY";
+    parameter USE_PATTERN_DETECT = "NO_PATDET";
+    parameter USE_SIMD = "ONE48";
+    parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+    parameter [47:0] PATTERN = 48'h000000000000;
+    parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+    parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
+    parameter [0:0] IS_CLK_INVERTED = 1'b0;
+    parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+    parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+
+    parameter _TECHMAP_CELLTYPE_ = "";
+
+    generate
+    if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
+        wire [29:0] iA;
+        wire [17:0] iB;
+        wire [47:0] iC;
+        wire [24:0] iD;
+
+        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire [47:0] oP, oPCOUT;
+
+		// Disconnect the A-input if MREG is enabled, since
+		//   combinatorial path is broken
+        if (AREG == 0 || MREG == 1 || PREG == 1)
+            assign iA = A;
+        else
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+        if (BREG == 0 || MREG == 1 || PREG == 1)
+            assign iB = B;
+        else
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+        if (CREG == 0 || PREG == 1)
+            assign iC = C;
+        else
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+        if (DREG == 0)
+            assign iD = D;
+        else if (_TECHMAP_CELLTYPE_ != "")
+			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        if (ADREG == 1 && _TECHMAP_CELLTYPE_ != "")
+			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+		if (PREG == 0) begin
+			if (MREG == 1)
+				\$__ABC_DSP48E1_REG rM (.Q(pM));
+		end
+		else
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
+
+        \$__ABC_DSP48E1_MULT_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+        );
+        \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        );
+
+        \$__ABC_DSP48E1_MULT #(
+            .ACASCREG(ACASCREG),
+            .ADREG(ADREG),
+            .ALUMODEREG(ALUMODEREG),
+            .AREG(AREG),
+            .AUTORESET_PATDET(AUTORESET_PATDET),
+            .A_INPUT(A_INPUT),
+            .BCASCREG(BCASCREG),
+            .BREG(BREG),
+            .B_INPUT(B_INPUT),
+            .CARRYINREG(CARRYINREG),
+            .CARRYINSELREG(CARRYINSELREG),
+            .CREG(CREG),
+            .DREG(DREG),
+            .INMODEREG(INMODEREG),
+            .MREG(MREG),
+            .OPMODEREG(OPMODEREG),
+            .PREG(PREG),
+            .SEL_MASK(SEL_MASK),
+            .SEL_PATTERN(SEL_PATTERN),
+            .USE_DPORT(USE_DPORT),
+            .USE_MULT(USE_MULT),
+            .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
+            .USE_SIMD(USE_SIMD),
+            .MASK(MASK),
+            .PATTERN(PATTERN),
+            .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
+            .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
+            .IS_CLK_INVERTED(IS_CLK_INVERTED),
+            .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
+            .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
+        ) _TECHMAP_REPLACE_ (
+            .ACOUT(ACOUT),
+            .BCOUT(BCOUT),
+            .CARRYCASCOUT(CARRYCASCOUT),
+            .CARRYOUT(CARRYOUT),
+            .MULTSIGNOUT(MULTSIGNOUT),
+            .OVERFLOW(OVERFLOW),
+            .P(oP),
+            .PATTERNBDETECT(PATTERNBDETECT),
+            .PATTERNDETECT(PATTERNDETECT),
+            .PCOUT(oPCOUT),
+            .UNDERFLOW(UNDERFLOW),
+            .A(iA),
+            .ACIN(ACIN),
+            .ALUMODE(ALUMODE),
+            .B(iB),
+            .BCIN(BCIN),
+            .C(iC),
+            .CARRYCASCIN(CARRYCASCIN),
+            .CARRYIN(CARRYIN),
+            .CARRYINSEL(CARRYINSEL),
+            .CEA1(CEA1),
+            .CEA2(CEA2),
+            .CEAD(CEAD),
+            .CEALUMODE(CEALUMODE),
+            .CEB1(CEB1),
+            .CEB2(CEB2),
+            .CEC(CEC),
+            .CECARRYIN(CECARRYIN),
+            .CECTRL(CECTRL),
+            .CED(CED),
+            .CEINMODE(CEINMODE),
+            .CEM(CEM),
+            .CEP(CEP),
+            .CLK(CLK),
+            .D(iD),
+            .INMODE(INMODE),
+            .MULTSIGNIN(MULTSIGNIN),
+            .OPMODE(OPMODE),
+            .PCIN(PCIN),
+            .RSTA(RSTA),
+            .RSTALLCARRYIN(RSTALLCARRYIN),
+            .RSTALUMODE(RSTALUMODE),
+            .RSTB(RSTB),
+            .RSTC(RSTC),
+            .RSTCTRL(RSTCTRL),
+            .RSTD(RSTD),
+            .RSTINMODE(RSTINMODE),
+            .RSTM(RSTM),
+            .RSTP(RSTP)
+        );
+    end
+    else
+        wire _TECHMAP_FAIL_ = 1;
+	endgenerate
+endmodule
-- 
cgit v1.2.3


From aaeaab4ac035aaf79f46873e27b8d464675d1c9c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Sep 2019 17:45:02 -0700
Subject: Rename to techmap_guard

---
 techlibs/xilinx/abc_map.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index be69ae256..f52397c9f 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -205,6 +205,7 @@ module DSP48E1 (
     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 
     parameter _TECHMAP_CELLTYPE_ = "";
+    localparam techmap_guard = (_TECHMAP_CELLTYPE_ != "");
 
     generate
     if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
@@ -232,9 +233,9 @@ module DSP48E1 (
             \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0)
             assign iD = D;
-        else if (_TECHMAP_CELLTYPE_ != "")
+        else if (techmap_guard)
 			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
-        if (ADREG == 1 && _TECHMAP_CELLTYPE_ != "")
+        if (ADREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
 		if (PREG == 0) begin
 			if (MREG == 1)
-- 
cgit v1.2.3


From 247a63f55df2e85f0aa15a9a05f436c1225f9ec1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 11:45:55 -0700
Subject: Add support for MULT and DPORT

---
 techlibs/xilinx/abc_map.v | 134 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 130 insertions(+), 4 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index f52397c9f..27133fc1e 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -219,15 +219,15 @@ module DSP48E1 (
 
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
-        if (AREG == 0 || MREG == 1 || PREG == 1)
+        if (AREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A;
         else
             \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
-        if (BREG == 0 || MREG == 1 || PREG == 1)
+        if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B;
         else
             \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
-        if (CREG == 0 || PREG == 1)
+        if (CREG == 0 && PREG == 0)
             assign iC = C;
         else
             \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
@@ -334,7 +334,133 @@ module DSP48E1 (
             .RSTP(RSTP)
         );
     end
+    else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
+        wire [29:0] iA;
+        wire [17:0] iB;
+        wire [47:0] iC;
+        wire [24:0] iD;
+
+        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire [47:0] oP, oPCOUT;
+
+		// Disconnect the A-input if MREG is enabled, since
+		//   combinatorial path is broken
+        if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 1)
+            assign iA = A;
+        else
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+        if (BREG == 0 && MREG == 0 && PREG == 0)
+            assign iB = B;
+        else
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+        if (CREG == 0 && PREG == 0)
+            assign iC = C;
+        else
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+        if (DREG == 0 && ADREG == 0)
+            assign iD = D;
+        else
+            \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
+		if (PREG == 0) begin
+			if (MREG == 1)
+				\$__ABC_DSP48E1_REG rM (.Q(pM));
+            else if (ADREG == 1)
+                \$__ABC_DSP48E1_REG rAD (.Q(pAD));
+		end
+		else
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
+
+        \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+        );
+        \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        );
+
+        \$__ABC_DSP48E1_MULT_DPORT #(
+            .ACASCREG(ACASCREG),
+            .ADREG(ADREG),
+            .ALUMODEREG(ALUMODEREG),
+            .AREG(AREG),
+            .AUTORESET_PATDET(AUTORESET_PATDET),
+            .A_INPUT(A_INPUT),
+            .BCASCREG(BCASCREG),
+            .BREG(BREG),
+            .B_INPUT(B_INPUT),
+            .CARRYINREG(CARRYINREG),
+            .CARRYINSELREG(CARRYINSELREG),
+            .CREG(CREG),
+            .DREG(DREG),
+            .INMODEREG(INMODEREG),
+            .MREG(MREG),
+            .OPMODEREG(OPMODEREG),
+            .PREG(PREG),
+            .SEL_MASK(SEL_MASK),
+            .SEL_PATTERN(SEL_PATTERN),
+            .USE_DPORT(USE_DPORT),
+            .USE_MULT(USE_MULT),
+            .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
+            .USE_SIMD(USE_SIMD),
+            .MASK(MASK),
+            .PATTERN(PATTERN),
+            .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
+            .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
+            .IS_CLK_INVERTED(IS_CLK_INVERTED),
+            .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
+            .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
+        ) _TECHMAP_REPLACE_ (
+            .ACOUT(ACOUT),
+            .BCOUT(BCOUT),
+            .CARRYCASCOUT(CARRYCASCOUT),
+            .CARRYOUT(CARRYOUT),
+            .MULTSIGNOUT(MULTSIGNOUT),
+            .OVERFLOW(OVERFLOW),
+            .P(oP),
+            .PATTERNBDETECT(PATTERNBDETECT),
+            .PATTERNDETECT(PATTERNDETECT),
+            .PCOUT(oPCOUT),
+            .UNDERFLOW(UNDERFLOW),
+            .A(iA),
+            .ACIN(ACIN),
+            .ALUMODE(ALUMODE),
+            .B(iB),
+            .BCIN(BCIN),
+            .C(iC),
+            .CARRYCASCIN(CARRYCASCIN),
+            .CARRYIN(CARRYIN),
+            .CARRYINSEL(CARRYINSEL),
+            .CEA1(CEA1),
+            .CEA2(CEA2),
+            .CEAD(CEAD),
+            .CEALUMODE(CEALUMODE),
+            .CEB1(CEB1),
+            .CEB2(CEB2),
+            .CEC(CEC),
+            .CECARRYIN(CECARRYIN),
+            .CECTRL(CECTRL),
+            .CED(CED),
+            .CEINMODE(CEINMODE),
+            .CEM(CEM),
+            .CEP(CEP),
+            .CLK(CLK),
+            .D(iD),
+            .INMODE(INMODE),
+            .MULTSIGNIN(MULTSIGNIN),
+            .OPMODE(OPMODE),
+            .PCIN(PCIN),
+            .RSTA(RSTA),
+            .RSTALLCARRYIN(RSTALLCARRYIN),
+            .RSTALUMODE(RSTALUMODE),
+            .RSTB(RSTB),
+            .RSTC(RSTC),
+            .RSTCTRL(RSTCTRL),
+            .RSTD(RSTD),
+            .RSTINMODE(RSTINMODE),
+            .RSTM(RSTM),
+            .RSTP(RSTP)
+        );
+    end
     else
-        wire _TECHMAP_FAIL_ = 1;
+        $error("Invalid DSP48E1 configuration");
 	endgenerate
 endmodule
-- 
cgit v1.2.3


From d0b202c58d45145e79243caac55f155328008d39 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 12:05:14 -0700
Subject: Add no MULT no DPORT config

---
 techlibs/xilinx/abc_map.v | 218 +++++++++++++++++++---------------------------
 1 file changed, 91 insertions(+), 127 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 27133fc1e..6e36417e2 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -207,51 +207,8 @@ module DSP48E1 (
     parameter _TECHMAP_CELLTYPE_ = "";
     localparam techmap_guard = (_TECHMAP_CELLTYPE_ != "");
 
-    generate
-    if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-        wire [29:0] iA;
-        wire [17:0] iB;
-        wire [47:0] iC;
-        wire [24:0] iD;
-
-        wire pA, pB, pC, pD, pAD, pM, pP;
-        wire [47:0] oP, oPCOUT;
-
-		// Disconnect the A-input if MREG is enabled, since
-		//   combinatorial path is broken
-        if (AREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A;
-        else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
-        if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B;
-        else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
-        if (CREG == 0 && PREG == 0)
-            assign iC = C;
-        else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
-        if (DREG == 0)
-            assign iD = D;
-        else if (techmap_guard)
-			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
-        if (ADREG == 1 && techmap_guard)
-			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
-		if (PREG == 0) begin
-			if (MREG == 1)
-				\$__ABC_DSP48E1_REG rM (.Q(pM));
-		end
-		else
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
-
-        \$__ABC_DSP48E1_MULT_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
-        );
-        \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
-        );
-
-        \$__ABC_DSP48E1_MULT #(
+`define DSP48E1_inst(__CELL__) """
+__CELL__ #(
             .ACASCREG(ACASCREG),
             .ADREG(ADREG),
             .ALUMODEREG(ALUMODEREG),
@@ -333,6 +290,53 @@ module DSP48E1 (
             .RSTM(RSTM),
             .RSTP(RSTP)
         );
+"""
+
+    generate
+    if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
+        wire [29:0] iA;
+        wire [17:0] iB;
+        wire [47:0] iC;
+        wire [24:0] iD;
+
+        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire [47:0] oP, oPCOUT;
+
+		// Disconnect the A-input if MREG is enabled, since
+		//   combinatorial path is broken
+        if (AREG == 0 && MREG == 0 && PREG == 0)
+            assign iA = A;
+        else
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+        if (BREG == 0 && MREG == 0 && PREG == 0)
+            assign iB = B;
+        else
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+        if (CREG == 0 && PREG == 0)
+            assign iC = C;
+        else
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+        if (DREG == 0)
+            assign iD = D;
+        else if (techmap_guard)
+			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        if (ADREG == 1 && techmap_guard)
+			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+		if (PREG == 0) begin
+			if (MREG == 1)
+				\$__ABC_DSP48E1_REG rM (.Q(pM));
+		end
+		else
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
+
+        \$__ABC_DSP48E1_MULT_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+        );
+        \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        );
+
+        `DSP48E1_inst(\$__ABC_DSP48E1_MULT )
     end
     else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
         wire [29:0] iA;
@@ -345,7 +349,7 @@ module DSP48E1 (
 
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
-        if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 1)
+        if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A;
         else
             \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
@@ -377,88 +381,48 @@ module DSP48E1 (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        \$__ABC_DSP48E1_MULT_DPORT #(
-            .ACASCREG(ACASCREG),
-            .ADREG(ADREG),
-            .ALUMODEREG(ALUMODEREG),
-            .AREG(AREG),
-            .AUTORESET_PATDET(AUTORESET_PATDET),
-            .A_INPUT(A_INPUT),
-            .BCASCREG(BCASCREG),
-            .BREG(BREG),
-            .B_INPUT(B_INPUT),
-            .CARRYINREG(CARRYINREG),
-            .CARRYINSELREG(CARRYINSELREG),
-            .CREG(CREG),
-            .DREG(DREG),
-            .INMODEREG(INMODEREG),
-            .MREG(MREG),
-            .OPMODEREG(OPMODEREG),
-            .PREG(PREG),
-            .SEL_MASK(SEL_MASK),
-            .SEL_PATTERN(SEL_PATTERN),
-            .USE_DPORT(USE_DPORT),
-            .USE_MULT(USE_MULT),
-            .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
-            .USE_SIMD(USE_SIMD),
-            .MASK(MASK),
-            .PATTERN(PATTERN),
-            .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
-            .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
-            .IS_CLK_INVERTED(IS_CLK_INVERTED),
-            .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
-            .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
-        ) _TECHMAP_REPLACE_ (
-            .ACOUT(ACOUT),
-            .BCOUT(BCOUT),
-            .CARRYCASCOUT(CARRYCASCOUT),
-            .CARRYOUT(CARRYOUT),
-            .MULTSIGNOUT(MULTSIGNOUT),
-            .OVERFLOW(OVERFLOW),
-            .P(oP),
-            .PATTERNBDETECT(PATTERNBDETECT),
-            .PATTERNDETECT(PATTERNDETECT),
-            .PCOUT(oPCOUT),
-            .UNDERFLOW(UNDERFLOW),
-            .A(iA),
-            .ACIN(ACIN),
-            .ALUMODE(ALUMODE),
-            .B(iB),
-            .BCIN(BCIN),
-            .C(iC),
-            .CARRYCASCIN(CARRYCASCIN),
-            .CARRYIN(CARRYIN),
-            .CARRYINSEL(CARRYINSEL),
-            .CEA1(CEA1),
-            .CEA2(CEA2),
-            .CEAD(CEAD),
-            .CEALUMODE(CEALUMODE),
-            .CEB1(CEB1),
-            .CEB2(CEB2),
-            .CEC(CEC),
-            .CECARRYIN(CECARRYIN),
-            .CECTRL(CECTRL),
-            .CED(CED),
-            .CEINMODE(CEINMODE),
-            .CEM(CEM),
-            .CEP(CEP),
-            .CLK(CLK),
-            .D(iD),
-            .INMODE(INMODE),
-            .MULTSIGNIN(MULTSIGNIN),
-            .OPMODE(OPMODE),
-            .PCIN(PCIN),
-            .RSTA(RSTA),
-            .RSTALLCARRYIN(RSTALLCARRYIN),
-            .RSTALUMODE(RSTALUMODE),
-            .RSTB(RSTB),
-            .RSTC(RSTC),
-            .RSTCTRL(RSTCTRL),
-            .RSTD(RSTD),
-            .RSTINMODE(RSTINMODE),
-            .RSTM(RSTM),
-            .RSTP(RSTP)
+        `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT )
+    end
+    else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
+        wire [29:0] iA;
+        wire [17:0] iB;
+        wire [47:0] iC;
+        wire [24:0] iD;
+
+        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire [47:0] oP, oPCOUT;
+
+		// Disconnect the A-input if MREG is enabled, since
+		//   combinatorial path is broken
+        if (AREG == 0 && PREG == 0)
+            assign iA = A;
+        else
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+        if (BREG == 0 && PREG == 0)
+            assign iB = B;
+        else
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+        if (CREG == 0 && PREG == 0)
+            assign iC = C;
+        else
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+        if (MREG == 1 && techmap_guard)
+			$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+        if (DREG == 1 && techmap_guard)
+			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        if (ADREG == 1 && techmap_guard)
+			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+		if (PREG == 1)
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
+
+        \$__ABC_DSP48E1_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
         );
+        \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        );
+
+        `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT )
     end
     else
         $error("Invalid DSP48E1 configuration");
-- 
cgit v1.2.3


From 681be20ca219fc64e2bf0f9d2c24937f98903455 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 17:07:18 -0700
Subject: Add `undef DSP48E1_INST

---
 techlibs/xilinx/abc_map.v | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 6e36417e2..31fd79861 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -207,7 +207,7 @@ module DSP48E1 (
     parameter _TECHMAP_CELLTYPE_ = "";
     localparam techmap_guard = (_TECHMAP_CELLTYPE_ != "");
 
-`define DSP48E1_inst(__CELL__) """
+`define DSP48E1_INST(__CELL__) """
 __CELL__ #(
             .ACASCREG(ACASCREG),
             .ADREG(ADREG),
@@ -336,7 +336,7 @@ __CELL__ #(
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_inst(\$__ABC_DSP48E1_MULT )
+        `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
     end
     else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
         wire [29:0] iA;
@@ -381,7 +381,7 @@ __CELL__ #(
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT )
+        `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT )
     end
     else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
         wire [29:0] iA;
@@ -422,9 +422,10 @@ __CELL__ #(
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT )
+        `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT )
     end
     else
         $error("Invalid DSP48E1 configuration");
 	endgenerate
+	`undef DSP48E1_INST
 endmodule
-- 
cgit v1.2.3


From 25e0f0c3765060b7ce25a0c58bc926b90dba304d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 18 Sep 2019 12:19:16 -0700
Subject: Fix copy-paste

---
 techlibs/xilinx/abc_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 31fd79861..1f369fc19 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -381,7 +381,7 @@ __CELL__ #(
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT )
+        `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
     end
     else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
         wire [29:0] iA;
@@ -422,7 +422,7 @@ __CELL__ #(
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT )
+        `DSP48E1_INST(\$__ABC_DSP48E1 )
     end
     else
         $error("Invalid DSP48E1 configuration");
-- 
cgit v1.2.3


From 595fb611a5179f280452b5af356f652648eb3e2d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 15:58:01 -0700
Subject: Use (* techmap_autopurge *) to suppress techmap warnings

---
 techlibs/xilinx/abc_map.v | 110 +++++++++++++++++++++++-----------------------
 1 file changed, 55 insertions(+), 55 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 1f369fc19..f23ec6463 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -22,11 +22,11 @@
 
 module RAM32X1D (
   output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A0, A1, A2, A3, A4,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+  (* techmap_autopurge *) input  D,
+  (* techmap_autopurge *) input  WCLK,
+  (* techmap_autopurge *) input  WE,
+  (* techmap_autopurge *) input  A0, A1, A2, A3, A4,
+  (* techmap_autopurge *) input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
   parameter INIT = 32'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
@@ -45,11 +45,11 @@ endmodule
 
 module RAM64X1D (
   output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A0, A1, A2, A3, A4, A5,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+  (* techmap_autopurge *) input  D,
+  (* techmap_autopurge *) input  WCLK,
+  (* techmap_autopurge *) input  WE,
+  (* techmap_autopurge *) input  A0, A1, A2, A3, A4, A5,
+  (* techmap_autopurge *) input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
@@ -68,10 +68,10 @@ endmodule
 
 module RAM128X1D (
   output       DPO, SPO,
-  input        D,
-  input        WCLK,
-  input        WE,
-  input  [6:0] A, DPRA
+  (* techmap_autopurge *) input        D,
+  (* techmap_autopurge *) input        WCLK,
+  (* techmap_autopurge *) input        WE,
+  (* techmap_autopurge *) input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
@@ -90,7 +90,7 @@ endmodule
 
 module SRL16E (
   output Q,
-  input A0, A1, A2, A3, CE, CLK, D
+  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -107,8 +107,8 @@ endmodule
 module SRLC32E (
   output Q,
   output Q31,
-  input [4:0] A,
-  input CE, CLK, D
+  (* techmap_autopurge *) input [4:0] A,
+  (* techmap_autopurge *) input CE, CLK, D
 );
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -134,44 +134,44 @@ module DSP48E1 (
     output PATTERNDETECT,
     output [47:0] PCOUT,
     output UNDERFLOW,
-    input signed [29:0] A,
-    input [29:0] ACIN,
-    input [3:0] ALUMODE,
-    input signed [17:0] B,
-    input [17:0] BCIN,
-    input [47:0] C,
-    input CARRYCASCIN,
-    input CARRYIN,
-    input [2:0] CARRYINSEL,
-    input CEA1,
-    input CEA2,
-    input CEAD,
-    input CEALUMODE,
-    input CEB1,
-    input CEB2,
-    input CEC,
-    input CECARRYIN,
-    input CECTRL,
-    input CED,
-    input CEINMODE,
-    input CEM,
-    input CEP,
-    input CLK,
-    input [24:0] D,
-    input [4:0] INMODE,
-    input MULTSIGNIN,
-    input [6:0] OPMODE,
-    input [47:0] PCIN,
-    input RSTA,
-    input RSTALLCARRYIN,
-    input RSTALUMODE,
-    input RSTB,
-    input RSTC,
-    input RSTCTRL,
-    input RSTD,
-    input RSTINMODE,
-    input RSTM,
-    input RSTP
+    (* techmap_autopurge *) input signed [29:0] A,
+    (* techmap_autopurge *) input [29:0] ACIN,
+    (* techmap_autopurge *) input [3:0] ALUMODE,
+    (* techmap_autopurge *) input signed [17:0] B,
+    (* techmap_autopurge *) input [17:0] BCIN,
+    (* techmap_autopurge *) input [47:0] C,
+    (* techmap_autopurge *) input CARRYCASCIN,
+    (* techmap_autopurge *) input CARRYIN,
+    (* techmap_autopurge *) input [2:0] CARRYINSEL,
+    (* techmap_autopurge *) input CEA1,
+    (* techmap_autopurge *) input CEA2,
+    (* techmap_autopurge *) input CEAD,
+    (* techmap_autopurge *) input CEALUMODE,
+    (* techmap_autopurge *) input CEB1,
+    (* techmap_autopurge *) input CEB2,
+    (* techmap_autopurge *) input CEC,
+    (* techmap_autopurge *) input CECARRYIN,
+    (* techmap_autopurge *) input CECTRL,
+    (* techmap_autopurge *) input CED,
+    (* techmap_autopurge *) input CEINMODE,
+    (* techmap_autopurge *) input CEM,
+    (* techmap_autopurge *) input CEP,
+    (* techmap_autopurge *) input CLK,
+    (* techmap_autopurge *) input [24:0] D,
+    (* techmap_autopurge *) input [4:0] INMODE,
+    (* techmap_autopurge *) input MULTSIGNIN,
+    (* techmap_autopurge *) input [6:0] OPMODE,
+    (* techmap_autopurge *) input [47:0] PCIN,
+    (* techmap_autopurge *) input RSTA,
+    (* techmap_autopurge *) input RSTALLCARRYIN,
+    (* techmap_autopurge *) input RSTALUMODE,
+    (* techmap_autopurge *) input RSTB,
+    (* techmap_autopurge *) input RSTC,
+    (* techmap_autopurge *) input RSTCTRL,
+    (* techmap_autopurge *) input RSTD,
+    (* techmap_autopurge *) input RSTINMODE,
+    (* techmap_autopurge *) input RSTM,
+    (* techmap_autopurge *) input RSTP
 );
     parameter integer ACASCREG = 1;
     parameter integer ADREG = 1;
-- 
cgit v1.2.3


From 5ca25b0c59d47e26c7bf119c47b4e73054fafbc8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 16:27:14 -0700
Subject: Suppress $anyseq warnings

---
 techlibs/xilinx/abc_map.v | 47 ++++++++++++++++++++++++++++++++---------------
 1 file changed, 32 insertions(+), 15 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index f23ec6463..1b7900af8 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -305,29 +305,36 @@ __CELL__ #(
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A;
+            assign iA = A, pA = 1'bx;
         else
             \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B;
+            assign iB = B, pB = 1'bx;
         else
             \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
-            assign iC = C;
+            assign iC = C, pC = 1'bx;
         else
             \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
 			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        assign pD = 1'bx;
         if (ADREG == 1 && techmap_guard)
-			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+            $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+        assign pAD = 1'bx;
 		if (PREG == 0) begin
+            assign pP = 1'bx;
 			if (MREG == 1)
 				\$__ABC_DSP48E1_REG rM (.Q(pM));
+            else
+                assign pM = 1'bx;
 		end
-		else
+        else begin
             \$__ABC_DSP48E1_REG rP (.Q(pP));
+            assign pM = 1'bx;
+        end
 
         \$__ABC_DSP48E1_MULT_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
@@ -350,26 +357,31 @@ __CELL__ #(
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A;
+            assign iA = A, pA = 1'bx;
         else
             \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B;
+            assign iB = B, pB = 1'bx;
         else
             \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
-            assign iC = C;
+            assign iC = C, pC = 1'bx;
         else
             \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0 && ADREG == 0)
-            assign iD = D;
+            assign iD = D, pD = 1'bx;
         else
             \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
 		if (PREG == 0) begin
 			if (MREG == 1)
 				\$__ABC_DSP48E1_REG rM (.Q(pM));
-            else if (ADREG == 1)
-                \$__ABC_DSP48E1_REG rAD (.Q(pAD));
+            else begin
+                assign pM = 1'bx;
+                if (ADREG == 1)
+                    \$__ABC_DSP48E1_REG rAD (.Q(pAD));
+                else
+                    assign pAD = 1'bx;
+            end
 		end
 		else
             \$__ABC_DSP48E1_REG rP (.Q(pP));
@@ -395,25 +407,30 @@ __CELL__ #(
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && PREG == 0)
-            assign iA = A;
+            assign iA = A, pA = 1'bx;
         else
             \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && PREG == 0)
-            assign iB = B;
+            assign iB = B, pB = 1'bx;
         else
             \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
-            assign iC = C;
+            assign iC = C, pC = 1'bx;
         else
             \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
         if (MREG == 1 && techmap_guard)
-			$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+        assign pM = 1'bx;
         if (DREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        assign pD = 1'bx;
         if (ADREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+        assign pAD = 1'bx;
 		if (PREG == 1)
             \$__ABC_DSP48E1_REG rP (.Q(pP));
+        else
+            assign pP = 1'bx;
 
         \$__ABC_DSP48E1_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
-- 
cgit v1.2.3


From 41256f48a5f3231e231cbdf9380a26128f272044 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 18:33:29 -0700
Subject: Different approach to timing

---
 techlibs/xilinx/abc_map.v | 141 ++++++++++++++++++++++++++--------------------
 1 file changed, 80 insertions(+), 61 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 1b7900af8..124ce6d8f 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -299,49 +299,60 @@ __CELL__ #(
         wire [47:0] iC;
         wire [24:0] iD;
 
-        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire pAP, pBP, pCP, pDP, pADP, pMP, pPP;
+        wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
         wire [47:0] oP, oPCOUT;
 
-		// Disconnect the A-input if MREG is enabled, since
-		//   combinatorial path is broken
+        // Disconnect the A-input if MREG is enabled, since
+        //   combinatorial path is broken
         if (AREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A, pA = 1'bx;
+            assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC_DSP48E1_MULT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT));
         if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B, pB = 1'bx;
+            assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC_DSP48E1_MULT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT));
         if (CREG == 0 && PREG == 0)
-            assign iC = C, pC = 1'bx;
+            assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC_DSP48E1_MULT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT));
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
-			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
-        assign pD = 1'bx;
+            $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        assign pDP = 1'bx, pDPCOUT = 1'bx;
         if (ADREG == 1 && techmap_guard)
             $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
-        assign pAD = 1'bx;
+        assign pADP = 1'bx, pADPCOUT = 1'bx;
 		if (PREG == 0) begin
-            assign pP = 1'bx;
 			if (MREG == 1)
-				\$__ABC_DSP48E1_REG rM (.Q(pM));
+				\$__ABC_DSP48E1_MULT_MREG rM (.P(pMP), .PCOUT(pMPCOUT));
             else
-                assign pM = 1'bx;
+                assign pMP = 1'bx, pMPCOUT = 1'bx;
+            assign pPP = 1'bx, pPPCOUT = 1'bx;
 		end
         else begin
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
-            assign pM = 1'bx;
+            assign pMP = 1'bx, pMPCOUT = 1'bx;
+            \$__ABC_DSP48E1_MULT_PREG rP (.P(pPP), .PCOUT(pPPCOUT));
         end
 
-        \$__ABC_DSP48E1_MULT_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
-        );
-        \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
-        );
+        if (MREG == 0 && PREG == 0) begin
+            \$__ABC_DSP48E1_MUX muxP (
+                .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P)
+            );
+            \$__ABC_DSP48E1_MUX muxPCOUT (
+                .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT)
+            );
+        end
+        else begin
+            \$__ABC_DSP48E1_MUX muxP (
+                .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(1'bx), .Pq(pPP), .O(P)
+            );
+            \$__ABC_DSP48E1_MUX muxPCOUT (
+                .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(1'bx), .Pq(pPPCOUT), .O(PCOUT)
+            );
+        end
 
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
     end
@@ -351,46 +362,53 @@ __CELL__ #(
         wire [47:0] iC;
         wire [24:0] iD;
 
-        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire pAP, pBP, pCP, pDP, pADP, pMP, pPP;
+        wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
         wire [47:0] oP, oPCOUT;
 
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A, pA = 1'bx;
+            assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC_DSP48E1_MULT_DPORT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT));
         if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B, pB = 1'bx;
+            assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC_DSP48E1_MULT_DPORT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT));
         if (CREG == 0 && PREG == 0)
-            assign iC = C, pC = 1'bx;
+            assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC_DSP48E1_MULT_DPORT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT));
         if (DREG == 0 && ADREG == 0)
-            assign iD = D, pD = 1'bx;
+            assign iD = D, pDP = 1'bx, pDPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
+            \$__ABC_DSP48E1_MULT_DPORT_DREG rD (.I(D), .O(iD), .P(pDP), .PCOUT(pDPCOUT));
 		if (PREG == 0) begin
-			if (MREG == 1)
-				\$__ABC_DSP48E1_REG rM (.Q(pM));
+            if (MREG == 1) begin
+                assign pADP = 1'bx, pADPCOUT = 1'bx;
+				\$__ABC_DSP48E1_MULT_DPORT_MREG rM (.P(pMP), .PCOUT(pMPCOUT));
+            end
             else begin
-                assign pM = 1'bx;
                 if (ADREG == 1)
-                    \$__ABC_DSP48E1_REG rAD (.Q(pAD));
+                    \$__ABC_DSP48E1_MULT_DPORT_ADPREG rAD (.P(pADP), .PCOUT(pADPCOUT));
                 else
-                    assign pAD = 1'bx;
+                    assign pADP = 1'bx, pADPCOUT = 1'bx;
+                assign pMP = 1'bx, pMPCOUT = 1'bx;
             end
+            assign pPP = 1'bx, pPPCOUT = 1'bx;
 		end
-		else
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
+        else begin
+            assign pADP = 1'bx, pADPCOUT = 1'bx;
+            assign pMP = 1'bx, pMPCOUT = 1'bx;
+            \$__ABC_DSP48E1_MULT_DPORT_PREG rP (.P(pPP), .PCOUT(pPPCOUT));
+        end
 
-        \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+        \$__ABC_DSP48E1_MUX muxP (
+            .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P)
         );
-        \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        \$__ABC_DSP48E1_MUX muxPCOUT (
+            .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
@@ -401,42 +419,43 @@ __CELL__ #(
         wire [47:0] iC;
         wire [24:0] iD;
 
-        wire pA, pB, pC, pD, pAD, pM, pP;
+        wire pAP, pBP, pCP, pDP, pADP, pMP, pPP;
+        wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
         wire [47:0] oP, oPCOUT;
 
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && PREG == 0)
-            assign iA = A, pA = 1'bx;
+            assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC_DSP48E1_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT));
         if (BREG == 0 && PREG == 0)
-            assign iB = B, pB = 1'bx;
+            assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC_DSP48E1_BREG rB (.I(B), .O(iB), .P(pB), .PCOUT(pBPCOUT));
         if (CREG == 0 && PREG == 0)
-            assign iC = C, pC = 1'bx;
+            assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
-        if (MREG == 1 && techmap_guard)
-            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
-        assign pM = 1'bx;
+            \$__ABC_DSP48E1_CREG rC (.I(C), .O(iC), .P(pC), .PCOUT(pCPCOUT));
         if (DREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
-        assign pD = 1'bx;
+        assign iD = 25'bx, pDP = 1'bx, pDPCOUT = 1'bx;
         if (ADREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
-        assign pAD = 1'bx;
+        assign pADP = 1'bx, pADPCOUT = 1'bx;
+        if (MREG == 1 && techmap_guard)
+            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+        assign pMP = 1'bx, pMPCOUT = 1'bx;
 		if (PREG == 1)
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
+            \$__ABC_DSP48E1_PREG rP (.P(pPP), .P(pPCOUT));
         else
-            assign pP = 1'bx;
+            assign pPP = 1'bx, pPPCOUT = 1'bx;
 
-        \$__ABC_DSP48E1_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+        \$__ABC_DSP48E1_MUX muxP (
+            .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P)
         );
-        \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        \$__ABC_DSP48E1_MUX muxPCOUT (
+            .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1 )
-- 
cgit v1.2.3


From 362a803779ac1a8a3af1e4991b80b0c4c71e02ff Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 18:33:38 -0700
Subject: Revert "Different approach to timing"

This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
---
 techlibs/xilinx/abc_map.v | 141 ++++++++++++++++++++--------------------------
 1 file changed, 61 insertions(+), 80 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 124ce6d8f..1b7900af8 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -299,60 +299,49 @@ __CELL__ #(
         wire [47:0] iC;
         wire [24:0] iD;
 
-        wire pAP, pBP, pCP, pDP, pADP, pMP, pPP;
-        wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
+        wire pA, pB, pC, pD, pAD, pM, pP;
         wire [47:0] oP, oPCOUT;
 
-        // Disconnect the A-input if MREG is enabled, since
-        //   combinatorial path is broken
+		// Disconnect the A-input if MREG is enabled, since
+		//   combinatorial path is broken
         if (AREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx;
+            assign iA = A, pA = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT));
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx;
+            assign iB = B, pB = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT));
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
-            assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx;
+            assign iC = C, pC = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT));
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
-            $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
-        assign pDP = 1'bx, pDPCOUT = 1'bx;
+			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        assign pD = 1'bx;
         if (ADREG == 1 && techmap_guard)
             $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
-        assign pADP = 1'bx, pADPCOUT = 1'bx;
+        assign pAD = 1'bx;
 		if (PREG == 0) begin
+            assign pP = 1'bx;
 			if (MREG == 1)
-				\$__ABC_DSP48E1_MULT_MREG rM (.P(pMP), .PCOUT(pMPCOUT));
+				\$__ABC_DSP48E1_REG rM (.Q(pM));
             else
-                assign pMP = 1'bx, pMPCOUT = 1'bx;
-            assign pPP = 1'bx, pPPCOUT = 1'bx;
+                assign pM = 1'bx;
 		end
         else begin
-            assign pMP = 1'bx, pMPCOUT = 1'bx;
-            \$__ABC_DSP48E1_MULT_PREG rP (.P(pPP), .PCOUT(pPPCOUT));
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
+            assign pM = 1'bx;
         end
 
-        if (MREG == 0 && PREG == 0) begin
-            \$__ABC_DSP48E1_MUX muxP (
-                .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P)
-            );
-            \$__ABC_DSP48E1_MUX muxPCOUT (
-                .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT)
-            );
-        end
-        else begin
-            \$__ABC_DSP48E1_MUX muxP (
-                .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(1'bx), .Pq(pPP), .O(P)
-            );
-            \$__ABC_DSP48E1_MUX muxPCOUT (
-                .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(1'bx), .Pq(pPPCOUT), .O(PCOUT)
-            );
-        end
+        \$__ABC_DSP48E1_MULT_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+        );
+        \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+        );
 
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
     end
@@ -362,53 +351,46 @@ __CELL__ #(
         wire [47:0] iC;
         wire [24:0] iD;
 
-        wire pAP, pBP, pCP, pDP, pADP, pMP, pPP;
-        wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
+        wire pA, pB, pC, pD, pAD, pM, pP;
         wire [47:0] oP, oPCOUT;
 
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
-            assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx;
+            assign iA = A, pA = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_DPORT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT));
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
-            assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx;
+            assign iB = B, pB = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_DPORT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT));
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
-            assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx;
+            assign iC = C, pC = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_DPORT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT));
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0 && ADREG == 0)
-            assign iD = D, pDP = 1'bx, pDPCOUT = 1'bx;
+            assign iD = D, pD = 1'bx;
         else
-            \$__ABC_DSP48E1_MULT_DPORT_DREG rD (.I(D), .O(iD), .P(pDP), .PCOUT(pDPCOUT));
+            \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
 		if (PREG == 0) begin
-            if (MREG == 1) begin
-                assign pADP = 1'bx, pADPCOUT = 1'bx;
-				\$__ABC_DSP48E1_MULT_DPORT_MREG rM (.P(pMP), .PCOUT(pMPCOUT));
-            end
+			if (MREG == 1)
+				\$__ABC_DSP48E1_REG rM (.Q(pM));
             else begin
+                assign pM = 1'bx;
                 if (ADREG == 1)
-                    \$__ABC_DSP48E1_MULT_DPORT_ADPREG rAD (.P(pADP), .PCOUT(pADPCOUT));
+                    \$__ABC_DSP48E1_REG rAD (.Q(pAD));
                 else
-                    assign pADP = 1'bx, pADPCOUT = 1'bx;
-                assign pMP = 1'bx, pMPCOUT = 1'bx;
+                    assign pAD = 1'bx;
             end
-            assign pPP = 1'bx, pPPCOUT = 1'bx;
 		end
-        else begin
-            assign pADP = 1'bx, pADPCOUT = 1'bx;
-            assign pMP = 1'bx, pMPCOUT = 1'bx;
-            \$__ABC_DSP48E1_MULT_DPORT_PREG rP (.P(pPP), .PCOUT(pPPCOUT));
-        end
+		else
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
 
-        \$__ABC_DSP48E1_MUX muxP (
-            .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P)
+        \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
         );
-        \$__ABC_DSP48E1_MUX muxPCOUT (
-            .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT)
+        \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
@@ -419,43 +401,42 @@ __CELL__ #(
         wire [47:0] iC;
         wire [24:0] iD;
 
-        wire pAP, pBP, pCP, pDP, pADP, pMP, pPP;
-        wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT;
+        wire pA, pB, pC, pD, pAD, pM, pP;
         wire [47:0] oP, oPCOUT;
 
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && PREG == 0)
-            assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx;
+            assign iA = A, pA = 1'bx;
         else
-            \$__ABC_DSP48E1_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT));
+            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && PREG == 0)
-            assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx;
+            assign iB = B, pB = 1'bx;
         else
-            \$__ABC_DSP48E1_BREG rB (.I(B), .O(iB), .P(pB), .PCOUT(pBPCOUT));
+            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
-            assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx;
+            assign iC = C, pC = 1'bx;
         else
-            \$__ABC_DSP48E1_CREG rC (.I(C), .O(iC), .P(pC), .PCOUT(pCPCOUT));
+            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+        if (MREG == 1 && techmap_guard)
+            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+        assign pM = 1'bx;
         if (DREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
-        assign iD = 25'bx, pDP = 1'bx, pDPCOUT = 1'bx;
+        assign pD = 1'bx;
         if (ADREG == 1 && techmap_guard)
 			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
-        assign pADP = 1'bx, pADPCOUT = 1'bx;
-        if (MREG == 1 && techmap_guard)
-            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
-        assign pMP = 1'bx, pMPCOUT = 1'bx;
+        assign pAD = 1'bx;
 		if (PREG == 1)
-            \$__ABC_DSP48E1_PREG rP (.P(pPP), .P(pPCOUT));
+            \$__ABC_DSP48E1_REG rP (.Q(pP));
         else
-            assign pPP = 1'bx, pPPCOUT = 1'bx;
+            assign pP = 1'bx;
 
-        \$__ABC_DSP48E1_MUX muxP (
-            .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P)
+        \$__ABC_DSP48E1_P_MUX muxP (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
         );
-        \$__ABC_DSP48E1_MUX muxPCOUT (
-            .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT)
+        \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1 )
-- 
cgit v1.2.3


From e09f80479e6d16cf95c26e406bf06d81b94231f4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 18:59:28 -0700
Subject: Fix DSP48E1 timing by breaking P path if MREG or PREG

---
 techlibs/xilinx/abc_map.v | 57 ++++++++++++++++++++++-------------------------
 1 file changed, 27 insertions(+), 30 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 1b7900af8..01307fcf2 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -292,16 +292,17 @@ __CELL__ #(
         );
 """
 
-    generate
-    if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-        wire [29:0] iA;
-        wire [17:0] iB;
-        wire [47:0] iC;
-        wire [24:0] iD;
+    wire [29:0] iA;
+    wire [17:0] iB;
+    wire [47:0] iC;
+    wire [24:0] iD;
 
-        wire pA, pB, pC, pD, pAD, pM, pP;
-        wire [47:0] oP, oPCOUT;
+    wire pA, pB, pC, pD, pAD, pM, pP;
+    wire [47:0] oP, mP;
+    wire [47:0] oPCOUT, mPCOUT;
 
+    generate
+    if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && MREG == 0 && PREG == 0)
@@ -336,24 +337,20 @@ __CELL__ #(
             assign pM = 1'bx;
         end
 
+        if (MREG == 0 && PREG == 0)
+            assign mP = oP, mPCOUT = oPCOUT;
+        else
+            assign mP = 1'bx, mPCOUT = 1'bx;
         \$__ABC_DSP48E1_MULT_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
         \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
     end
     else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
-        wire [29:0] iA;
-        wire [17:0] iB;
-        wire [47:0] iC;
-        wire [24:0] iD;
-
-        wire pA, pB, pC, pD, pAD, pM, pP;
-        wire [47:0] oP, oPCOUT;
-
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
@@ -386,24 +383,20 @@ __CELL__ #(
 		else
             \$__ABC_DSP48E1_REG rP (.Q(pP));
 
+        if (MREG == 0 && PREG == 0)
+            assign mP = oP, mPCOUT = oPCOUT;
+        else
+            assign mP = 1'bx, mPCOUT = 1'bx;
         \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
         \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
     end
     else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
-        wire [29:0] iA;
-        wire [17:0] iB;
-        wire [47:0] iC;
-        wire [24:0] iD;
-
-        wire pA, pB, pC, pD, pAD, pM, pP;
-        wire [47:0] oP, oPCOUT;
-
 		// Disconnect the A-input if MREG is enabled, since
 		//   combinatorial path is broken
         if (AREG == 0 && PREG == 0)
@@ -432,11 +425,15 @@ __CELL__ #(
         else
             assign pP = 1'bx;
 
+        if (MREG == 0 && PREG == 0)
+            assign mP = oP, mPCOUT = oPCOUT;
+        else
+            assign mP = 1'bx, mPCOUT = 1'bx;
         \$__ABC_DSP48E1_P_MUX muxP (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P)
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
         \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
-            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
+            .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
         `DSP48E1_INST(\$__ABC_DSP48E1 )
-- 
cgit v1.2.3


From 1602516a8b2ebd432528e9ba39a00db4e6edc081 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 19:37:45 -0700
Subject: $__ABC_REG to have WIDTH parameter

---
 techlibs/xilinx/abc_map.v | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 01307fcf2..423da3fdb 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -308,15 +308,15 @@ __CELL__ #(
         if (AREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
@@ -328,12 +328,12 @@ __CELL__ #(
 		if (PREG == 0) begin
             assign pP = 1'bx;
 			if (MREG == 1)
-				\$__ABC_DSP48E1_REG rM (.Q(pM));
+				\$__ABC_REG rM (.Q(pM));
             else
                 assign pM = 1'bx;
 		end
         else begin
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
+            \$__ABC_REG rP (.Q(pP));
             assign pM = 1'bx;
         end
 
@@ -356,32 +356,32 @@ __CELL__ #(
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0 && ADREG == 0)
             assign iD = D, pD = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD));
+            \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
 		if (PREG == 0) begin
 			if (MREG == 1)
-				\$__ABC_DSP48E1_REG rM (.Q(pM));
+				\$__ABC_REG rM (.Q(pM));
             else begin
                 assign pM = 1'bx;
                 if (ADREG == 1)
-                    \$__ABC_DSP48E1_REG rAD (.Q(pAD));
+                    \$__ABC_REG rAD (.Q(pAD));
                 else
                     assign pAD = 1'bx;
             end
 		end
 		else
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
+            \$__ABC_REG rP (.Q(pP));
 
         if (MREG == 0 && PREG == 0)
             assign mP = oP, mPCOUT = oPCOUT;
@@ -402,15 +402,15 @@ __CELL__ #(
         if (AREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA));
+            \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB));
+            \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC));
+            \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (MREG == 1 && techmap_guard)
             $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
         assign pM = 1'bx;
@@ -421,7 +421,7 @@ __CELL__ #(
 			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
         assign pAD = 1'bx;
 		if (PREG == 1)
-            \$__ABC_DSP48E1_REG rP (.Q(pP));
+            \$__ABC_REG rP (.Q(pP));
         else
             assign pP = 1'bx;
 
-- 
cgit v1.2.3


From 691686f92c011a94a649ae7ecc2f4f22b758fc12 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 20:04:52 -0700
Subject: Tidy up, fix undriven

---
 techlibs/xilinx/abc_map.v | 66 ++++++++++++++++++++++++-----------------------
 1 file changed, 34 insertions(+), 32 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 423da3fdb..9d78725df 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -303,8 +303,8 @@ __CELL__ #(
 
     generate
     if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-		// Disconnect the A-input if MREG is enabled, since
-		//   combinatorial path is broken
+        // Disconnect the A-input if MREG is enabled, since
+        //   combinatorial path is broken
         if (AREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
@@ -320,21 +320,20 @@ __CELL__ #(
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
-			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+        $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
         assign pD = 1'bx;
         if (ADREG == 1 && techmap_guard)
             $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
         assign pAD = 1'bx;
-		if (PREG == 0) begin
-            assign pP = 1'bx;
-			if (MREG == 1)
-				\$__ABC_REG rM (.Q(pM));
-            else
-                assign pM = 1'bx;
-		end
-        else begin
-            \$__ABC_REG rP (.Q(pP));
+    if (PREG == 0) begin
+        if (MREG == 1)
+        \$__ABC_REG rM (.Q(pM));
+        else
+        assign pM = 1'bx;
+        assign pP = 1'bx;
+    end else begin
             assign pM = 1'bx;
+            \$__ABC_REG rP (.Q(pP));
         end
 
         if (MREG == 0 && PREG == 0)
@@ -351,8 +350,8 @@ __CELL__ #(
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
     end
     else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
-		// Disconnect the A-input if MREG is enabled, since
-		//   combinatorial path is broken
+        // Disconnect the A-input if MREG is enabled, since
+        //   combinatorial path is broken
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
@@ -369,19 +368,22 @@ __CELL__ #(
             assign iD = D, pD = 1'bx;
         else
             \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
-		if (PREG == 0) begin
-			if (MREG == 1)
-				\$__ABC_REG rM (.Q(pM));
-            else begin
-                assign pM = 1'bx;
+        if (PREG == 0) begin
+            if (MREG == 1) begin
+                assign pAD = 1'bx;
+        \$__ABC_REG rM (.Q(pM));
+            end else begin
                 if (ADREG == 1)
                     \$__ABC_REG rAD (.Q(pAD));
                 else
                     assign pAD = 1'bx;
-            end
-		end
-		else
+        assign pM = 1'bx;
+        end
+        assign pP = 1'bx;
+    end else begin
+            assign pAD = 1'bx, pM = 1'bx;
             \$__ABC_REG rP (.Q(pP));
+        end
 
         if (MREG == 0 && PREG == 0)
             assign mP = oP, mPCOUT = oPCOUT;
@@ -397,8 +399,8 @@ __CELL__ #(
         `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
     end
     else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
-		// Disconnect the A-input if MREG is enabled, since
-		//   combinatorial path is broken
+        // Disconnect the A-input if MREG is enabled, since
+        //   combinatorial path is broken
         if (AREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
@@ -411,16 +413,16 @@ __CELL__ #(
             assign iC = C, pC = 1'bx;
         else
             \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
-        if (MREG == 1 && techmap_guard)
-            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
-        assign pM = 1'bx;
         if (DREG == 1 && techmap_guard)
-			$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
+            $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
         assign pD = 1'bx;
         if (ADREG == 1 && techmap_guard)
-			$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
+            $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
         assign pAD = 1'bx;
-		if (PREG == 1)
+        if (MREG == 1 && techmap_guard)
+            $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
+        assign pM = 1'bx;
+        if (PREG == 1)
             \$__ABC_REG rP (.Q(pP));
         else
             assign pP = 1'bx;
@@ -440,6 +442,6 @@ __CELL__ #(
     end
     else
         $error("Invalid DSP48E1 configuration");
-	endgenerate
-	`undef DSP48E1_INST
+    endgenerate
+    `undef DSP48E1_INST
 endmodule
-- 
cgit v1.2.3


From 11ac37733d436d5c0217fa6da029d620ec3da1b3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 21:56:28 -0700
Subject: Add techmap_autopurge to outputs in abc_map.v too

---
 techlibs/xilinx/abc_map.v | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs/xilinx/abc_map.v')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 9d78725df..e4976092c 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -123,17 +123,17 @@ module SRLC32E (
 endmodule
 
 module DSP48E1 (
-    output [29:0] ACOUT,
-    output [17:0] BCOUT,
-    output reg CARRYCASCOUT,
-    output reg [3:0] CARRYOUT,
-    output reg MULTSIGNOUT,
-    output OVERFLOW,
-    output reg signed [47:0] P,
-    output PATTERNBDETECT,
-    output PATTERNDETECT,
-    output [47:0] PCOUT,
-    output UNDERFLOW,
+    (* techmap_autopurge *) output [29:0] ACOUT,
+    (* techmap_autopurge *) output [17:0] BCOUT,
+    (* techmap_autopurge *) output reg CARRYCASCOUT,
+    (* techmap_autopurge *) output reg [3:0] CARRYOUT,
+    (* techmap_autopurge *) output reg MULTSIGNOUT,
+    (* techmap_autopurge *) output OVERFLOW,
+    (* techmap_autopurge *) output reg signed [47:0] P,
+    (* techmap_autopurge *) output PATTERNBDETECT,
+    (* techmap_autopurge *) output PATTERNDETECT,
+    (* techmap_autopurge *) output [47:0] PCOUT,
+    (* techmap_autopurge *) output UNDERFLOW,
     (* techmap_autopurge *) input signed [29:0] A,
     (* techmap_autopurge *) input [29:0] ACIN,
     (* techmap_autopurge *) input [3:0] ALUMODE,
-- 
cgit v1.2.3