From 247a63f55df2e85f0aa15a9a05f436c1225f9ec1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 11:45:55 -0700 Subject: Add support for MULT and DPORT --- techlibs/xilinx/abc_unmap.v | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'techlibs/xilinx/abc_unmap.v') diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index bcb1069bc..f9b5bd518 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -30,14 +30,13 @@ endmodule module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule -module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); - assign O = P; -endmodule -module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); +(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX" *) +module \$__ABC_DSP48E1_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); assign O = P; endmodule -module \$__ABC_DSP48E1_MULT ( +(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT" *) +module \$__ABC_DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, output reg CARRYCASCOUT, -- cgit v1.2.3