From e1ba25d79f0fc623006b250e72093199d0804d52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 22:54:35 -0700
Subject: Add RAM32X1D box info

---
 techlibs/xilinx/abc_xc7.box | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

(limited to 'techlibs/xilinx/abc_xc7.box')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index dafef9fef..39c535303 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -35,16 +35,23 @@ CARRY4 3 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
+# Outputs: DPO SPO
+RAM32X1D 4 0 13 2
+-   -   -   -   -   - 124 124 124 124 124 - -
+124 124 124 124 124 - -   -   -   -   -   - -
+
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
 # Outputs: DPO SPO
-RAM64X1D 4 0 15 2
+RAM64X1D 5 0 15 2
 -   -   -   -   -   -   - 124 124 124 124 124 124 - -
 124 124 124 124 124 124 - -   -   -   -   -   124 - -
 
 # SLICEM/A6LUT + F7[AB]MUX
 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
 # Outputs: DPO SPO
-RAM128X1D 5 0 17 2
+RAM128X1D 6 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
-- 
cgit v1.2.3