From 9c7f47bbd5fc190578054a6d018760c2f2b62c03 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 6 Jan 2015 13:33:51 +0100 Subject: Towards Xilinx bram support --- techlibs/xilinx/brams.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/brams.v') diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v index aaab8d475..49219c8a1 100644 --- a/techlibs/xilinx/brams.v +++ b/techlibs/xilinx/brams.v @@ -13,8 +13,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN input [71:0] B1DATA; input [7:0] B1EN; - wire [15:0] A1ADDR_16 = A1ADDR; - wire [15:0] B1ADDR_16 = B1ADDR; + wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0}; + wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0}; wire [7:0] DIP, DOP; wire [63:0] DI, DO; -- cgit v1.2.3