From 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 24 Nov 2019 16:05:45 +0100 Subject: clkbufmap: Add support for inverters in clock path. --- techlibs/xilinx/cells_sim.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/cells_sim.v') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5faddcd52..fa33f4596 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -126,7 +126,11 @@ endmodule // assign O = IO, IO = T ? 1'bz : I; // endmodule -module INV(output O, input I); +module INV( + (* clkbuf_inv = "I" *) + output O, + input I +); assign O = !I; endmodule -- cgit v1.2.3