From 10014e2643cdedd2050f072eb5d1b8d01dccc406 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <mwk@0x04.net>
Date: Wed, 4 Dec 2019 06:31:09 +0100
Subject: xilinx: Add models for LUTRAM cells. (#1537)

---
 techlibs/xilinx/cells_xtra.py | 68 +++++++++++++++++++++----------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

(limited to 'techlibs/xilinx/cells_xtra.py')

diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 01e7101d1..e4c580b9d 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -28,40 +28,40 @@ CELLS = [
     # - UG974 (Ultrascale)
 
     # CLB -- RAM/ROM.
-    Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
-    #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
-    Cell('ROM16X1'),
-    Cell('ROM32X1'),
-    Cell('ROM64X1'),
-    Cell('ROM128X1'),
-    Cell('ROM256X1'),
+    # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('ROM16X1'),
+    # Cell('ROM32X1'),
+    # Cell('ROM64X1'),
+    # Cell('ROM128X1'),
+    # Cell('ROM256X1'),
 
     # CLB -- registers/latches.
     # Virtex 1/2/4/5, Spartan 3.
-- 
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