From 7a9081440c33af05cd5b24b4eb8907ac2ba4876a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 18 Nov 2019 03:47:56 +0100 Subject: xilinx: Add simulation models for MULT18X18* and DSP48A*. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6) --- techlibs/xilinx/cells_xtra.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'techlibs/xilinx/cells_xtra.py') diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index ef7ce856a..f401ebe78 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -204,11 +204,11 @@ CELLS = [ Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), # Multipliers and DSP. - Cell('MULT18X18'), # Spartan 3 - Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 - Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E - Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP - Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 + # Cell('MULT18X18'), # Virtex 2, Spartan 3 + # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 + # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E + # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP + # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 -- cgit v1.2.3