From efd04880dbeb2021c503c82ad962fe8c5d6802d4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 16:16:50 -0700
Subject: Add RAM32X1D support

---
 techlibs/xilinx/drams.txt | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'techlibs/xilinx/drams.txt')

diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
index 91632bcee..2613c206c 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/drams.txt
@@ -1,4 +1,17 @@
 
+bram $__XILINX_RAM32X1D
+  init 1
+  abits 5
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
 bram $__XILINX_RAM64X1D
   init 1
   abits 6
@@ -25,6 +38,13 @@ bram $__XILINX_RAM128X1D
   clkpol 0 2
 endbram
 
+match $__XILINX_RAM32X1D
+  min bits 3
+  min wports 1
+  make_outreg
+  or_next_if_better
+endmatch
+
 match $__XILINX_RAM64X1D
   min bits 5
   min wports 1
-- 
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