From c865559f9540c29cb9c6302edc8b4a2620c0b49d Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jul 2019 19:15:25 +0100 Subject: xc7: Map combinational DSP48E1s Signed-off-by: David Shah --- techlibs/xilinx/dsp_map.v | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 techlibs/xilinx/dsp_map.v (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v new file mode 100644 index 000000000..4faa204aa --- /dev/null +++ b/techlibs/xilinx/dsp_map.v @@ -0,0 +1,40 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A({5'b0, A}), + .B(B), + .C(48'b0), + .D(24'b0), + .P(P_48), + + .INMODE(4'b0000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign OUT = P_48; +endmodule -- cgit v1.2.3 From b33ecd2a746b734fda33d8535afecf76bd35f59c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 16:00:03 -0700 Subject: Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little --- techlibs/xilinx/dsp_map.v | 40 ---------------------------------------- 1 file changed, 40 deletions(-) delete mode 100644 techlibs/xilinx/dsp_map.v (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v deleted file mode 100644 index 4faa204aa..000000000 --- a/techlibs/xilinx/dsp_map.v +++ /dev/null @@ -1,40 +0,0 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0) - ) _TECHMAP_REPLACE_ ( - //Data path - .A({5'b0, A}), - .B(B), - .C(48'b0), - .D(24'b0), - .P(P_48), - - .INMODE(4'b0000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign OUT = P_48; -endmodule -- cgit v1.2.3 From 0c7ee6d0fa14b634ffbde5ad79983cb89372a697 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 14:18:44 -0700 Subject: Move DSP mapping back out to dsp_map.v --- techlibs/xilinx/dsp_map.v | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 techlibs/xilinx/dsp_map.v (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v new file mode 100644 index 000000000..da1d6f3a9 --- /dev/null +++ b/techlibs/xilinx/dsp_map.v @@ -0,0 +1,40 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A({5'b0, A}), + .B(B), + .C(48'b0), + .D(24'b0), + .P(P_48), + + .INMODE(4'b0000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule -- cgit v1.2.3 From 6390c535ba70c0a4fe0cb08156fefa80fb621e47 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 14:30:25 -0700 Subject: Revert drop down to 24x16 multipliers for all --- techlibs/xilinx/dsp_map.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 2063c45e2..da1d6f3a9 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers @@ -20,8 +20,8 @@ module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({6'b0, A}), - .B({1'b0, B}), + .A({5'b0, A}), + .B(B), .C(48'b0), .D(24'b0), .P(P_48), -- cgit v1.2.3 From c501aa5ee84c14f5b6aebe3052dabb1c314eb9e0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 15:54:27 -0700 Subject: Signedness --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index da1d6f3a9..28e456898 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -20,7 +20,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({5'b0, A}), + .A({{5{A[24]}}, A}), .B(B), .C(48'b0), .D(24'b0), -- cgit v1.2.3 From e3f8e59f182129aa2ff9ba7a1ed7fbbaab657ce5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 14:25:40 -0700 Subject: Make all operands signed --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 28e456898..32f570935 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); +module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers -- cgit v1.2.3 From 601fac97e4c48d524d5c7f9b4688b536c2e1c891 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 21:02:49 -0700 Subject: Add params --- techlibs/xilinx/dsp_map.v | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 32f570935..3d7b09d69 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,10 @@ module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + wire [47:0] P_48; DSP48E1 #( // Disable all registers -- cgit v1.2.3 From 57b2e4b9c1dda6d092e261f90a311087c62d0bc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 10:44:35 -0700 Subject: INMODE is 5 bits --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 3d7b09d69..423e12fbe 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -32,7 +32,7 @@ module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed .D(24'b0), .P(P_48), - .INMODE(4'b0000), + .INMODE(5'b00000), .ALUMODE(4'b0000), .OPMODE(7'b000101), .CARRYINSEL(3'b000), -- cgit v1.2.3 From 1f722b35009275ad9a3f4ce4224fcb6973e3bc80 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 16:33:20 -0700 Subject: Remove signed from ports in +/xilinx/dsp_map.v --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 423e12fbe..fdd55afe3 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; -- cgit v1.2.3 From a7e60322878913886278d537365baf939182a1d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Sep 2019 20:56:29 -0700 Subject: Set USE_MULT and USE_SIMD --- techlibs/xilinx/dsp_map.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index fdd55afe3..cc37f0085 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -23,7 +23,9 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .INMODEREG(0), .MREG(0), .OPMODEREG(0), - .PREG(0) + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), -- cgit v1.2.3 From 3a390733027584071d0cd3b2d99c738ce6f1a829 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 17:10:43 -0700 Subject: Set more ports explicitly --- techlibs/xilinx/dsp_map.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index cc37f0085..8901b215b 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .OPMODEREG(0), .PREG(0), .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48") + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), -- cgit v1.2.3 From c15a35db8487a31592046bfe8422740e196407d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 15:55:49 -0700 Subject: D is 25 bits not 24 bits wide --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/dsp_map.v') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 8901b215b..a4256eb92 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .A({{5{A[24]}}, A}), .B(B), .C(48'b0), - .D(24'b0), + .D(25'b0), .P(P_48), .INMODE(5'b00000), -- cgit v1.2.3