From f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 13 Oct 2015 15:40:21 +0200 Subject: Added examples/ top-level directory --- techlibs/xilinx/example_basys3/example.v | 21 --------------------- 1 file changed, 21 deletions(-) delete mode 100644 techlibs/xilinx/example_basys3/example.v (limited to 'techlibs/xilinx/example_basys3/example.v') diff --git a/techlibs/xilinx/example_basys3/example.v b/techlibs/xilinx/example_basys3/example.v deleted file mode 100644 index 2b01a22a8..000000000 --- a/techlibs/xilinx/example_basys3/example.v +++ /dev/null @@ -1,21 +0,0 @@ -module example(CLK, LD); - input CLK; - output [15:0] LD; - - wire clock; - reg [15:0] leds; - - BUFG CLK_BUF (.I(CLK), .O(clock)); - OBUF LD_BUF[15:0] (.I(leds), .O(LD)); - - parameter COUNTBITS = 26; - reg [COUNTBITS-1:0] counter; - - always @(posedge CLK) begin - counter <= counter + 1; - if (counter[COUNTBITS-1]) - leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5]; - else - leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5]; - end -endmodule -- cgit v1.2.3