From 3090951d54859c331d28232481361bb9c26b3d48 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 1 Mar 2019 11:21:07 -0800 Subject: Changes required for VPR place and route synth_xilinx. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- techlibs/xilinx/synth_xilinx.cc | 68 +++++++++++++++++++++++++++++++---------- 1 file changed, 52 insertions(+), 16 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c11d885d..60cfde604 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -63,6 +63,12 @@ struct SynthXilinxPass : public Pass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -no-brams\n"); + log(" disable infering of block rams\n"); + log("\n"); + log(" -no-drams\n"); + log(" disable infering of distributed rams\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -90,11 +96,11 @@ struct SynthXilinxPass : public Pass log(" coarse:\n"); log(" synth -run coarse\n"); log("\n"); - log(" bram:\n"); + log(" bram: (only executed when '-no-brams' is not given)\n"); log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" techmap -map +/xilinx/brams_map.v\n"); log("\n"); - log(" dram:\n"); + log(" dram: (only executed when '-no-drams' is not given)\n"); log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); @@ -104,16 +110,17 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); + log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); log(" clean\n"); log("\n"); log(" map_cells:\n"); - log(" techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)\n"); - log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n"); + log(" techmap -map +/xilinx/cells_map.v\n"); + log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n"); log(" clean\n"); log("\n"); log(" check:\n"); @@ -137,6 +144,8 @@ struct SynthXilinxPass : public Pass bool flatten = false; bool retime = false; bool vpr = false; + bool noBrams = false; + bool noDrams = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -173,6 +182,14 @@ struct SynthXilinxPass : public Pass vpr = true; continue; } + if (args[argidx] == "-no-brams") { + noBrams = true; + continue; + } + if (args[argidx] == "-no-drams") { + noDrams = true; + continue; + } break; } extra_args(args, argidx, design); @@ -187,9 +204,18 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "begin")) { - Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); + if (vpr) { + Pass::call(design, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + } else { + Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); + } + Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); - Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); + + if (!noBrams) { + Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); + } + Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); } @@ -206,14 +232,18 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "bram")) { - Pass::call(design, "memory_bram -rules +/xilinx/brams.txt"); - Pass::call(design, "techmap -map +/xilinx/brams_map.v"); + if (!noBrams) { + Pass::call(design, "memory_bram -rules +/xilinx/brams.txt"); + Pass::call(design, "techmap -map +/xilinx/brams_map.v"); + } } if (check_label(active, run_from, run_to, "dram")) { - Pass::call(design, "memory_bram -rules +/xilinx/drams.txt"); - Pass::call(design, "techmap -map +/xilinx/drams_map.v"); + if (!noDrams) { + Pass::call(design, "memory_bram -rules +/xilinx/drams.txt"); + Pass::call(design, "techmap -map +/xilinx/drams_map.v"); + } } if (check_label(active, run_from, run_to, "fine")) @@ -223,7 +253,14 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + + if (vpr) { + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + } else { + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + } + + Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } @@ -231,14 +268,13 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); - if (vpr) - Pass::call(design, "techmap -map +/xilinx/lut2lut.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT"); Pass::call(design, "clean"); } -- cgit v1.2.3 From eccaf101d8324f518ed89134b4f21d2bdc636a8d Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 1 Mar 2019 12:14:27 -0800 Subject: Modify arguments to match existing style. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- techlibs/xilinx/synth_xilinx.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 60cfde604..12ad9fdaf 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -no-brams\n"); + log(" -nobrams\n"); log(" disable infering of block rams\n"); log("\n"); - log(" -no-drams\n"); + log(" -nodrams\n"); log(" disable infering of distributed rams\n"); log("\n"); log(" -run :\n"); @@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass log(" coarse:\n"); log(" synth -run coarse\n"); log("\n"); - log(" bram: (only executed when '-no-brams' is not given)\n"); + log(" bram: (only executed when '-nobrams' is not given)\n"); log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" techmap -map +/xilinx/brams_map.v\n"); log("\n"); - log(" dram: (only executed when '-no-drams' is not given)\n"); + log(" dram: (only executed when '-nodrams' is not given)\n"); log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); @@ -182,11 +182,11 @@ struct SynthXilinxPass : public Pass vpr = true; continue; } - if (args[argidx] == "-no-brams") { + if (args[argidx] == "-nobrams") { noBrams = true; continue; } - if (args[argidx] == "-no-drams") { + if (args[argidx] == "-nodrams") { noDrams = true; continue; } -- cgit v1.2.3 From 5ebeca12eb0bf9317acec3d619021ab337d445ba Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 1 Mar 2019 14:35:14 -0800 Subject: Use singular for disabling of DRAM or BRAM inference. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- techlibs/xilinx/synth_xilinx.cc | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 12ad9fdaf..9e7559944 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -nobrams\n"); + log(" -nobram\n"); log(" disable infering of block rams\n"); log("\n"); - log(" -nodrams\n"); + log(" -nodram\n"); log(" disable infering of distributed rams\n"); log("\n"); log(" -run :\n"); @@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass log(" coarse:\n"); log(" synth -run coarse\n"); log("\n"); - log(" bram: (only executed when '-nobrams' is not given)\n"); + log(" bram: (only executed when '-nobram' is not given)\n"); log(" memory_bram -rules +/xilinx/brams.txt\n"); log(" techmap -map +/xilinx/brams_map.v\n"); log("\n"); - log(" dram: (only executed when '-nodrams' is not given)\n"); + log(" dram: (only executed when '-nodram' is not given)\n"); log(" memory_bram -rules +/xilinx/drams.txt\n"); log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); @@ -144,8 +144,8 @@ struct SynthXilinxPass : public Pass bool flatten = false; bool retime = false; bool vpr = false; - bool noBrams = false; - bool noDrams = false; + bool nobram = false; + bool nodram = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -182,12 +182,12 @@ struct SynthXilinxPass : public Pass vpr = true; continue; } - if (args[argidx] == "-nobrams") { - noBrams = true; + if (args[argidx] == "-nobram") { + nobram = true; continue; } - if (args[argidx] == "-nodrams") { - noDrams = true; + if (args[argidx] == "-nodram") { + nodram = true; continue; } break; @@ -212,7 +212,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); - if (!noBrams) { + if (!nobram) { Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); } @@ -232,7 +232,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "bram")) { - if (!noBrams) { + if (!nobram) { Pass::call(design, "memory_bram -rules +/xilinx/brams.txt"); Pass::call(design, "techmap -map +/xilinx/brams_map.v"); } @@ -240,7 +240,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "dram")) { - if (!noDrams) { + if (!nodram) { Pass::call(design, "memory_bram -rules +/xilinx/drams.txt"); Pass::call(design, "techmap -map +/xilinx/drams_map.v"); } -- cgit v1.2.3