From 295bb23ae06d36acc8ced4825ece6003470cd357 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 09:08:56 -0700
Subject: Wrap FDRE with $__ABC_FDRE containing comb

---
 techlibs/xilinx/synth_xilinx.cc | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a11648873..b9da4e6a6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,25 +276,33 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+			if (abc == "abc9")
+				run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
 			run("clean");
 		}
 
 		if (check_label("map_luts")) {
-			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
-			else if (help_mode)
+			if (abc == "abc9") {
+				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
+				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
+			}
+			else if (help_mode) {
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
-			else
+				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			}
+			else {
 				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			}
 			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From ac18a76bebad001fc3e617a7cefebe13610abcb8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 09:34:48 -0700
Subject: Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9da4e6a6..375ab7af1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -277,7 +277,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_cells")) {
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			if (abc == "abc9")
-				run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
+				run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 09:46:35 -0700
Subject: Fix initialisation of flops

---
 techlibs/xilinx/synth_xilinx.cc | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 375ab7af1..db43e13c1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -275,9 +275,10 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			if (abc == "abc9")
-				run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*");
+				run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -D _ABC -map +/xilinx/ff_map.v");
+			else
+				run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
@@ -286,23 +287,22 @@ struct SynthXilinxPass : public ScriptPass
 				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
 				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
 			}
-			else if (help_mode) {
+			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
-				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-			}
-			else {
+			else
 				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-			}
 			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+			if (abc == "abc9")
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+			else
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From c865559f9540c29cb9c6302edc8b4a2620c0b49d Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 8 Jul 2019 19:15:25 +0100
Subject: xc7: Map combinational DSP48E1s

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/xilinx/synth_xilinx.cc | 39 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 5 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0a30848aa..db0cbb644 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -77,6 +77,9 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nowidelut\n");
 		log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
 		log("\n");
+		log("    -nodsp\n");
+		log("        do not use DSP48E1s to implement multipliers and associated logic\n");
+		log("\n");
 		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
 		log("        above this number of inputs (minimum value 5).\n");
@@ -103,7 +106,7 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, family;
-	bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+	bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, nodsp, abc9;
 	int widemux;
 
 	void clear_flags() YS_OVERRIDE
@@ -121,6 +124,7 @@ struct SynthXilinxPass : public ScriptPass
 		nosrl = false;
 		nocarry = false;
 		nowidelut = false;
+		nodsp = false;
 		abc9 = false;
 		widemux = 0;
 	}
@@ -201,6 +205,10 @@ struct SynthXilinxPass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
+			if (args[argidx] == "-nodsp") {
+				nodsp = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -239,10 +247,31 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("coarse")) {
-			if (help_mode)
-				run("synth -run coarse [-flatten]", "(with '-flatten')");
-			else
-				run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
+			run("proc");
+			if (flatten || help_mode)
+				run("flatten", "(with '-flatten')");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
+			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+			run("share");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			if (!nodsp || help_mode) {
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
+				run("clean");
+				run("techmap -map +/xilinx/dsp_map.v");
+			}
+			run("alumacc");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
-- 
cgit v1.2.3


From b33ecd2a746b734fda33d8535afecf76bd35f59c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 16:00:03 -0700
Subject: Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little

---
 techlibs/xilinx/synth_xilinx.cc | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3da35db75..9199fbb53 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -279,11 +279,8 @@ struct SynthXilinxPass : public ScriptPass
 
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 
-			if (!nodsp || help_mode) {
+			if (!nodsp || help_mode)
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
-				run("clean");
-				run("techmap -map +/xilinx/dsp_map.v");
-			}
 
 			run("alumacc");
 			run("share");
-- 
cgit v1.2.3


From 838ae1a14cddf25919bb2a68e74220a07db4a06e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 16:15:57 -0700
Subject: synth_xilinx's map_cells stage to techmap ff_map.v

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2455c2885..45be9a318 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -361,6 +361,8 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
+			if (abc9)
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
-- 
cgit v1.2.3


From 7b2599cb94a718d3c3d6fa4b5eb3ad4824ed13c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 17:06:05 -0700
Subject: Move ABC FF stuff to abc_ff.v; add support for other FD* types

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 45be9a318..d5ae124e0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -362,7 +362,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v";
+				techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
-- 
cgit v1.2.3


From 5f00d335d4861fc03dd7b6cee68fd79505bd3d41 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 15:03:15 -0700
Subject: Oops forgot these files

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 01e75b50e..796615211 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -329,6 +329,10 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
+			if (help_mode || !nodsp) {
+				run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')");
+				run("xilinx_dsp", "                     (skip if '-nodsp')");
+			}
 			if (help_mode) {
 				run("simplemap t:$mux", "         ('-widemux' only)");
 				run("muxcover <internal options>, ('-widemux' only)");
-- 
cgit v1.2.3


From 95c8d27b0bfdea330a62a18825dea3691b4affe2 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 16 Jul 2019 16:46:41 +0100
Subject: xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is
 25x18 signed)

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/xilinx/synth_xilinx.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 01e75b50e..5bfbd1583 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass
 
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 
+			// The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
+			// Due to current limitations of mul2dsp, we are actually mapping as a 24x17
+			// unsigned multiply with MSBs set to 1'b0
+
 			if (!nodsp || help_mode)
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
 
 			run("alumacc");
 			run("share");
-- 
cgit v1.2.3


From 6390c535ba70c0a4fe0cb08156fefa80fb621e47 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Jul 2019 14:30:25 -0700
Subject: Revert drop down to 24x16 multipliers for all

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 815bf0848..bfce922db 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -289,7 +289,7 @@ struct SynthXilinxPass : public ScriptPass
 			// unsigned multiply with MSBs set to 1'b0
 
 			if (!nodsp || help_mode)
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 
 			run("alumacc");
 			run("share");
-- 
cgit v1.2.3


From 58e63feae1e950fff839c4261a787d5daf07612e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Jul 2019 13:26:17 -0700
Subject: Update comment

---
 techlibs/xilinx/synth_xilinx.cc | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index bfce922db..2e2fbbd9d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -284,12 +284,10 @@ struct SynthXilinxPass : public ScriptPass
 
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 
-			// The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
-			// Due to current limitations of mul2dsp, we are actually mapping as a 24x17
-			// unsigned multiply with MSBs set to 1'b0
-
-			if (!nodsp || help_mode)
+			if (!nodsp || help_mode) {
+				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+			}
 
 			run("alumacc");
 			run("share");
-- 
cgit v1.2.3


From 5562cb08a47881bee30bf79f8ca720b997166b2f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 13:09:55 -0700
Subject: Use single DSP_SIGNEDONLY macro

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2e2fbbd9d..e5a27015a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,7 +286,7 @@ struct SynthXilinxPass : public ScriptPass
 
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 			}
 
 			run("alumacc");
-- 
cgit v1.2.3


From fc0b5d5ab6bcbb6cc5fcacab479504c08ab80d23 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 1 Aug 2019 12:45:14 -0700
Subject: Change $__softmul back to $mul

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e5a27015a..a787c7c4c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -334,6 +334,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (help_mode || !nodsp) {
 				run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
+				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
 			if (help_mode) {
 				run("simplemap t:$mux", "         ('-widemux' only)");
-- 
cgit v1.2.3


From 716024387468285f0d5ee2719b86fe6ddbfff93e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 8 Aug 2019 10:45:56 -0700
Subject: Move xilinx_dsp to before alumacc

---
 techlibs/xilinx/synth_xilinx.cc | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a787c7c4c..49beaa565 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,7 +286,10 @@ struct SynthXilinxPass : public ScriptPass
 
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
+				run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); // TODO: fold into xilinx_dsp
+				run("xilinx_dsp", "                     (skip if '-nodsp')");
+				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
 
 			run("alumacc");
@@ -331,11 +334,6 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-			if (help_mode || !nodsp) {
-				run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')");
-				run("xilinx_dsp", "                     (skip if '-nodsp')");
-				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
-			}
 			if (help_mode) {
 				run("simplemap t:$mux", "         ('-widemux' only)");
 				run("muxcover <internal options>, ('-widemux' only)");
-- 
cgit v1.2.3


From 162eab6b7422754c4c88d794f8024cfc1e03a419 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 8 Aug 2019 10:55:48 -0700
Subject: Combine techmap calls

---
 techlibs/xilinx/synth_xilinx.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 49beaa565..7b1fe5e3b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,8 +286,7 @@ struct SynthXilinxPass : public ScriptPass
 
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-				run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); // TODO: fold into xilinx_dsp
+				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
-- 
cgit v1.2.3


From 0b5b56c1ecab78d126bbab13598c184f5e28cccc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 15:19:33 -0700
Subject: Pack partial-product adder DSP48E1 packing

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7b1fe5e3b..a54b3ac52 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -287,6 +287,8 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
+				run("opt_expr -fine", "                 (skip if '-nodsp')");
+				run("wreduce", "                        (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
-- 
cgit v1.2.3


From edff79a25a802e5b1816608b48e3ac335ad87147 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 13 Aug 2019 10:29:42 +0100
Subject: xilinx: Rework labels for faster Verilator testing

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/xilinx/synth_xilinx.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 265cee6d6..546d67337 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -255,7 +255,7 @@ struct SynthXilinxPass : public ScriptPass
 			run(stringf("hierarchy -check %s", top_opt.c_str()));
 		}
 
-		if (check_label("coarse")) {
+		if (check_label("prepare")) {
 			run("proc");
 			if (flatten || help_mode)
 				run("flatten", "(with '-flatten')");
@@ -283,7 +283,9 @@ struct SynthXilinxPass : public ScriptPass
 			}
 
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+		}
 
+		if (check_label("dsp")) {
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
@@ -292,7 +294,9 @@ struct SynthXilinxPass : public ScriptPass
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
+		}
 
+		if (check_label("coarse")) {
 			run("alumacc");
 			run("share");
 			run("opt");
-- 
cgit v1.2.3


From 2a1b98d478918b0a17c7e509ada6e7a71bbab526 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 13 Aug 2019 10:21:24 -0700
Subject: Add DSP_A_MAXWIDTH_PARTIAL, refactor

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 265cee6d6..477b2f6f7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,7 +286,7 @@ struct SynthXilinxPass : public ScriptPass
 
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
+				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
 				run("opt_expr -fine", "                 (skip if '-nodsp')");
 				run("wreduce", "                        (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
-- 
cgit v1.2.3


From be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 12:39:11 -0700
Subject: Use abc_{map,unmap,model}.v

---
 techlibs/xilinx/synth_xilinx.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6456dbdf4..3525e4de9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
@@ -373,11 +373,11 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
+				techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -389,7 +389,7 @@ struct SynthXilinxPass : public ScriptPass
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
+				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
@@ -408,7 +408,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 			if (abc9)
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
 			else
 				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-- 
cgit v1.2.3


From 5eda5fc7eb889b738739270f67349b1027951443 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 12:41:11 -0700
Subject: Remove -icells

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3525e4de9..d4874af45 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -icells +/xilinx/cells_sim.v");
+				run("read_verilog -lib +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
-- 
cgit v1.2.3


From 3b52d6e29ccc95fd4d102d9a59bb34125521c648 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 17:55:12 -0700
Subject: Move `techmap abc_map.v` into map_luts

---
 techlibs/xilinx/synth_xilinx.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d6ff91e13..a2ec6a9c9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -380,7 +380,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -393,6 +393,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
+				run("techmap -map +/xilinx/abc_map.v";
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-- 
cgit v1.2.3


From 30a379b5b6600f0e0e99f0c99ad7bc1d4d08cd90 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 17:59:31 -0700
Subject: Cleanup techmap in map_luts

---
 techlibs/xilinx/synth_xilinx.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a2ec6a9c9..d28cd2428 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -393,7 +393,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
-				run("techmap -map +/xilinx/abc_map.v";
+				run("techmap -map +/xilinx/abc_map.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
@@ -411,10 +411,12 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+			std::string techmap_args = "-map +/xilinx/lut_map.v";
 			if (abc9)
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
+				techmap_args += " -map +/xilinx/abc_unmap.v";
 			else
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+				techmap_args += " -map +/xilinx/ff_map.v";
+			run("techmap " + techmap_args);
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
-- 
cgit v1.2.3


From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:16:37 -0700
Subject: Remove sequential extension

---
 techlibs/xilinx/synth_xilinx.cc | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d28cd2428..b9c4df82f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -379,8 +379,6 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
-			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -411,11 +409,9 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			std::string techmap_args = "-map +/xilinx/lut_map.v";
+			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
 			if (abc9)
 				techmap_args += " -map +/xilinx/abc_unmap.v";
-			else
-				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-- 
cgit v1.2.3


From c26c5563845d81048dea35c4aef5f4678e177b23 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:47:11 -0700
Subject: xilinx to use abc_map.v with -max_iter 1

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9c4df82f..263788fec 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -391,7 +391,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
-				run("techmap -map +/xilinx/abc_map.v");
+				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-- 
cgit v1.2.3


From 5d0f6cbd540e1be4525563329dabd2f2aaf7069e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 11:47:06 -0700
Subject: techmap before read

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 263788fec..218192315 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -390,8 +390,8 @@ struct SynthXilinxPass : public ScriptPass
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
+				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-- 
cgit v1.2.3


From c7af71ecde65ad310e487a296b957678412fca74 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 11:47:17 -0700
Subject: Use semicolon

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 218192315..8d0cf84f3 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -386,7 +386,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_luts")) {
 			run("opt_expr -mux_undef");
 			if (help_mode)
-				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
+				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-- 
cgit v1.2.3


From fda94311ee6e3ec8de0e85e91251a2744673abaf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Fri, 16 Aug 2019 03:14:30 +0000
Subject: synth_xilinx: Support init values on Spartan 6 flip-flops properly.

---
 techlibs/xilinx/synth_xilinx.cc | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index bfc0ac2bf..e0e81ef1d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -266,6 +266,14 @@ struct SynthXilinxPass : public ScriptPass
 
 	void script() YS_OVERRIDE
 	{
+		std::string ff_map_file;
+		if (help_mode)
+			ff_map_file = "+/xilinx/xc6s_ff_map.v";
+		else if (family == "xc6s")
+			ff_map_file = "+/xilinx/xc6s_ff_map.v";
+		else
+			ff_map_file = "+/xilinx/xc7_ff_map.v";
+
 		if (check_label("begin")) {
 			if (vpr)
 				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
@@ -416,11 +424,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_ffs")) {
-				if (abc9 || help_mode) {
-						run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
-						run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-										"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "('-abc9' only)");
-				}
+			if (abc9 || help_mode) {
+				run("techmap -map " + ff_map_file, "('-abc9' only)");
+			}
 		}
 
 		if (check_label("map_luts")) {
@@ -453,15 +459,12 @@ struct SynthXilinxPass : public ScriptPass
 				run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
 			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
 			if (help_mode)
-				techmap_args += " [-map +/xilinx/ff_map.v]";
+				techmap_args += " [-map " + ff_map_file + "]";
 			else if (abc9)
 				techmap_args += " -map +/xilinx/abc_unmap.v";
 			else
-				techmap_args += " -map +/xilinx/ff_map.v";
+				techmap_args += " -map " + ff_map_file;
 			run("techmap " + techmap_args);
-			if (!abc9 || help_mode)
-				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From bfda921d0317bfb4cb6fc9de8a556c2258b709bc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 13:17:47 -0700
Subject: Remove "opt_expr -fine" call

---
 techlibs/xilinx/synth_xilinx.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 95b2c4040..e13491e2c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -325,7 +325,6 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-				run("opt_expr -fine", "                 (skip if '-nodsp')");
 				run("wreduce", "                        (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
-- 
cgit v1.2.3


From d3fb3081812f0fc34230aabe01b14f06a3240d56 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 13:18:10 -0700
Subject: Rename label to map_dsp

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e13491e2c..af8ee2368 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -321,7 +321,7 @@ struct SynthXilinxPass : public ScriptPass
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 		}
 
-		if (check_label("dsp")) {
+		if (check_label("map_dsp")) {
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-- 
cgit v1.2.3


From 8514e7c32ebfb2ce35619063b1507416f01bd3b4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 14:09:21 -0700
Subject: Revert "Remove "opt_expr -fine" call"

This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc.
---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index af8ee2368..2cf0bd4f9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -325,6 +325,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
+				run("opt_expr -fine", "                 (skip if '-nodsp')");
 				run("wreduce", "                        (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
-- 
cgit v1.2.3


From f3a55d3f06a21af06a267b3f9da8bd4df3d4aa82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 14:11:56 -0700
Subject: Add comment for why opt_expr is necessary

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2cf0bd4f9..c99b77905 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -325,6 +325,8 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
+				// Necessary for optimising away $shl cells, as well as $add cells
+				//   that have inputs with 1'b0 LSBs
 				run("opt_expr -fine", "                 (skip if '-nodsp')");
 				run("wreduce", "                        (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
-- 
cgit v1.2.3


From c460d10e60648c5126fe4a105ebf608b4f8d5e1a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 14:17:35 -0700
Subject: Remove wreduce call

---
 techlibs/xilinx/synth_xilinx.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c99b77905..9ad28a933 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -328,7 +328,6 @@ struct SynthXilinxPass : public ScriptPass
 				// Necessary for optimising away $shl cells, as well as $add cells
 				//   that have inputs with 1'b0 LSBs
 				run("opt_expr -fine", "                 (skip if '-nodsp')");
-				run("wreduce", "                        (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
-- 
cgit v1.2.3


From 76eedee08928f035f00f46304d1b49e9502401c1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 14:26:12 -0700
Subject: Really get rid of 'opt_expr -fine' by being explicit

---
 techlibs/xilinx/synth_xilinx.cc | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 9ad28a933..4ca8a4667 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -325,9 +325,6 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-				// Necessary for optimising away $shl cells, as well as $add cells
-				//   that have inputs with 1'b0 LSBs
-				run("opt_expr -fine", "                 (skip if '-nodsp')");
 				run("xilinx_dsp", "                     (skip if '-nodsp')");
 				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
 			}
-- 
cgit v1.2.3


From 5c1271c51c41b8a067ecf6165d3e09a73eee5fb7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 15:26:56 -0700
Subject: Move "(skip if -nodsp)" message to label

---
 techlibs/xilinx/synth_xilinx.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4ca8a4667..83be66daa 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -321,12 +321,12 @@ struct SynthXilinxPass : public ScriptPass
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 		}
 
-		if (check_label("map_dsp")) {
+		if (check_label("map_dsp"), "(skip if '-nodsp')") {
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
-				run("xilinx_dsp", "                     (skip if '-nodsp')");
-				run("chtype -set $mul t:$__soft_mul","  (skip if '-nodsp')");
+				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+				run("xilinx_dsp");
+				run("chtype -set $mul t:$__soft_mul");
 			}
 		}
 
-- 
cgit v1.2.3


From 0ebbecf833712165c495fc15fe67b6287cf1fb72 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 13:06:59 -0700
Subject: Missing space

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3d92c3e2c..e822d9b7e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -83,6 +83,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("\n");
 		log("    -nodsp\n");
 		log("        do not use DSP48E1s to implement multipliers and associated logic\n");
+		log("\n");
 		log("    -iopad\n");
 		log("        enable I/O buffer insertion (selected automatically by -ise)\n");
 		log("\n");
-- 
cgit v1.2.3


From 09ac36da601aab607f01ccf6e2baa29296877877 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Sun, 15 Sep 2019 00:49:53 +0000
Subject: xilinx: Make blackbox library family-dependent.

Fixes #1246.
---
 techlibs/xilinx/synth_xilinx.cc | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e0e81ef1d..7467e024c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
-		log("    -family {xcup|xcu|xc7|xc6s}\n");
+		log("    -family {xcup|xcu|xc7|xc6v|xc6s}\n");
 		log("        run synthesis for the specified Xilinx architecture\n");
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        default: xc7\n");
@@ -244,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
-		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
+		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s")
 			log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
 
 		if (widemux != 0 && widemux < 2)
@@ -268,7 +268,7 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		std::string ff_map_file;
 		if (help_mode)
-			ff_map_file = "+/xilinx/xc6s_ff_map.v";
+			ff_map_file = "+/xilinx/{family}_ff_map.v";
 		else if (family == "xc6s")
 			ff_map_file = "+/xilinx/xc6s_ff_map.v";
 		else
@@ -280,13 +280,22 @@ struct SynthXilinxPass : public ScriptPass
 			else
 				run("read_verilog -lib +/xilinx/cells_sim.v");
 
-			run("read_verilog -lib +/xilinx/cells_xtra.v");
+			if (help_mode)
+				run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
+			else if (family == "xc6s")
+				run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
+			else if (family == "xc6v")
+				run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
+			else if (family == "xc7")
+				run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
+			else if (family == "xcu" || family == "xcup")
+				run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
 
 			if (help_mode) {
 				run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
 			} else if (family == "xc6s") {
 				run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
-			} else if (family == "xc7") {
+			} else if (family == "xc6v" || family == "xc7") {
 				run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
 			}
 
@@ -337,7 +346,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family == "xc6s") {
 					run("memory_bram -rules +/xilinx/xc6s_brams.txt");
 					run("techmap -map +/xilinx/xc6s_brams_map.v");
-				} else if (family == "xc7") {
+				} else if (family == "xc6v" || family == "xc7") {
 					run("memory_bram -rules +/xilinx/xc7_brams.txt");
 					run("techmap -map +/xilinx/xc7_brams_map.v");
 				} else {
-- 
cgit v1.2.3


From 13fa873f11c8332a10c1dda9e42c62b20e93c6b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Wed, 28 Aug 2019 15:28:01 +0000
Subject: Use extractinv for synth_xilinx -ise

---
 techlibs/xilinx/synth_xilinx.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7467e024c..173841799 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -485,8 +485,10 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					run("clkbufmap -buf BUFG O:I");
 			}
-			if (do_iopad)
+			if (help_mode || do_iopad)
 				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
+			if (help_mode || ise)
+				run("extractinv -inv INV O:I", "(only if '-ise')");
 		}
 
 		if (check_label("check")) {
-- 
cgit v1.2.3


From 95db2489bdb515a2e9d3a995574adc8c1071d3c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 14:58:06 -0700
Subject: synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2

---
 techlibs/xilinx/synth_xilinx.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2ac254a1f..b55c40764 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -342,7 +342,10 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_dsp"), "(skip if '-nodsp')") {
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
-				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 "
+						"-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 				run("xilinx_dsp");
 				run("chtype -set $mul t:$__soft_mul");
 			}
-- 
cgit v1.2.3


From 289cf688b76328d62c7416d1327d2d6777b0ffd9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 09:02:29 -0700
Subject: Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6687a0786..022b0d108 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -343,7 +343,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nodsp || help_mode) {
 				// NB: Xilinx multipliers are signed only
 				run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 "
-						"-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 				run("xilinx_dsp");
-- 
cgit v1.2.3


From 23d90e0439ffef510632ce45a3d2aff1c129f405 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 18:56:02 -0700
Subject: Add a xilinx_finalise pass

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 022b0d108..c2f8279c2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -512,6 +512,8 @@ struct SynthXilinxPass : public ScriptPass
 				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
 			if (help_mode || ise)
 				run("extractinv -inv INV O:I", "(only if '-ise')");
+			if (help_mode || !nodsp)
+				run("xilinx_finalise", "(skip if '-nodsp')");
 		}
 
 		if (check_label("check")) {
-- 
cgit v1.2.3


From 27167848f4c5709c6ca3cb0897bac91c4a2a7cbe Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 19:52:55 -0700
Subject: Revert "Add a xilinx_finalise pass"

This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405.
---
 techlibs/xilinx/synth_xilinx.cc | 2 --
 1 file changed, 2 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c2f8279c2..022b0d108 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -512,8 +512,6 @@ struct SynthXilinxPass : public ScriptPass
 				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
 			if (help_mode || ise)
 				run("extractinv -inv INV O:I", "(only if '-ise')");
-			if (help_mode || !nodsp)
-				run("xilinx_finalise", "(skip if '-nodsp')");
 		}
 
 		if (check_label("check")) {
-- 
cgit v1.2.3


From 53ea5daa42db335a69d3fccbf237fe5555f4bccb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 25 Sep 2019 14:04:36 -0700
Subject: Call 'wreduce' after mul2dsp to avoid unextend()

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 022b0d108..ca108e9d6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -346,6 +346,7 @@ struct SynthXilinxPass : public ScriptPass
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+				run("wreduce t:$add");
 				run("xilinx_dsp");
 				run("chtype -set $mul t:$__soft_mul");
 			}
-- 
cgit v1.2.3


From 27e5bf5aad229ef330bfea932f6b194ec5c09b68 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 09:57:11 -0700
Subject: Stop trying to be too smart by prematurely optimising

---
 techlibs/xilinx/synth_xilinx.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ca108e9d6..b87fa9f6f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -346,7 +346,9 @@ struct SynthXilinxPass : public ScriptPass
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
-				run("wreduce t:$add");
+				run("opt_expr -fine a:mul2dsp");
+				run("wreduce a:mul2dsp");
+				run("setattr -unset mul2dsp a:mul2dsp");
 				run("xilinx_dsp");
 				run("chtype -set $mul t:$__soft_mul");
 			}
-- 
cgit v1.2.3


From 781dda6175c86fcb2b08d055565d3d99a687e636 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 10:15:05 -0700
Subject: select once

---
 techlibs/xilinx/synth_xilinx.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b87fa9f6f..0445eb720 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -346,9 +346,11 @@ struct SynthXilinxPass : public ScriptPass
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
-				run("opt_expr -fine a:mul2dsp");
-				run("wreduce a:mul2dsp");
-				run("setattr -unset mul2dsp a:mul2dsp");
+				run("select a:mul2dsp");
+				run("opt_expr -fine"):
+				run("wreduce");
+				run("setattr -unset mul2dsp");
+				run("select -clear");
 				run("xilinx_dsp");
 				run("chtype -set $mul t:$__soft_mul");
 			}
-- 
cgit v1.2.3


From 033aefc0f44abdca50e34cad884c81875dcd7441 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 10:34:14 -0700
Subject: Typo

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0445eb720..d73cc3b16 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -347,7 +347,7 @@ struct SynthXilinxPass : public ScriptPass
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 				run("select a:mul2dsp");
-				run("opt_expr -fine"):
+				run("opt_expr -fine");
 				run("wreduce");
 				run("setattr -unset mul2dsp");
 				run("select -clear");
-- 
cgit v1.2.3


From 143f82def2030527a4fa92b7ba60b704aad08e53 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 11:13:08 -0700
Subject: Missing an '&'

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 173841799..888b5ed7b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -244,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
-		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s")
+		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
 			log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
 
 		if (widemux != 0 && widemux < 2)
-- 
cgit v1.2.3


From b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 14:32:07 -0700
Subject: Re-order

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx/synth_xilinx.cc')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d73cc3b16..6c58e0913 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -347,9 +347,9 @@ struct SynthXilinxPass : public ScriptPass
 						"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
 						"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
 				run("select a:mul2dsp");
+				run("setattr -unset mul2dsp");
 				run("opt_expr -fine");
 				run("wreduce");
-				run("setattr -unset mul2dsp");
 				run("select -clear");
 				run("xilinx_dsp");
 				run("chtype -set $mul t:$__soft_mul");
-- 
cgit v1.2.3