From c9ab18889a63f74534c6fe9184ccb32e3661ab90 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 28 Feb 2019 09:32:29 -0800 Subject: synth_xilinx to now have shregmap call after dff2dffe --- techlibs/xilinx/synth_xilinx.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c11d885d..afd868743 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -103,6 +103,7 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); + log(" shregmap -init\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); @@ -222,6 +223,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); + Pass::call(design, "shregmap -init"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); -- cgit v1.2.3 From 68f38f2ee0e82ac7250e8c4b257e33fd62d21544 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 28 Feb 2019 10:21:05 -0800 Subject: synth_xilinx to use shregmap with -params too --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index afd868743..4e4139154 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -223,7 +223,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "shregmap -init"); + Pass::call(design, "shregmap -init -params"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); -- cgit v1.2.3 From fe4d6898de378260c659dca08398fa434d71f7f0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 28 Feb 2019 11:17:13 -0800 Subject: synth_xilinx to call shregmap with enable support --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4e4139154..280c6b729 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -223,7 +223,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "shregmap -init -params"); + Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); -- cgit v1.2.3 From edca2f116373df7819ec68906ce74f15456168c2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 Mar 2019 17:13:52 -0700 Subject: Move shregmap until after first techmap --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 280c6b729..ce597ea4a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -103,9 +103,9 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); - log(" shregmap -init\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); + log(" shregmap -init -params -enpol any_or_none\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -223,9 +223,9 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "opt -fast"); } -- cgit v1.2.3 From 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 Mar 2019 08:10:02 -0700 Subject: Add shregmap -init_msb_first and use in synth_xilinx --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ce597ea4a..71b468e38 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -105,7 +105,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init -params -enpol any_or_none\n"); + log(" shregmap -init_msb_first -params -enpol any_or_none\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -225,7 +225,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); - Pass::call(design, "shregmap -init -params -enpol any_or_none"); + Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none"); Pass::call(design, "opt -fast"); } -- cgit v1.2.3 From 8af9979aab5f1434ee7d0e56a85324d78e2fd9f9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 Mar 2019 09:01:48 -0700 Subject: Revert "Add shregmap -init_msb_first and use in synth_xilinx" This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75. --- techlibs/xilinx/synth_xilinx.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 169f3b7ce..1978ccf21 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -111,7 +111,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init_msb_first -params -enpol any_or_none\n"); + log(" shregmap -init -params -enpol any_or_none\n"); log(" techmap -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -262,9 +262,8 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } - Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none"); + Pass::call(design, "shregmap -initt -params -enpol any_or_none"); Pass::call(design, "techmap -map +/xilinx/ff_map.v"); - Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } -- cgit v1.2.3 From af5706c2a38c010e6c7343aeb1c5d6e26a6b7799 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 Mar 2019 09:06:56 -0700 Subject: Misspell --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1978ccf21..f2c3833a4 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -262,7 +262,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } - Pass::call(design, "shregmap -initt -params -enpol any_or_none"); + Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "techmap -map +/xilinx/ff_map.v"); Pass::call(design, "opt -fast"); } -- cgit v1.2.3 From 06f8f2654abdef8684bfe4f373ac42cb8c62ee2a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 15 Mar 2019 19:13:40 -0700 Subject: Working --- techlibs/xilinx/synth_xilinx.cc | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f2c3833a4..443ac4eed 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,9 +110,8 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init -params -enpol any_or_none\n"); - log(" techmap -map +/xilinx/ff_map.v\n"); + log(" shregmap -tech xilinx\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -256,14 +255,17 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); + Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "shregmap -tech xilinx"); + Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_"); + Pass::call(design, "opt -fast"); + if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } - Pass::call(design, "shregmap -init -params -enpol any_or_none"); - Pass::call(design, "techmap -map +/xilinx/ff_map.v"); Pass::call(design, "opt -fast"); } -- cgit v1.2.3 From 29a8d4745eb4ecd2947694d02f51c9333bf3ac21 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 15 Mar 2019 23:01:40 -0700 Subject: Cleanup synth_xilinx --- techlibs/xilinx/synth_xilinx.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 443ac4eed..763732fe5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,6 +110,7 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); + log(" simplemap t:$dff*\n"); log(" shregmap -tech xilinx\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); log(" opt -fast\n"); @@ -257,8 +258,6 @@ struct SynthXilinxPass : public Pass Pass::call(design, "simplemap t:$dff*"); Pass::call(design, "shregmap -tech xilinx"); - Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_"); - Pass::call(design, "opt -fast"); if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); -- cgit v1.2.3 From ae2a625d0507c9e7476497e0064ffa003aa761f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 19 Mar 2019 16:14:08 -0700 Subject: Restore original synth_xilinx commands --- techlibs/xilinx/synth_xilinx.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 61895e032..0eccb97f2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -112,7 +112,7 @@ struct SynthXilinxPass : public Pass log(" opt -full\n"); log(" simplemap t:$dff*\n"); log(" shregmap -tech xilinx\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -266,6 +266,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } + Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } -- cgit v1.2.3 From 4cc6b3e942a54e94f472df7817788dc321955a20 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Mar 2019 15:04:44 -0700 Subject: Add '-nosrl' option to synth_xilinx --- techlibs/xilinx/synth_xilinx.cc | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0eccb97f2..5237cc4c6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,10 +64,13 @@ struct SynthXilinxPass : public Pass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -nobram\n"); - log(" disable infering of block rams\n"); + log(" disable inference of block rams\n"); log("\n"); log(" -nodram\n"); - log(" disable infering of distributed rams\n"); + log(" disable inference of distributed rams\n"); + log("\n"); + log(" -nobram\n"); + log(" disable inference of shift registers\n"); log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -110,8 +113,8 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff*\n"); - log(" shregmap -tech xilinx\n"); + log(" simplemap t:$dff* (only without -nosrl)\n"); + log(" shregmap -tech xilinx (only without -nosrl)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -149,6 +152,7 @@ struct SynthXilinxPass : public Pass bool vpr = false; bool nobram = false; bool nodram = false; + bool nosrl = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -193,6 +197,10 @@ struct SynthXilinxPass : public Pass nodram = true; continue; } + if (args[argidx] == "-nosrl") { + nosrl = true; + continue; + } break; } extra_args(args, argidx, design); @@ -257,8 +265,10 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); - Pass::call(design, "simplemap t:$dff*"); - Pass::call(design, "shregmap -tech xilinx"); + if (!nosrl) { + Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "shregmap -tech xilinx"); + } if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); -- cgit v1.2.3 From f9fb05cf6684d855ce2fc776a20cd5552a4ef4a8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 Mar 2019 13:18:55 -0700 Subject: synth_xilinx to use shregmap with -minlen 3 --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5237cc4c6..b6225a1a3 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -114,7 +114,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" simplemap t:$dff* (only without -nosrl)\n"); - log(" shregmap -tech xilinx (only without -nosrl)\n"); + log(" shregmap -tech xilinx -minlen 3 (only without -nosrl)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -267,7 +267,7 @@ struct SynthXilinxPass : public Pass if (!nosrl) { Pass::call(design, "simplemap t:$dff*"); - Pass::call(design, "shregmap -tech xilinx"); + Pass::call(design, "shregmap -tech xilinx -minlen 3"); } if (vpr) { -- cgit v1.2.3 From 88630cd02cfb7cb124c949777280b60f66ee5eb5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 3 Apr 2019 07:14:20 -0700 Subject: Disable shregmap in synth_xilinx if -retime --- techlibs/xilinx/synth_xilinx.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b6225a1a3..df30a22de 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,8 +113,8 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff* (only without -nosrl)\n"); - log(" shregmap -tech xilinx -minlen 3 (only without -nosrl)\n"); + log(" simplemap t:$dff* (without -nosrl and without -retime only)\n"); + log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -265,7 +265,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); - if (!nosrl) { + if (!nosrl && !retime) { Pass::call(design, "simplemap t:$dff*"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } -- cgit v1.2.3 From 0e2d929cead2a32ae176a408da257ec5b8b79f47 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 3 Apr 2019 08:28:07 -0700 Subject: -nosrl meant when -nobram --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index df30a22de..601a6811d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -69,7 +69,7 @@ struct SynthXilinxPass : public Pass log(" -nodram\n"); log(" disable inference of distributed rams\n"); log("\n"); - log(" -nobram\n"); + log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); log(" -run :\n"); -- cgit v1.2.3 From 736e19f02d9980691e244e08b711c5e8c0b4fc76 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 4 Apr 2019 07:39:19 -0700 Subject: t:$dff* -> t:$dff t:$dffe --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 601a6811d..5a3725e7d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,7 +113,7 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff* (without -nosrl and without -retime only)\n"); + log(" simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n"); log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); @@ -266,7 +266,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (!nosrl && !retime) { - Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "simplemap t:$dff t:$dffe"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } -- cgit v1.2.3 From 544843da717734ab9bd9bd88f71db2475fc3abc0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 12:55:52 -0700 Subject: techmap inside map_cells stage --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 326684daf..cabf0b76e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,7 +283,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); -- cgit v1.2.3 From a5f33b5409d9325730204eb776e0046726d55d2c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 16:20:43 -0700 Subject: Move dffinit til after abc --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ee8dec9ee..2676f5915 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -284,8 +284,6 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); } @@ -295,6 +293,8 @@ struct SynthXilinxPass : public Pass Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); } if (check_label(active, run_from, run_to, "check")) -- cgit v1.2.3 From 1d526b7f061fb7e7961fa4d0b318b27cfda469d4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 5 Apr 2019 17:35:49 -0700 Subject: Call shregmap twice -- once for variable, another for fixed --- techlibs/xilinx/synth_xilinx.cc | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2676f5915..57bde998f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,22 +113,23 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n"); - log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n"); + log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); + log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); - log(" techmap -map +/xilinx/cells_map.v\n"); - log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); - log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); + log(" techmap -map +/techmap.v -map +/xilinx/cells_map.v\n"); log(" clean\n"); log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); - log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); + log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); + log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); + log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); @@ -266,7 +267,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); - if (!nosrl && !retime) { + if (!nosrl) { Pass::call(design, "simplemap t:$dff t:$dffe"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } @@ -292,7 +293,9 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); + if (!nosrl) + Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); } -- cgit v1.2.3 From d99422411f568d6d8d7de7d11346718e70012df4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 21 Apr 2019 14:16:34 -0700 Subject: Use new pmux2shiftx from #944, remove my old attempt --- techlibs/xilinx/synth_xilinx.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 57bde998f..4f02a47ea 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -112,9 +112,11 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); - log(" opt -full\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); + log(" pmux2shiftx (without '-nosrl' only)\n"); + log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); + log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); @@ -261,17 +263,20 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "opt -fast -full"); + Pass::call(design, "opt -fast"); Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "opt -full"); if (!nosrl) { Pass::call(design, "simplemap t:$dff t:$dffe"); + Pass::call(design, "pmux2shiftx"); + Pass::call(design, "opt_expr -mux_undef"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } + Pass::call(design, "opt -full"); + if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { -- cgit v1.2.3 From ae95aba60a573bf34034d6a70931bd55490d3f14 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 21 Apr 2019 14:16:59 -0700 Subject: Add comments --- techlibs/xilinx/synth_xilinx.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4f02a47ea..f59c0c622 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -269,8 +269,15 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); if (!nosrl) { + // shregmap operates on bit-level flops, not word-level, + // so break those down here Pass::call(design, "simplemap t:$dff t:$dffe"); + // shregmap -tech xilinx can cope with $shiftx and $mux + // cells for identifiying variable-length shift registers, + // so attempt to convert $pmux-es to the former Pass::call(design, "pmux2shiftx"); + // pmux2shiftx can leave behind a $pmux with a single entry + // -- need this to clean that up Pass::call(design, "opt_expr -mux_undef"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } -- cgit v1.2.3 From d342b5b135a85da0df5df0fa2acc25dec5605760 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 21 Apr 2019 15:33:03 -0700 Subject: Tidy up, fix for -nosrl --- techlibs/xilinx/synth_xilinx.cc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a9e50329c..e84a6714b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -116,8 +116,7 @@ struct SynthXilinxPass : public Pass log(" pmux2shiftx (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); - log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); + log(" techmap -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); @@ -125,7 +124,8 @@ struct SynthXilinxPass : public Pass log(" clean\n"); log("\n"); log(" map_luts:\n"); - log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); + log(" opt -full\n"); + log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n"); @@ -282,12 +282,10 @@ struct SynthXilinxPass : public Pass Pass::call(design, "shregmap -tech xilinx -minlen 3"); } - Pass::call(design, "opt -full"); - if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v"); } Pass::call(design, "hierarchy -check"); @@ -302,7 +300,8 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); + Pass::call(design, "opt -full"); + Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); if (!nosrl) -- cgit v1.2.3 From 0e76718720895a4985a7fad24052a61550acdeda Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 10:45:39 -0700 Subject: Move 'shregmap -tech xilinx' into map_cells --- techlibs/xilinx/synth_xilinx.cc | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1449e792f..d6e7c2623 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -112,14 +112,14 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); - log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); - log(" pmux2shiftx (without '-nosrl' only)\n"); - log(" opt_expr -mux_undef (without '-nosrl' only)\n"); - log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); log(" techmap -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); + log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); + log(" pmux2shiftx (without '-nosrl' only)\n"); + log(" opt_expr -mux_undef (without '-nosrl' only)\n"); + log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); log(" techmap -map +/xilinx/cells_map.v\n"); log(" clean\n"); log("\n"); @@ -269,6 +269,18 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); + if (vpr) { + Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + } else { + Pass::call(design, "techmap -map +/xilinx/arith_map.v"); + } + + Pass::call(design, "hierarchy -check"); + Pass::call(design, "opt -fast"); + } + + if (check_label(active, run_from, run_to, "map_cells")) + { if (!nosrl) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -278,23 +290,12 @@ struct SynthXilinxPass : public Pass // so attempt to convert $pmux-es to the former Pass::call(design, "pmux2shiftx"); // pmux2shiftx can leave behind a $pmux with a single entry - // -- need this to clean that up + // -- need this to clean that up before shregmap Pass::call(design, "opt_expr -mux_undef"); + // shregmap with '-tech xilinx' infers variable length shift regs Pass::call(design, "shregmap -tech xilinx -minlen 3"); } - if (vpr) { - Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - } else { - Pass::call(design, "techmap -map +/xilinx/arith_map.v"); - } - - Pass::call(design, "hierarchy -check"); - Pass::call(design, "opt -fast"); - } - - if (check_label(active, run_from, run_to, "map_cells")) - { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "clean"); } @@ -305,6 +306,8 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); + // This shregmap call infers fixed length shift registers after abc + // has performed any necessary retiming if (!nosrl) Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); -- cgit v1.2.3 From ec88129a5cf510afc39ea12efa6059bed3eadfc3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 11:38:23 -0700 Subject: Update help message --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/synth_xilinx.cc') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d6e7c2623..53eee7962 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -108,7 +108,7 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/xilinx/drams_map.v\n"); log("\n"); log(" fine:\n"); - log(" opt -fast -full\n"); + log(" opt -fast\n"); log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); -- cgit v1.2.3