From de79978372c1953e295fa262444cb0a28a246c5f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 23 Sep 2020 09:15:24 -0700 Subject: xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled --- techlibs/xilinx/xc7_dsp_map.v | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/xilinx/xc7_dsp_map.v') diff --git a/techlibs/xilinx/xc7_dsp_map.v b/techlibs/xilinx/xc7_dsp_map.v index a4256eb92..58df977ec 100644 --- a/techlibs/xilinx/xc7_dsp_map.v +++ b/techlibs/xilinx/xc7_dsp_map.v @@ -33,6 +33,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .B(B), .C(48'b0), .D(25'b0), + .CARRYIN(1'b0), .P(P_48), .INMODE(5'b00000), -- cgit v1.2.3