From 895e2befa76bd326cc47fd40de112ea067fcaf98 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 19:04:07 -0700 Subject: Vivado does not like zero width port connections --- techlibs/xilinx/xilinx_finalise.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/xilinx_finalise.cc') diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc index db73babe3..2c0bd3534 100644 --- a/techlibs/xilinx/xilinx_finalise.cc +++ b/techlibs/xilinx/xilinx_finalise.cc @@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass for (auto cell : module->selected_cells()) { if (cell->type != ID(DSP48E1)) continue; - for (auto &conn : cell->connections_) { + for (auto conn : cell->connections()) { if (!cell->output(conn.first)) continue; bool purge = true; @@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass if (purge) { log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); - conn.second = SigSpec(); + cell->unsetPort(conn.first); } } } -- cgit v1.2.3