From 738fdfe8f55e18ac7f315cd68c117eae370004ca Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:20:46 -0700
Subject: Remove wide mux inference

---
 techlibs/xilinx/Makefile.inc    |   1 -
 techlibs/xilinx/cells_map.v     | 120 ----------------------------------------
 techlibs/xilinx/mux_map.v       |  52 -----------------
 techlibs/xilinx/synth_xilinx.cc |  24 +-------
 4 files changed, 3 insertions(+), 194 deletions(-)
 delete mode 100644 techlibs/xilinx/mux_map.v

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 2f3945167..296edace9 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,7 +30,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
 
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f8f9356bc..6b92d2ea9 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -142,123 +142,3 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
     end
   endgenerate
 endmodule
-
-module \$__XILINX_SHIFTX (A, B, Y);
-  parameter A_SIGNED = 0;
-  parameter B_SIGNED = 0;
-  parameter A_WIDTH = 1;
-  parameter B_WIDTH = 1;
-  parameter Y_WIDTH = 1;
-
-  input [A_WIDTH-1:0] A;
-  input [B_WIDTH-1:0] B;
-  output [Y_WIDTH-1:0] Y;
-
-  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
-  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
-
-  function integer compute_num_leading_X_in_A;
-    integer i, c;
-  begin
-    compute_num_leading_X_in_A = 0;
-    c = 1;
-    for (i = A_WIDTH-1; i >= 0; i=i-1) begin
-      if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
-        c = 0;
-      compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
-    end
-  end
-  endfunction
-  localparam num_leading_X_in_A = compute_num_leading_X_in_A();
-
-  generate
-    genvar i, j;
-    // Bit-blast
-    if (Y_WIDTH > 1) begin
-      for (i = 0; i < Y_WIDTH; i++)
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
-    end
-    // If the LSB of B is constant zero (and Y_WIDTH is 1) then
-    //   we can optimise by removing every other entry from A
-    //   and popping the constant zero from B
-    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
-      wire [(A_WIDTH+1)/2-1:0] A_i;
-      for (i = 0; i < (A_WIDTH+1)/2; i++)
-        assign A_i[i] = A[i*2];
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
-    end
-    // Trim off any leading 1'bx -es in A, and resize B accordingly
-    else if (num_leading_X_in_A > 0) begin
-      localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
-      localparam B_WIDTH_new = $clog2(A_WIDTH_new);
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
-    end
-    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
-    end
-    else if (B_WIDTH == 3) begin
-      localparam a_width0 = 2 ** 2;
-      localparam a_widthN = A_WIDTH - a_width0;
-      wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
-      if (a_widthN > 1)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      else
-        assign T1 = A[A_WIDTH-1];
-      MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
-    end
-    else if (B_WIDTH == 4) begin
-      localparam a_width0 = 2 ** 2;
-      localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [4-1:0] T;
-      wire T0, T1;
-      for (i = 0; i < 4; i++)
-        if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
-        else
-          assign T[i] = 1'bx;
-      MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
-      MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
-      MUXF8 fpga_hard_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
-    end
-    else begin
-      localparam a_width0 = 2 ** 4;
-      localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [(2**(B_WIDTH-4))-1:0] T;
-      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
-        if (i < num_mux16)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
-        else if (i == num_mux16 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
-        else
-          assign T[i] = 1'bx;
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
-    end
-  endgenerate
-endmodule
-
-module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
-input A, B, C, D, E, F, G, H, S, T, U;
-output Y;
-  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
-endmodule
-
-module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
-input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
-output Y;
-  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
-endmodule
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
deleted file mode 100644
index 0fa8db736..000000000
--- a/techlibs/xilinx/mux_map.v
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *                2019  Eddie Hung    <eddie@fpgeh.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-module \$shiftx (A, B, Y);
-  parameter A_SIGNED = 0;
-  parameter B_SIGNED = 0;
-  parameter A_WIDTH = 1;
-  parameter B_WIDTH = 1;
-  parameter Y_WIDTH = 1;
-
-  input [A_WIDTH-1:0] A;
-  input [B_WIDTH-1:0] B;
-  output [Y_WIDTH-1:0] Y;
-
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
-
-  generate
-    genvar i, j;
-    // TODO: Check if this opt still necessary
-    if (B_SIGNED) begin
-      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
-        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
-      else
-        wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-    else begin
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
-    end
-  endgenerate
-endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f966115cd..42a3bba12 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -70,9 +70,6 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nosrl\n");
 		log("        disable inference of shift registers\n");
 		log("\n");
-		log("    -nomux\n");
-		log("        disable inference of wide multiplexers\n");
-		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -94,7 +91,7 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, abc, arch;
-	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
+	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -109,7 +106,6 @@ struct SynthXilinxPass : public ScriptPass
 		nobram = false;
 		nodram = false;
 		nosrl = false;
-		nomux = false;
 		arch = "xc7";
 	}
 
@@ -173,10 +169,6 @@ struct SynthXilinxPass : public ScriptPass
 				nosrl = true;
 				continue;
 			}
-			if (args[argidx] == "-nomux") {
-				nomux = true;
-				continue;
-			}
 			if (args[argidx] == "-abc9") {
 				abc = "abc9";
 				continue;
@@ -225,15 +217,11 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("coarse")) {
 			run("synth -run coarse");
 
-			//if (!nomux || help_mode)
-			//	run("muxpack", "(skip if '-nomux')");
-
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
-			// Also: wide multiplexer inference benefits from this too
-			if (!(nosrl && nomux) || help_mode)
-				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
+			if (!nosrl || help_mode)
+				run("pmux2shiftx", "(skip if '-nosrl')");
 
 			// Run a number of peephole optimisations, including one
 			//   that optimises $mul cells driving $shiftx's B input
@@ -271,10 +259,6 @@ struct SynthXilinxPass : public ScriptPass
 			}
 
 			std::string techmap_files = " -map +/techmap.v";
-			if (help_mode)
-					techmap_files += " [-map +/xilinx/mux_map.v]";
-			else if (!nomux)
-					techmap_files += " -map +/xilinx/mux_map.v";
 			if (help_mode)
 					techmap_files += " [-map +/xilinx/arith_map.v]";
 			else if (!nocarry) {
@@ -289,8 +273,6 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			if (!nomux || help_mode)
-				run("muxcover -mux8 -mux16", "(skip if '-nomux')");
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
-- 
cgit v1.2.3


From 99267f660f5aca3d84d885a27aad54ae3e4e8044 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:21:52 -0700
Subject: Fix spacing

---
 techlibs/xilinx/synth_xilinx.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 42a3bba12..56a3eb6fc 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -260,13 +260,13 @@ struct SynthXilinxPass : public ScriptPass
 
 			std::string techmap_files = " -map +/techmap.v";
 			if (help_mode)
-					techmap_files += " [-map +/xilinx/arith_map.v]";
+				techmap_files += " [-map +/xilinx/arith_map.v]";
 			else if (!nocarry) {
-					techmap_files += " -map +/xilinx/arith_map.v";
-					if (vpr)
-							techmap_files += " -D _EXPLICIT_CARRY";
-					else if (abc == "abc9")
-							techmap_files += " -D _CLB_CARRY";
+				techmap_files += " -map +/xilinx/arith_map.v";
+				if (vpr)
+					techmap_files += " -D _EXPLICIT_CARRY";
+				else if (abc == "abc9")
+					techmap_files += " -D _CLB_CARRY";
 			}
 			run("techmap " + techmap_files);
 			run("opt -fast");
-- 
cgit v1.2.3


From c7f5091c2fac374c4e48cd9736c2727d65acdcf9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:34:41 -0700
Subject: Reduce diff with master

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 56a3eb6fc..3ac19e498 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
-- 
cgit v1.2.3


From 009255d11d37beaeca95a59e5b484d44b39b980a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 28 Apr 2019 12:36:04 -0700
Subject: Move neg-pol to pos-pol mapping from ff_map to cells_map.v

---
 techlibs/xilinx/cells_map.v | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 6b92d2ea9..8291f5647 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -18,6 +18,14 @@
  *
  */
 
+// Convert negative-polarity reset to positive-polarity
+module  \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+
+module  \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+
+
 module \$__SHREG_ (input C, input D, input E, output Q);
   parameter DEPTH = 0;
   parameter [DEPTH-1:0] INIT = 0;
-- 
cgit v1.2.3


From 75d89e56cfd9472605f27570cf2760ff89dc7603 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 14:27:07 -0700
Subject: Fix name clash

---
 techlibs/xilinx/cells_map.v | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 8291f5647..b5114758c 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -19,11 +19,15 @@
  */
 
 // Convert negative-polarity reset to positive-polarity
-module  \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_NN0_" *)
+module _90_dff_nn0_to_np0(input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_PN0_" *)
+module _90_dff_pn0_to_pp0(input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 
-module  \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_NN1_" *)
+module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_PN1_" *)
+module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 
 
 module \$__SHREG_ (input C, input D, input E, output Q);
-- 
cgit v1.2.3


From 627a62a797ef9e676ba9d89f53f927d0c2463585 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:32:46 -0700
Subject: Make doc consistent

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3ac19e498..69a3d99c2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -82,7 +82,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        run 'abc' with -dff option\n");
 		log("\n");
 		log("    -abc9\n");
-		log("        use abc9 instead of abc\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
-- 
cgit v1.2.3


From ee428f73abdbbde95601e583db186d86a8fa6b91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:37:52 -0700
Subject: Remove WIP ABC9 flop support

---
 techlibs/xilinx/brams_bb.v  | 16 ++++++++--------
 techlibs/xilinx/cells_sim.v | 20 ++++++++++----------
 2 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/brams_bb.v b/techlibs/xilinx/brams_bb.v
index f540d299d..a682ba4a7 100644
--- a/techlibs/xilinx/brams_bb.v
+++ b/techlibs/xilinx/brams_bb.v
@@ -19,10 +19,10 @@ module RAMB18E1 (
 	input [1:0] WEA,
 	input [3:0] WEBWE,
 
-	(* abc_flop_q *) output [15:0] DOADO,
-	(* abc_flop_q *) output [15:0] DOBDO,
-	(* abc_flop_q *) output [1:0] DOPADOP,
-	(* abc_flop_q *) output [1:0] DOPBDOP
+	output [15:0] DOADO,
+	output [15:0] DOBDO,
+	output [1:0] DOPADOP,
+	output [1:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -143,10 +143,10 @@ module RAMB36E1 (
 	input [3:0] WEA,
 	input [7:0] WEBWE,
 
-	(* abc_flop_q *) output [31:0] DOADO,
-	(* abc_flop_q *) output [31:0] DOBDO,
-	(* abc_flop_q *) output [3:0] DOPADOP,
-	(* abc_flop_q *) output [3:0] DOPBDOP
+	output [31:0] DOADO,
+	output [31:0] DOBDO,
+	output [3:0] DOPADOP,
+	output [3:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d9aa36666..bf7a0ed44 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -205,7 +205,7 @@ endmodule
 
 `endif
 
-module FDRE ((* abc_flop_q *) output reg Q, input C, CE, D, R);
+module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -217,7 +217,7 @@ module FDRE ((* abc_flop_q *) output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
-module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
+module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -229,7 +229,7 @@ module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
-module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
+module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -243,7 +243,7 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
-module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
+module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -257,25 +257,25 @@ module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
-module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
+module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
+module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
@@ -315,7 +315,7 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  (* abc_flop_q *) output Q,
+  output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -333,7 +333,7 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  (* abc_flop_q *) output Q,
+  output Q,
   output Q31,
   input [4:0] A,
   input CE, CLK, D
-- 
cgit v1.2.3


From d47ff7ba8702f9ec76514cbbec1e447c454f5699 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:51:11 -0700
Subject: Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}

---
 techlibs/xilinx/Makefile.inc    |  4 +--
 techlibs/xilinx/abc.box         | 62 -----------------------------------------
 techlibs/xilinx/abc.lut         | 14 ----------
 techlibs/xilinx/abc_xc7.box     | 62 +++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_xc7.lut     | 14 ++++++++++
 techlibs/xilinx/synth_xilinx.cc |  2 +-
 6 files changed, 79 insertions(+), 79 deletions(-)
 delete mode 100644 techlibs/xilinx/abc.box
 delete mode 100644 techlibs/xilinx/abc.lut
 create mode 100644 techlibs/xilinx/abc_xc7.box
 create mode 100644 techlibs/xilinx/abc_xc7.lut

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 296edace9..1a652eb27 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,8 +30,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
deleted file mode 100644
index a4182ed63..000000000
--- a/techlibs/xilinx/abc.box
+++ /dev/null
@@ -1,62 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
-
-# F7BMUX slower than F7AMUX
-# Inputs: I0 I1 S0
-# Outputs: O
-F7BMUX 1 1 3 1
-217 223 296
-
-# Inputs: I0 I1 S0
-# Outputs: O
-MUXF8 2 1 3 1
-104 94 273
-
-# CARRY4 + CARRY4_[ABCD]X
-# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
-# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
-#   (NB: carry chain input/output must be last input/output,
-#        swapped with what normally would have been the last
-#        output, here: CI <-> S, CO <-> O
-CARRY4 3 1 10 8
-223 -   -   -   482 -   -   -   -   222
-400 205 -   -   598 407 -   -   -   334
-523 558 226 -   584 556 537 -   -   239
-582 618 330 227 642 615 596 438 -   313
-340 -   -   -   536 379 -   -   -   271
-433 469 -   -   494 465 445 -   -   157
-512 548 292 -   592 540 520 356 -   228
-508 528 378 380 580 526 507 398 385 114
-
-# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-# Outputs: DPO SPO
-RAM64X1D 4 0 15 2
--   -   -   -   -   -   - 124 124 124 124 124 124 - -
-124 124 124 124 124 124 - -   -   -   -   -   124 - -
-
-# SLICEM/A6LUT + F7[AB]MUX
-# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
-# Outputs: DPO SPO
-RAM128X1D 5 0 17 2
--   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
-347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
-
-# Inputs: C CE D R
-# Outputs: Q
-FDRE 6 0 4 1
-- - - -
-
-# Inputs: C CE D S
-# Outputs: Q
-FDSE 7 0 4 1
-- - - -
-
-# Inputs: C CE CLR D
-# Outputs: Q
-FDCE 8 0 4 1
-- - 404 -
-
-# Inputs: C CE D PRE
-# Outputs: Q
-FDPE 9 0 4 1
-- - - 404
diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
deleted file mode 100644
index 3a7dc268d..000000000
--- a/techlibs/xilinx/abc.lut
+++ /dev/null
@@ -1,14 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
-
-# K	area	delay
-1 	1	124
-2	2	124 235
-3	3	124 235 399
-4	3	124 235 399 490
-5	3	124 235 399 490 620
-6	5	124 235 399 490 620 632
-                # F7BMUX
-7	10	296 420 531 695 756 916 928
-                # F8MUX
-                    # F8MUX+F7BMUX
-8	20	273 569 693 804 968 1029 1189 1201
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
new file mode 100644
index 000000000..a4182ed63
--- /dev/null
+++ b/techlibs/xilinx/abc_xc7.box
@@ -0,0 +1,62 @@
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+
+# F7BMUX slower than F7AMUX
+# Inputs: I0 I1 S0
+# Outputs: O
+F7BMUX 1 1 3 1
+217 223 296
+
+# Inputs: I0 I1 S0
+# Outputs: O
+MUXF8 2 1 3 1
+104 94 273
+
+# CARRY4 + CARRY4_[ABCD]X
+# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
+# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
+#   (NB: carry chain input/output must be last input/output,
+#        swapped with what normally would have been the last
+#        output, here: CI <-> S, CO <-> O
+CARRY4 3 1 10 8
+223 -   -   -   482 -   -   -   -   222
+400 205 -   -   598 407 -   -   -   334
+523 558 226 -   584 556 537 -   -   239
+582 618 330 227 642 615 596 438 -   313
+340 -   -   -   536 379 -   -   -   271
+433 469 -   -   494 465 445 -   -   157
+512 548 292 -   592 540 520 356 -   228
+508 528 378 380 580 526 507 398 385 114
+
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
+# Outputs: DPO SPO
+RAM64X1D 4 0 15 2
+-   -   -   -   -   -   - 124 124 124 124 124 124 - -
+124 124 124 124 124 124 - -   -   -   -   -   124 - -
+
+# SLICEM/A6LUT + F7[AB]MUX
+# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
+# Outputs: DPO SPO
+RAM128X1D 5 0 17 2
+-   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
+347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
+
+# Inputs: C CE D R
+# Outputs: Q
+FDRE 6 0 4 1
+- - - -
+
+# Inputs: C CE D S
+# Outputs: Q
+FDSE 7 0 4 1
+- - - -
+
+# Inputs: C CE CLR D
+# Outputs: Q
+FDCE 8 0 4 1
+- - 404 -
+
+# Inputs: C CE D PRE
+# Outputs: Q
+FDPE 9 0 4 1
+- - - 404
diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc_xc7.lut
new file mode 100644
index 000000000..3a7dc268d
--- /dev/null
+++ b/techlibs/xilinx/abc_xc7.lut
@@ -0,0 +1,14 @@
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+
+# K	area	delay
+1 	1	124
+2	2	124 235
+3	3	124 235 399
+4	3	124 235 399 490
+5	3	124 235 399 490 620
+6	5	124 235 399 490 620 632
+                # F7BMUX
+7	10	296 420 531 695 756 916 928
+                # F8MUX
+                    # F8MUX+F7BMUX
+8	20	273 569 693 804 968 1029 1189 1201
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 69a3d99c2..2308ddadd 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -279,7 +279,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
+				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W 160" + string(retime ? " -dff" : ""));
 			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 			else
-- 
cgit v1.2.3


From ba4b4a0088ff7ae37b86f0c22cf2a95f0aba9e13 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 11:33:10 -0700
Subject: Update delays based on SymbiFlow/prjxray-db

---
 techlibs/xilinx/abc_xc7.lut | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc_xc7.lut
index 3a7dc268d..2e6906945 100644
--- a/techlibs/xilinx/abc_xc7.lut
+++ b/techlibs/xilinx/abc_xc7.lut
@@ -1,14 +1,15 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf
+#            and  https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json
 
 # K	area	delay
-1 	1	124
-2	2	124 235
-3	3	124 235 399
-4	3	124 235 399 490
-5	3	124 235 399 490 620
-6	5	124 235 399 490 620 632
-                # F7BMUX
-7	10	296 420 531 695 756 916 928
-                # F8MUX
-                    # F8MUX+F7BMUX
-8	20	273 569 693 804 968 1029 1189 1201
+1 	1	127
+2	2	127 238
+3	3	127 238 407
+4	3	127 238 407 472
+5	3	127 238 407 472 631
+6	5	127 238 407 472 631 642
+        # F7AMUX + F7BMUX / 2
+7	10	286 413 524 693 758 917 928
+        # F8MUX
+            # F8MUX+F7MUX
+8	20	273 559 686 797 966 1031 1190 1201
-- 
cgit v1.2.3


From 2e34859a6b9780d6dc2df28dabcab893b5f4ce4a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 11:38:22 -0700
Subject: Add XC7_WIRE_DELAY macro to synth_xilinx.cc

---
 techlibs/xilinx/synth_xilinx.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2308ddadd..a11648873 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,6 +25,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+#define XC7_WIRE_DELAY "160"
+
 struct SynthXilinxPass : public ScriptPass
 {
 	SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
@@ -279,7 +281,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W 160" + string(retime ? " -dff" : ""));
+				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
 			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 			else
-- 
cgit v1.2.3


From 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 12:43:20 -0700
Subject: As per @daveshah1 remove async DFF timing from xilinx

---
 techlibs/xilinx/abc_xc7.box | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index a4182ed63..8a48bad4e 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -54,9 +54,9 @@ FDSE 7 0 4 1
 # Inputs: C CE CLR D
 # Outputs: Q
 FDCE 8 0 4 1
-- - 404 -
+- - - -
 
 # Inputs: C CE D PRE
 # Outputs: Q
 FDPE 9 0 4 1
-- - - 404
+- - - -
-- 
cgit v1.2.3