From a323881e152c0d51728f3df773ac2f326544b379 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Apr 2020 14:13:38 -0700
Subject: xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells

---
 techlibs/xilinx/cells_sim.v | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index a6eb9a90e..cd611399e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -692,9 +692,14 @@ module FDCE (
     $setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
     $setup(CLR, negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+`ifndef YOSYS
+    if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764;
+    if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764;
+`else
     if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
                                                   // but for facilitating a bypass box, let's pretend it's
                                                   // a simple path
+`endif
     if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
     if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
   endspecify
@@ -720,14 +725,18 @@ module FDCE_1 (
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(CLR, negedge C, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+`ifndef YOSYS
+    (posedge CLR => (Q : 1'b0)) = 764;
+`else
     if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
                                // but for facilitating a bypass box, let's pretend it's
                                // a simple path
+`endif
     if (!CLR && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
-//(* abc9_box, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module FDPE (
   output reg Q,
   (* clkbuf_sink *)
@@ -762,9 +771,14 @@ module FDPE (
     $setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
     $setup(PRE, negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+`ifndef YOSYS
+    if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764;
+    if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764;
+`else
     if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
                                                   // but for facilitating a bypass box, let's pretend it's
                                                   // a simple path
+`endif
     if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
     if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
   endspecify
@@ -790,9 +804,13 @@ module FDPE_1 (
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(PRE, negedge C, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+`ifndef YOSYS
+    (posedge PRE => (Q : 1'b1)) = 764;
+`else
     if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
                                // but for facilitating a bypass box, let's pretend it's
                                // a simple path
+`endif
     if (!PRE && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
-- 
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