From b64b38eea2e9a7de30d6045f069c86bf4446134f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Aug 2014 14:18:40 +0200
Subject: Renamed $lut ports to follow A-Y naming scheme

---
 techlibs/xilinx/cells.v | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v
index 5bf8ccd86..d19be0db7 100644
--- a/techlibs/xilinx/cells.v
+++ b/techlibs/xilinx/cells.v
@@ -10,41 +10,41 @@ module  \$_DFF_P_ (D, C, Q);
 
 endmodule
 
-module \$lut (I, O);
+module \$lut (A, Y);
 
   parameter WIDTH = 0;
   parameter LUT = 0;
 
-  input [WIDTH-1:0] I;
-  output O;
+  input [WIDTH-1:0] A;
+  output Y;
 
   generate
     if (WIDTH == 1) begin:lut1
-      LUT1 #(.INIT(LUT)) fpga_lut (.O(O),
-        .I0(I[0]));
+      LUT1 #(.INIT(LUT)) fpga_lut (.O(Y),
+        .I0(A[0]));
     end else
     if (WIDTH == 2) begin:lut2
-      LUT2 #(.INIT(LUT)) fpga_lut (.O(O),
-        .I0(I[0]), .I1(I[1]));
+      LUT2 #(.INIT(LUT)) fpga_lut (.O(Y),
+        .I0(A[0]), .I1(A[1]));
     end else
     if (WIDTH == 3) begin:lut3
-      LUT3 #(.INIT(LUT)) fpga_lut (.O(O),
-        .I0(I[0]), .I1(I[1]), .I2(I[2]));
+      LUT3 #(.INIT(LUT)) fpga_lut (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]));
     end else
     if (WIDTH == 4) begin:lut4
-      LUT4 #(.INIT(LUT)) fpga_lut (.O(O),
-        .I0(I[0]), .I1(I[1]), .I2(I[2]),
-        .I3(I[3]));
+      LUT4 #(.INIT(LUT)) fpga_lut (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]));
     end else
     if (WIDTH == 5) begin:lut5
-      LUT5 #(.INIT(LUT)) fpga_lut (.O(O),
-        .I0(I[0]), .I1(I[1]), .I2(I[2]),
-        .I3(I[3]), .I4(I[4]));
+      LUT5 #(.INIT(LUT)) fpga_lut (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]));
     end else
     if (WIDTH == 6) begin:lut6
-      LUT6 #(.INIT(LUT)) fpga_lut (.O(O),
-        .I0(I[0]), .I1(I[1]), .I2(I[2]),
-        .I3(I[3]), .I4(I[4]), .I5(I[5]));
+      LUT6 #(.INIT(LUT)) fpga_lut (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
     end else begin:error
       wire _TECHMAP_FAIL_ = 1;
     end
-- 
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