From 004999218f52cd5a1308023a474ee608b842a5b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 May 2020 08:01:27 -0700 Subject: techlibs/common: more robustness when *_WIDTH = 0 --- techlibs/common/cmp2lcu.v | 8 ++++++-- techlibs/common/techmap.v | 29 ++++++++++++++++++++++++----- 2 files changed, 30 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v index b6f4aeed6..e42f346d1 100644 --- a/techlibs/common/cmp2lcu.v +++ b/techlibs/common/cmp2lcu.v @@ -108,8 +108,12 @@ generate // Generate if any comparisons call for it wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG}; end - $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI)) - _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y)); + if (AB_WIDTH == 1) + $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI)) + _TECHMAP_REPLACE_ (.A(), .B(), .P(P_), .G(G_), .Y(Y)); + else + $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI)) + _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y)); end end endgenerate diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index ecf4d5dc5..225cff449 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -285,13 +285,32 @@ module _90_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] AA, BB; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + if (A_WIDTH == 0) begin + wire [Y_WIDTH-1:0] B_buf; + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + assign AA = {Y_WIDTH{1'b0}}; + assign BB = BI ? ~B_buf : B_buf; + end + else if (B_WIDTH == 0) begin + wire [Y_WIDTH-1:0] A_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + + assign AA = A_buf; + assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}}; + end + else begin + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + assign AA = A_buf; + assign BB = BI ? ~B_buf : B_buf; + end + \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO)); assign X = AA ^ BB; -- cgit v1.2.3 From 95fb3cf487544068bc36207d5250a8bcd4386115 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 12 May 2020 21:12:26 +0100 Subject: ecp5: Add missing SERDES parameters Signed-off-by: David Shah --- techlibs/ecp5/cells_bb.v | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index ae124e7a3..756f05366 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -652,6 +652,10 @@ module DCUA( parameter CH1_PROTOCOL = "8B10B"; parameter CH0_CDR_MAX_RATE = "2.5"; parameter CH1_CDR_MAX_RATE = "2.5"; + parameter CH0_TXDEPRE = "DISABLED"; + parameter CH1_TXDEPRE = "DISABLED"; + parameter CH0_TXDEPOST = "DISABLED"; + parameter CH1_TXDEPOST = "DISABLED"; endmodule (* blackbox *) -- cgit v1.2.3 From 4ecae8a6735f71e0dd9e3cc8eb0e7855299a78bc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 12 May 2020 15:40:13 -0700 Subject: ice40: fix whitespace --- techlibs/ice40/synth_ice40.cc | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2b211572d..6e05ab0b2 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -225,10 +225,10 @@ struct SynthIce40Pass : public ScriptPass device_opt = args[++argidx]; continue; } - if (args[argidx] == "-flowmap") { - flowmap = true; - continue; - } + if (args[argidx] == "-flowmap") { + flowmap = true; + continue; + } break; } extra_args(args, argidx, design); @@ -240,13 +240,12 @@ struct SynthIce40Pass : public ScriptPass if (abc9 && retime) log_cmd_error("-retime option not currently compatible with -abc9!\n"); - - if (abc9 && noabc) - log_cmd_error("-abc9 is incompatible with -noabc!\n"); - if (abc9 && flowmap) - log_cmd_error("-abc9 is incompatible with -flowmap!\n"); - if (flowmap && noabc) - log_cmd_error("-flowmap is incompatible with -noabc!\n"); + if (abc9 && noabc) + log_cmd_error("-abc9 is incompatible with -noabc!\n"); + if (abc9 && flowmap) + log_cmd_error("-abc9 is incompatible with -flowmap!\n"); + if (flowmap && noabc) + log_cmd_error("-flowmap is incompatible with -noabc!\n"); log_header(design, "Executing SYNTH_ICE40 pass.\n"); log_push(); @@ -372,10 +371,10 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/ice40/latches_map.v"); if (noabc || flowmap || help_mode) { run("simplemap", " (if -noabc or -flowmap)"); - if (noabc || help_mode) - run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); - if (flowmap || help_mode) - run("flowmap -maxlut 4", "(only if -flowmap)"); + if (noabc || help_mode) + run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); + if (flowmap || help_mode) + run("flowmap -maxlut 4", "(only if -flowmap)"); } if (!noabc) { if (abc9) { -- cgit v1.2.3 From 27b7ffc75444583bbecc70e2d7e2e84bc321f2cf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 12 May 2020 15:40:48 -0700 Subject: ice40: fix ICESTORM_LC process sensitivity --- techlibs/ice40/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 6a0e3031e..5d107989d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1908,7 +1908,7 @@ module ICESTORM_LC ( o_reg <= SR_pd ? SET_NORESET : lut_o; reg o_reg_async = 1'b0; - always @(posedge polarized_clk, posedge SR) + always @(posedge polarized_clk, posedge SR_pd) if (SR_pd) o_reg_async <= SET_NORESET; else if (CEN_pu) -- cgit v1.2.3 From 95763c8d18eec49de3acff5d38a82f54cc25cb1b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 13 Apr 2020 09:38:07 -0700 Subject: abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes --- techlibs/common/abc9_model.v | 3 - techlibs/xilinx/abc9_map.v | 354 ---------------------------------------- techlibs/xilinx/abc9_unmap.v | 4 - techlibs/xilinx/cells_sim.v | 8 +- techlibs/xilinx/synth_xilinx.cc | 5 +- 5 files changed, 5 insertions(+), 369 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v index c0c5dc2fd..9e8048faf 100644 --- a/techlibs/common/abc9_model.v +++ b/techlibs/common/abc9_model.v @@ -1,6 +1,3 @@ -module \$__ABC9_FF_ (input D, output Q); -endmodule - (* abc9_box *) module \$__ABC9_DELAY (input I, output O); parameter DELAY = 0; diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 81f8a1d42..1d733a650 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -22,360 +22,6 @@ // before invoking the `abc9` pass in order to transform the design into // a format that it understands. -`ifdef DFF_MODE -// For example, (complex) flip-flops are expected to be described as an -// combinatorial box (containing all control logic such as clock enable -// or synchronous resets) followed by a basic D-Q flop. -// Yosys will automatically analyse the simulation model (described in -// cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in -// order to extract the combinatorial control logic left behind. -// Specifically, a simulation model similar to the one below: -// -// ++===================================++ -// || Sim model || -// || /\/\/\/\ || -// D -->>-----< > +------+ || -// R -->>-----< Comb. > |$_DFF_| || -// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q -// || +--< > +------+ | || -// || | \/\/\/\/ | || -// || | | || -// || +----------------------------+ || -// || || -// ++===================================++ -// -// is transformed into: -// -// ++==================++ -// || Comb box || -// || || -// || /\/\/\/\ || -// D -->>-----< > || -// R -->>-----< Comb. > || +-----------+ -// CE -->>-----< logic >--->>-- $Q --|$__ABC9_FF_|--+-->> Q -// abc9_ff.Q +-->>-----< > || +-----------+ | -// | || \/\/\/\/ || | -// | || || | -// | ++==================++ | -// | | -// +-----------------------------------------------+ -// -// The purpose of the following FD* rules are to wrap the flop with: -// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 -// the connectivity of its basic D-Q flop -// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to -// capture asynchronous behaviour -// (c) a special abc9_ff.clock wire to capture its clock domain and polarity -// (indicated to `abc9' so that it only performs sequential synthesis -// (with reachability analysis) correctly on one domain at a time) -// (d) an (* abc9_init *) attribute on the $__ABC9_FF_ cell capturing its -// initial state -// NOTE: in order to perform sequential synthesis, `abc9' requires that -// the initial value of all flops be zero -// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback -// into the (combinatorial) FD* cell to facilitate clock-enable behaviour - -module FDRE (output Q, (* techmap_autopurge *) input C, CE, D, R); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - wire QQ, $Q; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDSE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_S_INVERTED(IS_R_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .S(R) - ); - end - else begin - assign Q = QQ; - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_R_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .R(R) - ); - end - endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; -endmodule -module FDRE_1 (output Q, (* techmap_autopurge *) input C, CE, D, R); - parameter [0:0] INIT = 1'b0; - wire QQ, $Q; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDSE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .S(R) - ); - end - else begin - assign Q = QQ; - FDRE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .R(R) - ); - end - endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; -endmodule - -module FDSE (output Q, (* techmap_autopurge *) input C, CE, D, S); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - wire QQ, $Q; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) - ); - end - else begin - assign Q = QQ; - FDSE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_S_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .S(S) - ); - end endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; -endmodule -module FDSE_1 (output Q, (* techmap_autopurge *) input C, CE, D, S); - parameter [0:0] INIT = 1'b1; - wire QQ, $Q; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDRE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) - ); - end - else begin - assign Q = QQ; - FDSE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .S(S) - ); - end endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; -endmodule - -module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire QQ, $Q, $QQ; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDPE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_PRE_INVERTED(IS_CLR_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below - ); - // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); - end - else begin - assign Q = QQ; - FDCE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_CLR_INVERTED(IS_CLR_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below - ); - // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); - end endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; -endmodule -module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR); - parameter [0:0] INIT = 1'b0; - wire QQ, $Q, $QQ; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDPE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below - ); - $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ)); - end - else begin - assign Q = QQ; - FDCE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below - ); - $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ)); - end endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; -endmodule - -module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire QQ, $Q, $QQ; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDCE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_CLR_INVERTED(IS_PRE_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below - ); - $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); - end - else begin - assign Q = QQ; - FDPE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_PRE_INVERTED(IS_PRE_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below - ); - $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); - end endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; -endmodule -module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE); - parameter [0:0] INIT = 1'b1; - wire QQ, $Q, $QQ; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDCE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC0 below - ); - $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ)); - end - else begin - assign Q = QQ; - FDPE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC1 below - ); - $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ)); - end endgenerate - (* abc9_init = 1'b0 *) - $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); - - // Special signals - wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; -endmodule -`endif - // Attach a (combinatorial) black-box onto the output // of thes LUTRAM primitives to capture their // asynchronous read behaviour diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index 5604ceb0a..49a7bd88c 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -25,10 +25,6 @@ module $__ABC9_ASYNC01(input A, S, output Y); assign Y = A; endmodule -module $__ABC9_FF_(input D, output Q); - assign Q = D; -endmodule - module $__ABC9_RAM6(input A, input [5:0] S, output Y); assign Y = A; endmodule diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 63223afbf..93d080ffd 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -640,7 +640,7 @@ module FDRSE ( Q <= d; endmodule -(* abc9_flop, lib_whitebox *) +(* lib_whitebox *) module FDCE ( output reg Q, (* clkbuf_sink *) @@ -683,7 +683,7 @@ module FDCE ( endspecify endmodule -(* abc9_flop, lib_whitebox *) +(* lib_whitebox *) module FDCE_1 ( output reg Q, (* clkbuf_sink *) @@ -708,7 +708,7 @@ module FDCE_1 ( endspecify endmodule -(* abc9_flop, lib_whitebox *) +(* lib_whitebox *) module FDPE ( output reg Q, (* clkbuf_sink *) @@ -750,7 +750,7 @@ module FDPE ( endspecify endmodule -(* abc9_flop, lib_whitebox *) +(* lib_whitebox *) module FDPE_1 ( output reg Q, (* clkbuf_sink *) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 229ffcb3d..173bdcb91 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -613,10 +613,7 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); - std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1"; - if (dff_mode) - techmap_args += " -D DFF_MODE"; - run("techmap " + techmap_args); + run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v"); std::string abc9_opts; std::string k = "synth_xilinx.abc9.W"; -- cgit v1.2.3 From c10757a8ea5d6052d7a06690fb7411b5e4c7d772 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 13 Apr 2020 16:21:08 -0700 Subject: synth_xilinx: rename dff_mode -> dff --- techlibs/xilinx/synth_xilinx.cc | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 173bdcb91..c45d389ef 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -143,7 +143,7 @@ struct SynthXilinxPass : public ScriptPass std::string top_opt, edif_file, blif_file, family; bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; - bool abc9, dff_mode; + bool abc9, dff; bool flatten_before_abc; int widemux; int lut_size; @@ -170,7 +170,7 @@ struct SynthXilinxPass : public ScriptPass nodsp = false; uram = false; abc9 = false; - dff_mode = false; + dff = false; flatten_before_abc = false; widemux = 0; lut_size = 6; @@ -217,7 +217,7 @@ struct SynthXilinxPass : public ScriptPass continue; } if (args[argidx] == "-retime") { - dff_mode = true; + dff = true; retime = true; continue; } @@ -281,7 +281,7 @@ struct SynthXilinxPass : public ScriptPass continue; } if (args[argidx] == "-dff") { - dff_mode = true; + dff = true; continue; } break; @@ -595,9 +595,11 @@ struct SynthXilinxPass : public ScriptPass run("clean"); } - if (check_label("map_ffs")) { + if (check_label("map_ffs", "('-abc9' only)")) { if (abc9 || help_mode) { - run("techmap -map " + ff_map_file, "('-abc9' only)"); + if (dff || help_mode) + run("zinit -all", "('-dff' only)"); + run("techmap -map " + ff_map_file); } } @@ -625,7 +627,7 @@ struct SynthXilinxPass : public ScriptPass } if (nowidelut) abc9_opts += stringf(" -maxlut %d", lut_size); - if (dff_mode) + if (dff) abc9_opts += " -dff"; run("abc9" + abc9_opts); run("techmap -map +/xilinx/abc9_unmap.v"); @@ -645,7 +647,7 @@ struct SynthXilinxPass : public ScriptPass else abc_opts += " -luts 2:2,3,6:5,10,20,40"; } - if (dff_mode) + if (dff) abc_opts += " -dff"; if (retime) abc_opts += " -D 1"; -- cgit v1.2.3 From 4a10c87ae1916fb1d19b7bb0adebd54a5b15cf30 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 13 Apr 2020 17:31:44 -0700 Subject: ice40: split out cells_map.v into ff_map.v --- techlibs/ice40/Makefile.inc | 1 + techlibs/ice40/cells_map.v | 31 ------------------------------- techlibs/ice40/ff_map.v | 28 ++++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 31 deletions(-) create mode 100644 techlibs/ice40/ff_map.v (limited to 'techlibs') diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index b9e504a9d..1a8caf9a9 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -23,6 +23,7 @@ techlibs/ice40/brams_init3.vh: techlibs/ice40/brams_init.mk $(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/ff_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index d5362eb83..e9ccca239 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -1,33 +1,3 @@ -module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule -module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule - -module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule -module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule - -module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule - -module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule - -module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule - -module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule -module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule -module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule -module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule - -module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule -module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule -module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule - -`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -59,4 +29,3 @@ module \$lut (A, Y); end endgenerate endmodule -`endif diff --git a/techlibs/ice40/ff_map.v b/techlibs/ice40/ff_map.v new file mode 100644 index 000000000..e8807e0bd --- /dev/null +++ b/techlibs/ice40/ff_map.v @@ -0,0 +1,28 @@ +module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule +module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule +module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule + +module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule +module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule + +module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule + +module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule +module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule +module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule +module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule + +module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule +module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule -- cgit v1.2.3 From fe7965e0eeb7dacf1453ff6cfc1783c8c39c8201 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 13 Apr 2020 17:32:21 -0700 Subject: ice40: add synth_ice40 -dff option, support with -abc9 --- techlibs/ice40/cells_sim.v | 13 +++++++++++++ techlibs/ice40/synth_ice40.cc | 36 ++++++++++++++++++++++++++++-------- 2 files changed, 41 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 5d107989d..1b759a28f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -245,6 +245,7 @@ endmodule // Positive Edge SiliconBlue FF Cells +(* abc9_flop, lib_whitebox *) module SB_DFF ( output `SB_DFF_REG, input C, D @@ -280,6 +281,7 @@ module SB_DFF ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFE ( output `SB_DFF_REG, input C, E, D @@ -322,6 +324,7 @@ module SB_DFFE ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFSR ( output `SB_DFF_REG, input C, R, D @@ -419,6 +422,7 @@ module SB_DFFR ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFSS ( output `SB_DFF_REG, input C, S, D @@ -516,6 +520,7 @@ module SB_DFFS ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFESR ( output `SB_DFF_REG, input C, E, R, D @@ -627,6 +632,7 @@ module SB_DFFER ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFESS ( output `SB_DFF_REG, input C, E, S, D @@ -740,6 +746,7 @@ endmodule // Negative Edge SiliconBlue FF Cells +(* abc9_flop, lib_whitebox *) module SB_DFFN ( output `SB_DFF_REG, input C, D @@ -775,6 +782,7 @@ module SB_DFFN ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFNE ( output `SB_DFF_REG, input C, E, D @@ -817,6 +825,7 @@ module SB_DFFNE ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFNSR ( output `SB_DFF_REG, input C, R, D @@ -864,6 +873,7 @@ module SB_DFFNSR ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFNR ( output `SB_DFF_REG, input C, R, D @@ -914,6 +924,7 @@ module SB_DFFNR ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFNSS ( output `SB_DFF_REG, input C, S, D @@ -1011,6 +1022,7 @@ module SB_DFFNS ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFNESR ( output `SB_DFF_REG, input C, E, R, D @@ -1122,6 +1134,7 @@ module SB_DFFNER ( `endif endmodule +(* abc9_flop, lib_whitebox *) module SB_DFFNESS ( output `SB_DFF_REG, input C, E, S, D diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 6e05ab0b2..a8bf93db5 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -71,6 +71,9 @@ struct SynthIce40Pass : public ScriptPass log(" -noflatten\n"); log(" do not flatten design before synthesis\n"); log("\n"); + log(" -dff\n"); + log(" run 'abc'/'abc9' with -dff option\n"); + log("\n"); log(" -retime\n"); log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); @@ -113,7 +116,7 @@ struct SynthIce40Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file, device_opt; - bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, flowmap; + bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap; int min_ce_use; void clear_flags() YS_OVERRIDE @@ -221,6 +224,10 @@ struct SynthIce40Pass : public ScriptPass abc9 = true; continue; } + if (args[argidx] == "-dff") { + dff = true; + continue; + } if (args[argidx] == "-device" && argidx+1 < args.size()) { device_opt = args[++argidx]; continue; @@ -354,7 +361,9 @@ struct SynthIce40Pass : public ScriptPass run(stringf("dff2dffe -unmap-mince %d", min_ce_use)); run("simplemap t:$dff"); } - run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v"); + if ((abc9 && dff) || help_mode) + run("zinit -all", "(-abc9 and -dff only)"); + run("techmap -map +/ice40/ff_map.v"); run("opt_expr -mux_undef"); run("simplemap"); run("ice40_ffinit"); @@ -387,23 +396,34 @@ struct SynthIce40Pass : public ScriptPass k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str()); abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); } + if (dff) + abc9_opts += " -dff"; run("abc9 " + abc9_opts); } else - run("abc -dress -lut 4", "(skip if -noabc)"); + run(stringf("abc -dress -lut 4 %s", dff ? "-dff" : ""), "(skip if -noabc)"); } run("ice40_wrapcarry -unwrap"); - run("techmap -D NO_LUT -map +/ice40/cells_map.v"); + run("techmap -map +/ice40/ff_map.v"); run("clean"); run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); } if (check_label("map_cells")) { - if (vpr) - run("techmap -D NO_LUT -map +/ice40/cells_map.v"); - else - run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)"); + if (help_mode) + run("techmap [-map +/ice40/ff_map.v] [-map +/ice40/cells_map.v]", "(skip if -abc9; skip if -vpr)"); + else if (vpr) + run("techmap -map +/ice40/ff_map.v"); + else { + std::string techmap_args; + if (!abc9) + techmap_args += " -map +/ice40/ff_map.v"; + if (!vpr) + techmap_args += " -map +/ice40/cells_map.v"; + if (!techmap_args.empty()) + run("techmap " + techmap_args); + } run("clean"); } -- cgit v1.2.3 From 5d5029fa75b8cb37c07fc15a0429e28fe317b472 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Apr 2020 07:31:07 -0700 Subject: ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init --- techlibs/ecp5/Makefile.inc | 3 +- techlibs/ecp5/cells_map.v | 278 ++++++++++++++++++++++++++++++++++---------- techlibs/ecp5/synth_ecp5.cc | 3 +- 3 files changed, 220 insertions(+), 64 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 217151e96..6bc9c854e 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -1,6 +1,5 @@ -OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \ - techlibs/ecp5/ecp5_gsr.o +OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o GENFILES += techlibs/ecp5/bram_init_1_2_4.vh GENFILES += techlibs/ecp5/bram_init_9_18_36.vh diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index c031703a9..f8df08eab 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -1,65 +1,223 @@ -module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule - -module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule - -module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule - -module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *) +module \$_DFF_x_ (input D, C, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + localparam REGSET = "SET"; + else + localparam REGSET = "RESET"; + endgenerate + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET)) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); +endmodule + +(* techmap_celltype = "$_DFFE_NN_ $_DFFE_PN_ $_DFFE_NP_ $_DFFE_PP_" *) +module \$_DFFE_xx_ (input D, C, E, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") + localparam CEMUX = "INV"; + else + localparam CEMUX = "CE"; + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + localparam REGSET = "SET"; + else + localparam REGSET = "RESET"; + endgenerate + TRELLIS_FF #(.GSR("AUTO"), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET)) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); +endmodule + +(* techmap_celltype = "$_DFF_NN0_ $_DFF_NN1_ $_DFF_PN0_ $_DFF_PN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PP0_ $_DFF_PP1_" *) +module \$_DFF_xxx_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + // TODO: Why not use LSRMUX param? + if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") + wire LSR_ = !R; + else + wire LSR_ = R; + if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin + localparam REGSET = "SET"; + if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("ECP5 doesn't support FFs with asynchronous set initialized to 0"); + end + else begin + localparam REGSET = "RESET"; + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("ECP5 doesn't support FFs with asynchronous reset initialized to 1"); + end + endgenerate + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(LSR_), .DI(D), .Q(Q)); +endmodule + +(* techmap_celltype = "$__DFFS_NN0_ $__DFFS_NN1_ $__DFFS_PN0_ $__DFFS_PN1_ $__DFFS_NP0_ $__DFFS_NP1_ $__DFFS_PP0_ $__DFFS_PP1_" *) +module \$__DFFS_xxx_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + // TODO: Why not use LSRMUX param? + if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") + wire LSR_ = !R; + else + wire LSR_ = R; + if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin + localparam REGSET = "SET"; + if (_TECHMAP_WIREINIT_Q_ === 1'b0) + // init is 0, reset to 1 + wire D_ = D || LSR_; + else + wire D_ = D; + end + else begin + localparam REGSET = "RESET"; + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + // init is 1, reset to 0 + wire D_ = !(D && LSR_); + else + wire D_ = D; + end + endgenerate + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(LSR_), .DI(D_), .Q(Q)); +endmodule + +(* techmap_celltype = "$__DFFE_NN0 $__DFFE_NN1 $__DFFE_PN0 $__DFFE_PN1 $__DFFE_NP0 $__DFFE_NP1 $__DFFE_PP0 $__DFFE_PP1" *) +module \$__DFFE_xxx_ (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + // TODO: Why not use LSRMUX param? + if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") + wire LSR_ = !R; + else + wire LSR_ = R; + if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin + if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("ECP5 doesn't support FFs with asynchronous set initialized to 0"); + else + localparam REGSET = "SET"; + end + else begin + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("ECP5 doesn't support FFs with asynchronous reset initialized to 1"); + else + localparam REGSET = "RESET"; + end + endgenerate + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(LSR_), .DI(D), .Q(Q)); +endmodule + +(* techmap_celltype = "$__DFFSE_NN0 $__DFFSE_NN1 $__DFFSE_PN0 $__DFFSE_PN1 $__DFFSE_NP0 $__DFFSE_NP1 $__DFFSE_PP0 $__DFFSE_PP1" *) +module \$__DFFSE_xxx_ (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + // TODO: Why not use LSRMUX param? + if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") + wire LSR_ = !R; + else + wire LSR_ = R; + if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin + localparam REGSET = "SET"; + if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin + // init is 0, reset to 1 + wire D_ = D || LSR_; + wire E_ = E || LSR_; + end + else begin + wire D_ = D; + wire E_ = E; + end + end + else begin + localparam REGSET = "RESET"; + if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin + // init is 1, reset to 0 + wire D_ = !(D && LSR_); + wire E_ = !(E && LSR_); + end + else begin + wire D_ = D; + wire E_ = E; + end + end + endgenerate + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E_), .LSR(LSR_), .DI(D_), .Q(Q)); +endmodule `ifdef ASYNC_PRLD -module \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule -module \$_DLATCH_P_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(E), .DI(1'b0), .M(D), .Q(Q)); endmodule - -module \$_DFFSR_NNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule -module \$_DFFSR_NNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule -module \$_DFFSR_NPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule -module \$_DFFSR_NPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule - -module \$_DFFSR_PNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule -module \$_DFFSR_PNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule -module \$_DFFSR_PPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule -module \$_DFFSR_PPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule +(* techmap_celltype = "$_DLATCH_N_ $_DLATCH_P_" *) +module \$_DLATCH_x_ (input E, input D, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + // TODO: Why not use LSRMUX param? + if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") + wire LSR_ = !E; + else + wire LSR_ = E; + if (_TECHMAP_WIREINIT_Q_ !== 1'bx) + $error("ECP5 doesn't support latches with initial values"); // TODO: Check + endgenerate + TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(LSR_), .DI(1'b0), .M(D), .Q(Q)); +endmodule + +(* techmap_celltype = "$_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_PNN_ $_DFFSR_PNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PPN_ $_DFFSR_PPP_" *) +module \$_DFFSR_xxx_ (input C, S, R, D, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + generate + if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") + localparam CLKMUX = "INV"; + else + localparam CLKMUX = "CLK"; + if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") + wire S_ = !S; + else + wire S_ = S; + if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") + wire R_ = !R; + else + wire R_ = R; + if (_TECHMAP_WIREINIT_Q_ !== 1'bx) + $error("ECP5 doesn't support FFs with asynchronous set and reset with initial values"); + endgenerate + + TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX(CLKINV), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S_ || R_), .DI(D), .M(!R_), .Q(Q)); +endmodule `endif `include "cells_ff.vh" diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index b9b236a0c..5f00d3d4e 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -303,14 +303,13 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("map_ffs")) { - run("dff2dffs"); + run("dff2dffs -match-init"); run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); - run("ecp5_ffinit"); run("ecp5_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); -- cgit v1.2.3 From 23c53a6bdde645ef475752e24e7751beb20a3121 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Apr 2020 07:48:37 -0700 Subject: ice40: synth_ice40 cleanup --- techlibs/ice40/synth_ice40.cc | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index a8bf93db5..376cb7dbd 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -412,19 +412,9 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_cells")) { if (help_mode) - run("techmap [-map +/ice40/ff_map.v] [-map +/ice40/cells_map.v]", "(skip if -abc9; skip if -vpr)"); - else if (vpr) - run("techmap -map +/ice40/ff_map.v"); - else { - std::string techmap_args; - if (!abc9) - techmap_args += " -map +/ice40/ff_map.v"; - if (!vpr) - techmap_args += " -map +/ice40/cells_map.v"; - if (!techmap_args.empty()) - run("techmap " + techmap_args); - } - + run("techmap -map +/ice40/cells_map.v", "(skip if -vpr)"); + else if (!vpr) + run("techmap -map +/ice40/cells_map.v"); run("clean"); } -- cgit v1.2.3 From 34c77326420e4f906544e26499683869c47d09aa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Apr 2020 07:51:23 -0700 Subject: ecp5: add synth_ecp5 -dff to work with -abc9 --- techlibs/ecp5/cells_sim.v | 21 +++++++++++++++++++++ techlibs/ecp5/synth_ecp5.cc | 38 ++++++++++++++++++++++++++------------ 2 files changed, 47 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 12b33e925..69685683f 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -294,6 +294,7 @@ endmodule // --------------------------------------- +(* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *) module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter GSR = "ENABLED"; parameter [127:0] CEMUX = "1"; @@ -340,6 +341,26 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); Q <= DI; end endgenerate + + generate + // TODO + if (CLKMUX == "INV") + specify + $setup(DI, negedge CLK, 0); + $setup(CE, negedge CLK, 0); + $setup(LSR, negedge CLK, 0); + if (muxlsr) (negedge CLK => (Q : DI)) = 0; + if (!muxlsr && muxce) (negedge CLK => (Q : srval)) = 0; + endspecify + else + specify + $setup(DI, posedge CLK, 0); + $setup(CE, posedge CLK, 0); + $setup(LSR, posedge CLK, 0); + if (muxlsr) (posedge CLK => (Q : srval)) = 0; + if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0; + endspecify + endgenerate endmodule // --------------------------------------- diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 5f00d3d4e..ecc5039e6 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -66,6 +66,9 @@ struct SynthEcp5Pass : public ScriptPass log(" -noflatten\n"); log(" do not flatten design before synthesis\n"); log("\n"); + log(" -dff\n"); + log(" run 'abc'/'abc9' with -dff option\n"); + log("\n"); log(" -retime\n"); log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); @@ -107,7 +110,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr; void clear_flags() YS_OVERRIDE { @@ -122,6 +125,7 @@ struct SynthEcp5Pass : public ScriptPass nowidelut = false; asyncprld = false; flatten = true; + dff = false; retime = false; abc2 = false; vpr = false; @@ -169,6 +173,10 @@ struct SynthEcp5Pass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-dff") { + dff = true; + continue; + } if (args[argidx] == "-retime") { retime = true; continue; @@ -307,6 +315,8 @@ struct SynthEcp5Pass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); + if ((abc9 && dff) || help_mode) + run("zinit -all", "(-abc9 and -dff only)"); run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); @@ -323,7 +333,7 @@ struct SynthEcp5Pass : public ScriptPass std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v"; if (abc9) techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1"; - if (!asyncprld || abc9) + if (!techmap_args.empty()) run("techmap " + techmap_args); if (abc9) { @@ -337,26 +347,30 @@ struct SynthEcp5Pass : public ScriptPass else abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); if (nowidelut) - run("abc9 -maxlut 4 -W 200"); - else - run("abc9 -W 200"); + abc9_args += " -maxlut 4"; + if (dff) + abc9_args += " -dff"; + run("abc9" + abc9_args); run("techmap -map +/ecp5/abc9_unmap.v"); } else { + std::string abc_args = " -dress"; if (nowidelut) - run("abc -lut 4 -dress"); + abc_args += " -lut 4"; else - run("abc -lut 4:7 -dress"); + abc_args += " -lut 4:7"; + if (dff) + abc_args += " -dff"; + run("abc" + abc_args); } run("clean"); } if (check_label("map_cells")) { - if (vpr) - run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); - else - run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)"); - + if (help_mode) + run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)"); + else if (!vpr) + run("techmap -map +/ecp5/cells_map.v"); run("opt_lut_ins -tech ecp5"); run("clean"); } -- cgit v1.2.3 From a52f779ecae79be5ea79bd27f04837e7031f8415 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Apr 2020 10:36:07 -0700 Subject: ecp5: (* abc9_flop *) gated behind YOSYS --- techlibs/ecp5/cells_sim.v | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 69685683f..563592218 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -294,7 +294,9 @@ endmodule // --------------------------------------- +`ifdef YOSYS (* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *) +`endif module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter GSR = "ENABLED"; parameter [127:0] CEMUX = "1"; -- cgit v1.2.3 From 0d84ff3fc47fbc17184e706ea3ef1ee801f19790 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Apr 2020 12:56:28 -0700 Subject: Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b. --- techlibs/ecp5/Makefile.inc | 3 +- techlibs/ecp5/cells_map.v | 278 ++++++++++---------------------------------- techlibs/ecp5/synth_ecp5.cc | 3 +- 3 files changed, 64 insertions(+), 220 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 6bc9c854e..217151e96 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -1,5 +1,6 @@ -OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o +OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \ + techlibs/ecp5/ecp5_gsr.o GENFILES += techlibs/ecp5/bram_init_1_2_4.vh GENFILES += techlibs/ecp5/bram_init_9_18_36.vh diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index f8df08eab..c031703a9 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -1,223 +1,65 @@ -(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *) -module \$_DFF_x_ (input D, C, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - if (_TECHMAP_WIREINIT_Q_ === 1'b1) - localparam REGSET = "SET"; - else - localparam REGSET = "RESET"; - endgenerate - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET)) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); -endmodule - -(* techmap_celltype = "$_DFFE_NN_ $_DFFE_PN_ $_DFFE_NP_ $_DFFE_PP_" *) -module \$_DFFE_xx_ (input D, C, E, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") - localparam CEMUX = "INV"; - else - localparam CEMUX = "CE"; - if (_TECHMAP_WIREINIT_Q_ === 1'b1) - localparam REGSET = "SET"; - else - localparam REGSET = "RESET"; - endgenerate - TRELLIS_FF #(.GSR("AUTO"), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET)) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); -endmodule - -(* techmap_celltype = "$_DFF_NN0_ $_DFF_NN1_ $_DFF_PN0_ $_DFF_PN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PP0_ $_DFF_PP1_" *) -module \$_DFF_xxx_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - // TODO: Why not use LSRMUX param? - if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") - wire LSR_ = !R; - else - wire LSR_ = R; - if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin - localparam REGSET = "SET"; - if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("ECP5 doesn't support FFs with asynchronous set initialized to 0"); - end - else begin - localparam REGSET = "RESET"; - if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("ECP5 doesn't support FFs with asynchronous reset initialized to 1"); - end - endgenerate - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(LSR_), .DI(D), .Q(Q)); -endmodule - -(* techmap_celltype = "$__DFFS_NN0_ $__DFFS_NN1_ $__DFFS_PN0_ $__DFFS_PN1_ $__DFFS_NP0_ $__DFFS_NP1_ $__DFFS_PP0_ $__DFFS_PP1_" *) -module \$__DFFS_xxx_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - // TODO: Why not use LSRMUX param? - if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") - wire LSR_ = !R; - else - wire LSR_ = R; - if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin - localparam REGSET = "SET"; - if (_TECHMAP_WIREINIT_Q_ === 1'b0) - // init is 0, reset to 1 - wire D_ = D || LSR_; - else - wire D_ = D; - end - else begin - localparam REGSET = "RESET"; - if (_TECHMAP_WIREINIT_Q_ === 1'b1) - // init is 1, reset to 0 - wire D_ = !(D && LSR_); - else - wire D_ = D; - end - endgenerate - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(LSR_), .DI(D_), .Q(Q)); -endmodule - -(* techmap_celltype = "$__DFFE_NN0 $__DFFE_NN1 $__DFFE_PN0 $__DFFE_PN1 $__DFFE_NP0 $__DFFE_NP1 $__DFFE_PP0 $__DFFE_PP1" *) -module \$__DFFE_xxx_ (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - // TODO: Why not use LSRMUX param? - if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") - wire LSR_ = !R; - else - wire LSR_ = R; - if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin - if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("ECP5 doesn't support FFs with asynchronous set initialized to 0"); - else - localparam REGSET = "SET"; - end - else begin - if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("ECP5 doesn't support FFs with asynchronous reset initialized to 1"); - else - localparam REGSET = "RESET"; - end - endgenerate - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(LSR_), .DI(D), .Q(Q)); -endmodule - -(* techmap_celltype = "$__DFFSE_NN0 $__DFFSE_NN1 $__DFFSE_PN0 $__DFFSE_PN1 $__DFFSE_NP0 $__DFFSE_NP1 $__DFFSE_PP0 $__DFFSE_PP1" *) -module \$__DFFSE_xxx_ (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - // TODO: Why not use LSRMUX param? - if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") - wire LSR_ = !R; - else - wire LSR_ = R; - if (_TECHMAP_CELLTYPE_[1*8+:8] == "1") begin - localparam REGSET = "SET"; - if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin - // init is 0, reset to 1 - wire D_ = D || LSR_; - wire E_ = E || LSR_; - end - else begin - wire D_ = D; - wire E_ = E; - end - end - else begin - localparam REGSET = "RESET"; - if (_TECHMAP_WIREINIT_Q_ === 1'b1) begin - // init is 1, reset to 0 - wire D_ = !(D && LSR_); - wire E_ = !(E && LSR_); - end - else begin - wire D_ = D; - wire E_ = E; - end - end - endgenerate - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX(CLKMUX), .LSRMUX("LSR"), .REGSET(REGSET), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E_), .LSR(LSR_), .DI(D_), .Q(Q)); -endmodule +module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule `ifdef ASYNC_PRLD -(* techmap_celltype = "$_DLATCH_N_ $_DLATCH_P_" *) -module \$_DLATCH_x_ (input E, input D, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - // TODO: Why not use LSRMUX param? - if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") - wire LSR_ = !E; - else - wire LSR_ = E; - if (_TECHMAP_WIREINIT_Q_ !== 1'bx) - $error("ECP5 doesn't support latches with initial values"); // TODO: Check - endgenerate - TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(LSR_), .DI(1'b0), .M(D), .Q(Q)); -endmodule - -(* techmap_celltype = "$_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_PNN_ $_DFFSR_PNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PPN_ $_DFFSR_PPP_" *) -module \$_DFFSR_xxx_ (input C, S, R, D, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - parameter _TECHMAP_CELLTYPE_ = ""; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - generate - if (_TECHMAP_CELLTYPE_[3*8+:8] == "N") - localparam CLKMUX = "INV"; - else - localparam CLKMUX = "CLK"; - if (_TECHMAP_CELLTYPE_[2*8+:8] == "N") - wire S_ = !S; - else - wire S_ = S; - if (_TECHMAP_CELLTYPE_[1*8+:8] == "N") - wire R_ = !R; - else - wire R_ = R; - if (_TECHMAP_WIREINIT_Q_ !== 1'bx) - $error("ECP5 doesn't support FFs with asynchronous set and reset with initial values"); - endgenerate - - TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX(CLKINV), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S_ || R_), .DI(D), .M(!R_), .Q(Q)); -endmodule +module \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule +module \$_DLATCH_P_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(E), .DI(1'b0), .M(D), .Q(Q)); endmodule + +module \$_DFFSR_NNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_NNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule +module \$_DFFSR_NPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_NPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule + +module \$_DFFSR_PNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_PNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule +module \$_DFFSR_PPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_PPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule `endif `include "cells_ff.vh" diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index ecc5039e6..8039531ae 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -311,7 +311,7 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("map_ffs")) { - run("dff2dffs -match-init"); + run("dff2dffs"); run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); @@ -320,6 +320,7 @@ struct SynthEcp5Pass : public ScriptPass run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); + run("ecp5_ffinit"); run("ecp5_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); -- cgit v1.2.3 From 6c66030dfbcd93024f5f5bb602b9fcc58cb80a88 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 18 Feb 2020 17:59:33 -0800 Subject: Uncomment negative setup times; clamp to zero for connectivity --- techlibs/xilinx/cells_sim.v | 42 +++++++++++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 13 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 93d080ffd..5143f87da 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -36,6 +36,9 @@ module IBUF( parameter IOSTANDARD = "default"; parameter IBUF_LOW_PWR = 0; assign O = I; + specify + (I => O) = 0; + endspecify endmodule module IBUFG( @@ -57,6 +60,9 @@ module OBUF( parameter DRIVE = 12; parameter SLEW = "SLOW"; assign O = I; + specify + (I => O) = 0; + endspecify endmodule module IOBUF ( @@ -72,6 +78,10 @@ module IOBUF ( parameter SLEW = "SLOW"; assign IO = T ? 1'bz : I; assign O = IO; + specify + (I => IO) = 0; + (IO => O) = 0; + endspecify endmodule module OBUFT ( @@ -85,14 +95,20 @@ module OBUFT ( parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; assign O = T ? 1'bz : I; + specify + (I => O) = 0; + endspecify endmodule module BUFG( (* clkbuf_driver *) output O, input I); - assign O = I; + specify + // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/CLK_BUFG_TOP_R.sdf#L11 + (I => O) = 96; + endspecify endmodule module BUFGCTRL( @@ -499,8 +515,8 @@ module FDRE ( endgenerate specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , posedge C &&& CE && !IS_C_INVERTED , -46); // Negative times not currently supported - //$setup(D , negedge C &&& CE && IS_C_INVERTED , -46); // Negative times not currently supported + $setup(D , posedge C &&& CE && !IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& CE && IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE, posedge C &&& !IS_C_INVERTED, 109); $setup(CE, negedge C &&& IS_C_INVERTED, 109); @@ -529,7 +545,7 @@ module FDRE_1 ( always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE, negedge C, 109); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 @@ -564,8 +580,8 @@ module FDSE ( endgenerate specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported - //$setup(D , negedge C &&& IS_C_INVERTED && CE, -46); // Negative times not currently supported + $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE, posedge C &&& !IS_C_INVERTED, 109); $setup(CE, negedge C &&& IS_C_INVERTED, 109); @@ -594,7 +610,7 @@ module FDSE_1 ( always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE, negedge C, 109); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 @@ -667,8 +683,8 @@ module FDCE ( endgenerate specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported - //$setup(D , negedge C &&& IS_C_INVERTED && CE, -46); // Negative times not currently supported + $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , posedge C &&& !IS_C_INVERTED, 109); $setup(CE , negedge C &&& IS_C_INVERTED, 109); @@ -697,7 +713,7 @@ module FDCE_1 ( always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , negedge C, 109); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 @@ -734,8 +750,8 @@ module FDPE ( endgenerate specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported - //$setup(D , negedge C &&& IS_C_INVERTED && CE, -46); // Negative times not currently supported + $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported + $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , posedge C &&& !IS_C_INVERTED, 109); $setup(CE , negedge C &&& IS_C_INVERTED, 109); @@ -764,7 +780,7 @@ module FDPE_1 ( always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported + $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , negedge C, 109); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 -- cgit v1.2.3 From 4cec21b93e62e9c43a0ab9618c0111ee65e520c1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 15 Apr 2020 16:29:11 -0700 Subject: abc9_ops: -prep_dff_map to error if async flop found --- techlibs/xilinx/cells_sim.v | 4 ---- 1 file changed, 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5143f87da..25df3a865 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -656,7 +656,6 @@ module FDRSE ( Q <= d; endmodule -(* lib_whitebox *) module FDCE ( output reg Q, (* clkbuf_sink *) @@ -699,7 +698,6 @@ module FDCE ( endspecify endmodule -(* lib_whitebox *) module FDCE_1 ( output reg Q, (* clkbuf_sink *) @@ -724,7 +722,6 @@ module FDCE_1 ( endspecify endmodule -(* lib_whitebox *) module FDPE ( output reg Q, (* clkbuf_sink *) @@ -766,7 +763,6 @@ module FDPE ( endspecify endmodule -(* lib_whitebox *) module FDPE_1 ( output reg Q, (* clkbuf_sink *) -- cgit v1.2.3 From 48052ad813db3561a959a1921466d571bafa354c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 10:24:02 -0700 Subject: abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too --- techlibs/common/Makefile.inc | 2 ++ techlibs/common/abc9_map.v | 21 +++++++++++++++++++++ techlibs/common/abc9_model.v | 20 ++++++++++++++++++++ techlibs/common/abc9_unmap.v | 12 ++++++++++++ 4 files changed, 55 insertions(+) create mode 100644 techlibs/common/abc9_map.v create mode 100644 techlibs/common/abc9_unmap.v (limited to 'techlibs') diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 7b1e4b430..607e772a2 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -30,4 +30,6 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) +$(eval $(call add_share_file,share,techlibs/common/abc9_map.v)) +$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v)) diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v new file mode 100644 index 000000000..b04a5b64f --- /dev/null +++ b/techlibs/common/abc9_map.v @@ -0,0 +1,21 @@ +(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *) +module $_DFF_x_(input C, D, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + wire _TECHMAP_FAIL_ = 1; + else if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin + wire D_; + $__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); + $_DFF_N_ ff (.C(C), .D(D_), .Q(Q)); + end + else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin + wire D_; + $__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); + $_DFF_P_ ff (.C(C), .D(D_), .Q(Q)); + end + else if (_TECHMAP_CELLTYPE_ != "") + $error("Unrecognised _TECHMAP_CELLTYPE_"); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v index 9e8048faf..41acf4d97 100644 --- a/techlibs/common/abc9_model.v +++ b/techlibs/common/abc9_model.v @@ -5,3 +5,23 @@ module \$__ABC9_DELAY (input I, output O); (I => O) = DELAY; endspecify endmodule + +(* abc9_flop, abc9_box, lib_whitebox *) +module $__DFF_N__$abc9_flop(input C, D, Q, (* init=INIT *) output n1); + parameter [0:0] INIT = 1'bx; + assign n1 = D; + specify + $setup(D, posedge C, 0); + (posedge C => (n1:D)) = 0; + endspecify +endmodule + +(* abc9_flop, abc9_box, lib_whitebox *) +module $__DFF_P__$abc9_flop(input C, D, Q, (* init=INIT *) output n1); + parameter [0:0] INIT = 1'bx; + assign n1 = D; + specify + $setup(D, posedge C, 0); + (posedge C => (n1:D)) = 0; + endspecify +endmodule diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v new file mode 100644 index 000000000..0fd07207d --- /dev/null +++ b/techlibs/common/abc9_unmap.v @@ -0,0 +1,12 @@ +(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *) +module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1); + parameter [0:0] INIT = 1'bx; + parameter _TECHMAP_CELLTYPE_ = ""; + generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop") + $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); + else if (_TECHMAP_CELLTYPE_ == "$__DFF_P__$abc9_flop") + $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); + else if (_TECHMAP_CELLTYPE_ != "") + $error("Unrecognised _TECHMAP_CELLTYPE_"); + endgenerate +endmodule -- cgit v1.2.3 From 8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 10:25:41 -0700 Subject: synth_*: no need to explicitly read +/abc9_model.v --- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel_alm/synth_intel_alm.cc | 1 - techlibs/xilinx/synth_xilinx.cc | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 8039531ae..c1545cbb5 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -338,7 +338,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { - run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v"); + run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); std::string abc9_opts; if (nowidelut) abc9_opts += " -maxlut 4"; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 376cb7dbd..f780832e6 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -387,7 +387,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc9) { - run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v"); + run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v"); std::string abc9_opts; std::string k = "synth_ice40.abc9.W"; if (active_design && active_design->scratchpad.count(k)) diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index bf9e746b8..0f844961e 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_luts")) { - run("read_verilog -icells -specify -lib +/abc9_model.v"); run("abc9 -maxlut 6 -W 200"); run("techmap -map +/intel_alm/common/alm_map.v"); run("opt -fast"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c45d389ef..d6ca9e57e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -616,7 +616,7 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); - run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v"); + run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v"); std::string abc9_opts; std::string k = "synth_xilinx.abc9.W"; if (active_design && active_design->scratchpad.count(k)) -- cgit v1.2.3 From 722540dbf942d2b8acbaf7372001c7d982eb2845 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 12:08:59 -0700 Subject: abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ --- techlibs/common/abc9_map.v | 24 ++++++++++++++---------- techlibs/common/abc9_unmap.v | 12 ++++++++++++ 2 files changed, 26 insertions(+), 10 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v index b04a5b64f..5f1822485 100644 --- a/techlibs/common/abc9_map.v +++ b/techlibs/common/abc9_map.v @@ -2,20 +2,24 @@ module $_DFF_x_(input C, D, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; parameter _TECHMAP_CELLTYPE_ = ""; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - wire _TECHMAP_FAIL_ = 1; - else if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin - wire D_; - $__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); - $_DFF_N_ ff (.C(C), .D(D_), .Q(Q)); + wire D_; + generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin + if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin + $__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); + $_DFF_N_ ff (.C(C), .D(D_), .Q(Q)); + end + else + $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));// hide from abc9 using $__ prefix end else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin - wire D_; - $__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); - $_DFF_P_ ff (.C(C), .D(D_), .Q(Q)); + if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin + $__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); + $_DFF_P_ ff (.C(C), .D(D_), .Q(Q)); + end + else + $__DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix end else if (_TECHMAP_CELLTYPE_ != "") $error("Unrecognised _TECHMAP_CELLTYPE_"); endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v index 0fd07207d..4dfac0cbb 100644 --- a/techlibs/common/abc9_unmap.v +++ b/techlibs/common/abc9_unmap.v @@ -10,3 +10,15 @@ module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1); $error("Unrecognised _TECHMAP_CELLTYPE_"); endgenerate endmodule + +(* techmap_celltype = "$__DFF_N_ $__DFF_P_" *) +module $__DFF_N__$abc9_flop(input C, D, output Q); + parameter _TECHMAP_CELLTYPE_ = ""; + generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_") + $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); + else if (_TECHMAP_CELLTYPE_ == "$__DFF_P_") + $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); + else if (_TECHMAP_CELLTYPE_ != "") + $error("Unrecognised _TECHMAP_CELLTYPE_"); + endgenerate +endmodule -- cgit v1.2.3 From 7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 12:22:39 -0700 Subject: abc9_ops: add -prep_bypass for auto bypass boxes; refactor Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier --- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/xilinx/Makefile.inc | 2 - techlibs/xilinx/abc9_map.v | 432 ---------------------------------------- techlibs/xilinx/abc9_model.v | 171 ---------------- techlibs/xilinx/abc9_unmap.v | 57 ------ techlibs/xilinx/cells_sim.v | 222 ++++++++++++--------- techlibs/xilinx/synth_xilinx.cc | 4 +- 8 files changed, 129 insertions(+), 763 deletions(-) delete mode 100644 techlibs/xilinx/abc9_map.v delete mode 100644 techlibs/xilinx/abc9_unmap.v (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index c1545cbb5..3e475baab 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -316,7 +316,7 @@ struct SynthEcp5Pass : public ScriptPass if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); if ((abc9 && dff) || help_mode) - run("zinit -all", "(-abc9 and -dff only)"); + run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff"); run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index f780832e6..f2270dbca 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -362,7 +362,7 @@ struct SynthIce40Pass : public ScriptPass run("simplemap t:$dff"); } if ((abc9 && dff) || help_mode) - run("zinit -all", "(-abc9 and -dff only)"); + run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff"); run("techmap -map +/ice40/ff_map.v"); run("opt_expr -mux_undef"); run("simplemap"); diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9984290a6..d4d863831 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -54,8 +54,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v deleted file mode 100644 index 1d733a650..000000000 --- a/techlibs/xilinx/abc9_map.v +++ /dev/null @@ -1,432 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * 2019 Eddie Hung - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// The following techmapping rules are intended to be run (with -max_iter 1) -// before invoking the `abc9` pass in order to transform the design into -// a format that it understands. - -// Attach a (combinatorial) black-box onto the output -// of thes LUTRAM primitives to capture their -// asynchronous read behaviour -module RAM32X1D ( - output DPO, SPO, - (* techmap_autopurge *) input D, - (* techmap_autopurge *) input WCLK, - (* techmap_autopurge *) input WE, - (* techmap_autopurge *) input A0, A1, A2, A3, A4, - (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 -); - parameter INIT = 32'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire $DPO, $SPO; - RAM32X1D #( - .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .DPO($DPO), .SPO($SPO), - .D(D), .WCLK(WCLK), .WE(WE), - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), - .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4) - ); - $__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO)); - $__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); -endmodule - -module RAM64X1D ( - output DPO, SPO, - (* techmap_autopurge *) input D, - (* techmap_autopurge *) input WCLK, - (* techmap_autopurge *) input WE, - (* techmap_autopurge *) input A0, A1, A2, A3, A4, A5, - (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 -); - parameter INIT = 64'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire $DPO, $SPO; - RAM64X1D #( - .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .DPO($DPO), .SPO($SPO), - .D(D), .WCLK(WCLK), .WE(WE), - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), - .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5) - ); - $__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO)); - $__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); -endmodule - -module RAM128X1D ( - output DPO, SPO, - (* techmap_autopurge *) input D, - (* techmap_autopurge *) input WCLK, - (* techmap_autopurge *) input WE, - (* techmap_autopurge *) input [6:0] A, DPRA -); - parameter INIT = 128'h0; - parameter IS_WCLK_INVERTED = 1'b0; - wire $DPO, $SPO; - RAM128X1D #( - .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .DPO($DPO), .SPO($SPO), - .D(D), .WCLK(WCLK), .WE(WE), - .A(A), - .DPRA(DPRA) - ); - $__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO)); - $__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO)); -endmodule - -module RAM32M ( - output [1:0] DOA, - output [1:0] DOB, - output [1:0] DOC, - output [1:0] DOD, - (* techmap_autopurge *) input [4:0] ADDRA, - (* techmap_autopurge *) input [4:0] ADDRB, - (* techmap_autopurge *) input [4:0] ADDRC, - (* techmap_autopurge *) input [4:0] ADDRD, - (* techmap_autopurge *) input [1:0] DIA, - (* techmap_autopurge *) input [1:0] DIB, - (* techmap_autopurge *) input [1:0] DIC, - (* techmap_autopurge *) input [1:0] DID, - (* techmap_autopurge *) input WCLK, - (* techmap_autopurge *) input WE -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [1:0] $DOA, $DOB, $DOC, $DOD; - RAM32M #( - .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), - .IS_WCLK_INVERTED(IS_WCLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD), - .WCLK(WCLK), .WE(WE), - .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), - .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) - ); - $__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0])); - $__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1])); - $__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0])); - $__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1])); - $__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0])); - $__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1])); - $__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0])); - $__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1])); -endmodule - -module RAM64M ( - output DOA, - output DOB, - output DOC, - output DOD, - (* techmap_autopurge *) input [5:0] ADDRA, - (* techmap_autopurge *) input [5:0] ADDRB, - (* techmap_autopurge *) input [5:0] ADDRC, - (* techmap_autopurge *) input [5:0] ADDRD, - (* techmap_autopurge *) input DIA, - (* techmap_autopurge *) input DIB, - (* techmap_autopurge *) input DIC, - (* techmap_autopurge *) input DID, - (* techmap_autopurge *) input WCLK, - (* techmap_autopurge *) input WE -); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire $DOA, $DOB, $DOC, $DOD; - RAM64M #( - .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), - .IS_WCLK_INVERTED(IS_WCLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD), - .WCLK(WCLK), .WE(WE), - .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), - .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) - ); - $__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA)); - $__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB)); - $__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC)); - $__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD)); -endmodule - -module SRL16 ( - output Q, - (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D -); - parameter [15:0] INIT = 16'h0000; - wire $Q; - SRL16 #( - .INIT(INIT), - ) _TECHMAP_REPLACE_ ( - .Q($Q), - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D) - ); - $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); -endmodule - -module SRL16E ( - output Q, - (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - wire $Q; - SRL16E #( - .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .Q($Q), - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) - ); - $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); -endmodule - -module SRLC16 ( - output Q, Q15, - (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D -); - parameter [15:0] INIT = 16'h0000; - wire $Q; - SRLC16 #( - .INIT(INIT), - ) _TECHMAP_REPLACE_ ( - .Q($Q), .Q(Q15), - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D) - ); - $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); -endmodule - -module SRLC16E ( - output Q, Q15, - (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - wire $Q; - SRLC16E #( - .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .Q($Q), .Q(Q15), - .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) - ); - $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); -endmodule - -module SRLC32E ( - output Q, - output Q31, - (* techmap_autopurge *) input [4:0] A, - (* techmap_autopurge *) input CE, CLK, D -); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - wire $Q; - SRLC32E #( - .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED) - ) _TECHMAP_REPLACE_ ( - .Q($Q), .Q31(Q31), - .A(A), .CE(CE), .CLK(CLK), .D(D) - ); - $__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q)); -endmodule - -module DSP48E1 ( - (* techmap_autopurge *) output [29:0] ACOUT, - (* techmap_autopurge *) output [17:0] BCOUT, - (* techmap_autopurge *) output reg CARRYCASCOUT, - (* techmap_autopurge *) output reg [3:0] CARRYOUT, - (* techmap_autopurge *) output reg MULTSIGNOUT, - (* techmap_autopurge *) output OVERFLOW, - (* techmap_autopurge *) output reg signed [47:0] P, - (* techmap_autopurge *) output PATTERNBDETECT, - (* techmap_autopurge *) output PATTERNDETECT, - (* techmap_autopurge *) output [47:0] PCOUT, - (* techmap_autopurge *) output UNDERFLOW, - (* techmap_autopurge *) input signed [29:0] A, - (* techmap_autopurge *) input [29:0] ACIN, - (* techmap_autopurge *) input [3:0] ALUMODE, - (* techmap_autopurge *) input signed [17:0] B, - (* techmap_autopurge *) input [17:0] BCIN, - (* techmap_autopurge *) input [47:0] C, - (* techmap_autopurge *) input CARRYCASCIN, - (* techmap_autopurge *) input CARRYIN, - (* techmap_autopurge *) input [2:0] CARRYINSEL, - (* techmap_autopurge *) input CEA1, - (* techmap_autopurge *) input CEA2, - (* techmap_autopurge *) input CEAD, - (* techmap_autopurge *) input CEALUMODE, - (* techmap_autopurge *) input CEB1, - (* techmap_autopurge *) input CEB2, - (* techmap_autopurge *) input CEC, - (* techmap_autopurge *) input CECARRYIN, - (* techmap_autopurge *) input CECTRL, - (* techmap_autopurge *) input CED, - (* techmap_autopurge *) input CEINMODE, - (* techmap_autopurge *) input CEM, - (* techmap_autopurge *) input CEP, - (* techmap_autopurge *) input CLK, - (* techmap_autopurge *) input [24:0] D, - (* techmap_autopurge *) input [4:0] INMODE, - (* techmap_autopurge *) input MULTSIGNIN, - (* techmap_autopurge *) input [6:0] OPMODE, - (* techmap_autopurge *) input [47:0] PCIN, - (* techmap_autopurge *) input RSTA, - (* techmap_autopurge *) input RSTALLCARRYIN, - (* techmap_autopurge *) input RSTALUMODE, - (* techmap_autopurge *) input RSTB, - (* techmap_autopurge *) input RSTC, - (* techmap_autopurge *) input RSTCTRL, - (* techmap_autopurge *) input RSTD, - (* techmap_autopurge *) input RSTINMODE, - (* techmap_autopurge *) input RSTM, - (* techmap_autopurge *) input RSTP -); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - - wire [47:0] $P, $PCOUT; - - DSP48E1 #( - .ACASCREG(ACASCREG), - .ADREG(ADREG), - .ALUMODEREG(ALUMODEREG), - .AREG(AREG), - .AUTORESET_PATDET(AUTORESET_PATDET), - .A_INPUT(A_INPUT), - .BCASCREG(BCASCREG), - .BREG(BREG), - .B_INPUT(B_INPUT), - .CARRYINREG(CARRYINREG), - .CARRYINSELREG(CARRYINSELREG), - .CREG(CREG), - .DREG(DREG), - .INMODEREG(INMODEREG), - .MREG(MREG), - .OPMODEREG(OPMODEREG), - .PREG(PREG), - .SEL_MASK(SEL_MASK), - .SEL_PATTERN(SEL_PATTERN), - .USE_DPORT(USE_DPORT), - .USE_MULT(USE_MULT), - .USE_PATTERN_DETECT(USE_PATTERN_DETECT), - .USE_SIMD(USE_SIMD), - .MASK(MASK), - .PATTERN(PATTERN), - .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), - .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), - .IS_CLK_INVERTED(IS_CLK_INVERTED), - .IS_INMODE_INVERTED(IS_INMODE_INVERTED), - .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) - ) _TECHMAP_REPLACE_ ( - .ACOUT(ACOUT), - .BCOUT(BCOUT), - .CARRYCASCOUT(CARRYCASCOUT), - .CARRYOUT(CARRYOUT), - .MULTSIGNOUT(MULTSIGNOUT), - .OVERFLOW(OVERFLOW), - .P($P), - .PATTERNBDETECT(PATTERNBDETECT), - .PATTERNDETECT(PATTERNDETECT), - .PCOUT($PCOUT), - .UNDERFLOW(UNDERFLOW), - .A(A), - .ACIN(ACIN), - .ALUMODE(ALUMODE), - .B(B), - .BCIN(BCIN), - .C(C), - .CARRYCASCIN(CARRYCASCIN), - .CARRYIN(CARRYIN), - .CARRYINSEL(CARRYINSEL), - .CEA1(CEA1), - .CEA2(CEA2), - .CEAD(CEAD), - .CEALUMODE(CEALUMODE), - .CEB1(CEB1), - .CEB2(CEB2), - .CEC(CEC), - .CECARRYIN(CECARRYIN), - .CECTRL(CECTRL), - .CED(CED), - .CEINMODE(CEINMODE), - .CEM(CEM), - .CEP(CEP), - .CLK(CLK), - .D(D), - .INMODE(INMODE), - .MULTSIGNIN(MULTSIGNIN), - .OPMODE(OPMODE), - .PCIN(PCIN), - .RSTA(RSTA), - .RSTALLCARRYIN(RSTALLCARRYIN), - .RSTALUMODE(RSTALUMODE), - .RSTB(RSTB), - .RSTC(RSTC), - .RSTCTRL(RSTCTRL), - .RSTD(RSTD), - .RSTINMODE(RSTINMODE), - .RSTM(RSTM), - .RSTP(RSTP) - ); - $__ABC9_DSP48E1 #( - .ADREG(ADREG), - .AREG(AREG), - .BREG(BREG), - .CREG(CREG), - .DREG(DREG), - .MREG(MREG), - .PREG(PREG), - .USE_DPORT(USE_DPORT), - .USE_MULT(USE_MULT) - ) dsp_comb ( - .$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); -endmodule diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 2d109ef8a..db44ff00b 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -37,174 +37,3 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); (S1 => O) = 273; endspecify endmodule - -// Box to emulate async behaviour of FDC* -(* abc9_box, lib_whitebox *) -module \$__ABC9_ASYNC0 (input A, S, output Y); - assign Y = S ? 1'b0 : A; - specify - (A => Y) = 0; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 - (S => Y) = 764; - endspecify -endmodule - -// Box to emulate async behaviour of FDP* -(* abc9_box, lib_whitebox *) -module \$__ABC9_ASYNC1 (input A, S, output Y); - assign Y = S ? 1'b1 : A; - specify - (A => Y) = 0; - // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 - (S => Y) = 764; - endspecify -endmodule - -// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} -// Necessary since RAMD* and SRL* have both combinatorial (i.e. -// same-cycle read operation) and sequential (write operation -// is only committed on the next clock edge). -// To model the combinatorial path, such cells have to be split -// into comb and seq parts, with this box modelling only the former. -(* abc9_box *) -module \$__ABC9_RAM6 (input A, input [5:0] S, output Y); - specify - (A => Y) = 0; - (S[0] => Y) = 642; - (S[1] => Y) = 631; - (S[2] => Y) = 472; - (S[3] => Y) = 407; - (S[4] => Y) = 238; - (S[5] => Y) = 127; - endspecify -endmodule -// Box to emulate comb/seq behaviour of RAM128 -(* abc9_box *) -module \$__ABC9_RAM7 (input A, input [6:0] S, output Y); - specify - (A => Y) = 0; - // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867 - (S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; - (S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */; - endspecify -endmodule - -// Boxes used to represent the comb behaviour of DSP48E1 -(* abc9_box *) -module $__ABC9_DSP48E1 ( - input [29:0] $A, - input [17:0] $B, - input [47:0] $C, - input [24:0] $D, - input [47:0] $P, - input [47:0] $PCIN, - input [47:0] $PCOUT, - output [47:0] P, - output [47:0] PCOUT -); - parameter integer ADREG = 1; - parameter integer AREG = 1; - parameter integer BREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer MREG = 1; - parameter integer PREG = 1; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - - function integer \A.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523; - end - endfunction - function integer \A.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671; - end - endfunction - function integer \B.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509; - end - endfunction - function integer \B.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658; - end - endfunction - function integer \C.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325; - end - endfunction - function integer \C.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474; - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474; - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474; - end - endfunction - function integer \D.P.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717; - end - endfunction - function integer \D.PCOUT.comb ; - begin - if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700; - end - endfunction - - specify - ($P *> P) = 0; - ($PCOUT *> PCOUT) = 0; - endspecify - - // Identical comb delays to DSP48E1 in cells_sim.v - generate - if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) - specify - ($A *> P) = \A.P.comb (); - ($A *> PCOUT) = \A.PCOUT.comb (); - endspecify - - if (PREG == 0 && MREG == 0 && BREG == 0) - specify - ($B *> P) = \B.P.comb (); - ($B *> PCOUT) = \B.PCOUT.comb (); - endspecify - - if (PREG == 0 && CREG == 0) - specify - ($C *> P) = \C.P.comb (); - ($C *> PCOUT) = \C.PCOUT.comb (); - endspecify - - if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) - specify - ($D *> P) = \D.P.comb (); - ($D *> PCOUT) = \D.PCOUT.comb (); - endspecify - - if (PREG == 0) - specify - ($PCIN *> P) = 1107; - ($PCIN *> PCOUT) = 1255; - endspecify - endgenerate -endmodule diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v deleted file mode 100644 index 49a7bd88c..000000000 --- a/techlibs/xilinx/abc9_unmap.v +++ /dev/null @@ -1,57 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * 2019 Eddie Hung - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// ============================================================================ - -(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *) -module $__ABC9_ASYNC01(input A, S, output Y); - assign Y = A; -endmodule - -module $__ABC9_RAM6(input A, input [5:0] S, output Y); - assign Y = A; -endmodule -module $__ABC9_RAM7(input A, input [6:0] S, output Y); - assign Y = A; -endmodule - -module $__ABC9_DSP48E1( - input [29:0] $A, - input [17:0] $B, - input [47:0] $C, - input [24:0] $D, - input [47:0] $P, - input [47:0] $PCIN, - input [47:0] $PCOUT, - output [47:0] P, - output [47:0] PCOUT -); - parameter integer ADREG = 1; - parameter integer AREG = 1; - parameter integer BREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer MREG = 1; - parameter integer PREG = 1; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - - assign P = $P, PCOUT = $PCOUT; -endmodule diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 25df3a865..a6eb9a90e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -524,10 +524,10 @@ module FDRE ( $setup(R , posedge C &&& !IS_C_INVERTED, 404); $setup(R , negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 - if (!IS_C_INVERTED && R ^ IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303; - if ( IS_C_INVERTED && R ^ IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303; - if (!IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303; + if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303; + if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; endspecify endmodule @@ -589,10 +589,10 @@ module FDSE ( $setup(S , posedge C &&& !IS_C_INVERTED, 404); $setup(S , negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243 - if (!IS_C_INVERTED && S ^ IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303; - if ( IS_C_INVERTED && S ^ IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303; - if (!IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303; + if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303; + if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; endspecify endmodule @@ -656,6 +656,7 @@ module FDRSE ( Q <= d; endmodule +(* abc9_box, lib_whitebox *) module FDCE ( output reg Q, (* clkbuf_sink *) @@ -691,13 +692,15 @@ module FDCE ( $setup(CLR, posedge C &&& !IS_C_INVERTED, 404); $setup(CLR, negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 - //if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0 - //if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0 - if (!IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path + if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; endspecify endmodule +(* abc9_box, lib_whitebox *) module FDCE_1 ( output reg Q, (* clkbuf_sink *) @@ -717,11 +720,14 @@ module FDCE_1 ( // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(CLR, negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 - //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0 + if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path if (!CLR && CE) (negedge C => (Q : D)) = 303; endspecify endmodule +//(* abc9_box, lib_whitebox *) module FDPE ( output reg Q, (* clkbuf_sink *) @@ -756,13 +762,15 @@ module FDPE ( $setup(PRE, posedge C &&& !IS_C_INVERTED, 404); $setup(PRE, negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 - //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1 - //if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1 - if (!IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; - if ( IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path + if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; + if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; endspecify endmodule +(* abc9_box, lib_whitebox *) module FDPE_1 ( output reg Q, (* clkbuf_sink *) @@ -782,8 +790,9 @@ module FDPE_1 ( // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(PRE, negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 - //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1 - //if (IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1 + if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path if (!PRE && CE) (negedge C => (Q : D)) = 303; endspecify endmodule @@ -1395,6 +1404,7 @@ module RAM16X1D_1 ( always @(negedge clk) if (WE) mem[a] <= D; endmodule +(* abc9_box, lib_whitebox *) module RAM32X1D ( output DPO, SPO, input D, @@ -1441,15 +1451,15 @@ module RAM32X1D ( if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153; if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153; if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153; - // Captured by $__ABC9_RAM6 - //({A0,DPRA0} => {SPO,DPO}) = 642; - //({A1,DPRA1} => {SPO,DPO}) = 631; - //({A2,DPRA2} => {SPO,DPO}) = 472; - //({A3,DPRA3} => {SPO,DPO}) = 407; - //({A4,DPRA4} => {SPO,DPO}) = 238; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; endspecify endmodule +(* abc9_box, lib_whitebox *) module RAM32X1D_1 ( output DPO, SPO, input D, @@ -1491,15 +1501,15 @@ module RAM32X1D_1 ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 if (WE) (negedge WCLK => (SPO : D)) = 1153; if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; - // Captured by $__ABC9_RAM6 - //({A0,DPRA0} => {SPO,DPO}) = 642; - //({A1,DPRA1} => {SPO,DPO}) = 631; - //({A2,DPRA2} => {SPO,DPO}) = 472; - //({A3,DPRA3} => {SPO,DPO}) = 407; - //({A4,DPRA4} => {SPO,DPO}) = 238; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; endspecify endmodule +(* abc9_box, lib_whitebox *) module RAM64X1D ( output DPO, SPO, input D, @@ -1549,13 +1559,12 @@ module RAM64X1D ( if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153; - // Captured by $__ABC9_RAM6 - //({A0,DPRA0} => {SPO,DPO}) = 642; - //({A1,DPRA1} => {SPO,DPO}) = 631; - //({A2,DPRA2} => {SPO,DPO}) = 472; - //({A3,DPRA3} => {SPO,DPO}) = 407; - //({A4,DPRA4} => {SPO,DPO}) = 238; - //({A5,DPRA5} => {SPO,DPO}) = 127; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + (A5 => SPO) = 127; (DPRA5 => DPO) = 127; endspecify endmodule @@ -1598,9 +1607,16 @@ module RAM64X1D_1 ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 if (WE) (negedge WCLK => (SPO : D)) = 1153; if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153; + (A0 => SPO) = 642; (DPRA0 => DPO) = 642; + (A1 => SPO) = 632; (DPRA1 => DPO) = 631; + (A2 => SPO) = 472; (DPRA2 => DPO) = 472; + (A3 => SPO) = 407; (DPRA3 => DPO) = 407; + (A4 => SPO) = 238; (DPRA4 => DPO) = 238; + (A5 => SPO) = 127; (DPRA5 => DPO) = 127; endspecify endmodule +(* abc9_box, lib_whitebox *) module RAM128X1D ( output DPO, SPO, input D, @@ -1645,21 +1661,20 @@ module RAM128X1D ( if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; `endif - // Captured by $__ABC9_RAM7 - //(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - //(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - //(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - //(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - //(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - //(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; - //(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */; - //(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; - //(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; - //(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; - //(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; - //(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; - //(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; - //(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */; + (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; + (A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */; + (DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; + (DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; + (DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; + (DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; + (DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; + (DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; + (DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */; endspecify endmodule @@ -1683,6 +1698,7 @@ endmodule // Multi port. +(* abc9_box, lib_whitebox *) module RAM32M ( output [1:0] DOA, output [1:0] DOB, @@ -1779,12 +1795,11 @@ module RAM32M ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061 if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190; - // Captured by $__ABC9_RAM6 - //({{2{ADDRA[0]}},{2{ADDRB[0]}},{2{ADDRC[0]}},{2{ADDRD[0]}}} => {DOA,DOB,DOC,DOD}) = 642; - //({{2{ADDRA[1]}},{2{ADDRB[1]}},{2{ADDRC[1]}},{2{ADDRD[1]}}} => {DOA,DOB,DOC,DOD}) = 631; - //({{2{ADDRA[2]}},{2{ADDRB[2]}},{2{ADDRC[2]}},{2{ADDRD[2]}}} => {DOA,DOB,DOC,DOD}) = 472; - //({{2{ADDRA[3]}},{2{ADDRB[3]}},{2{ADDRC[3]}},{2{ADDRD[3]}}} => {DOA,DOB,DOC,DOD}) = 407; - //({{2{ADDRA[4]}},{2{ADDRB[4]}},{2{ADDRC[4]}},{2{ADDRD[4]}}} => {DOA,DOB,DOC,DOD}) = 238; + (ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642; + (ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631; + (ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472; + (ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407; + (ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238; endspecify endmodule @@ -1857,6 +1872,7 @@ module RAM32M16 ( end endmodule +(* abc9_box, lib_whitebox *) module RAM64M ( output DOA, output DOB, @@ -1935,12 +1951,11 @@ module RAM64M ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093 if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163; - // Captured by $__ABC9_RAM6 - //({ADDRA[0],ADDRB[0],ADDRC[0],ADDRD[0]} => {DOA,DOB,DOC,DOD}) = 642; - //({ADDRA[1],ADDRB[1],ADDRC[1],ADDRD[1]} => {DOA,DOB,DOC,DOD}) = 631; - //({ADDRA[2],ADDRB[2],ADDRC[2],ADDRD[2]} => {DOA,DOB,DOC,DOD}) = 472; - //({ADDRA[3],ADDRB[3],ADDRC[3],ADDRD[3]} => {DOA,DOB,DOC,DOD}) = 407; - //({ADDRA[4],ADDRB[4],ADDRC[4],ADDRD[4]} => {DOA,DOB,DOC,DOD}) = 238; + (ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642; + (ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631; + (ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472; + (ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407; + (ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238; endspecify endmodule @@ -2057,6 +2072,7 @@ endmodule // Shift registers. +(* abc9_box, lib_whitebox *) module SRL16 ( output Q, input A0, A1, A2, A3, @@ -2075,14 +2091,14 @@ module SRL16 ( (posedge CLK => (Q : 1'bx)) = 1472; // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 $setup(D , posedge CLK, 173); - // Captured by $__ABC9_RAM6 - //(A0 => Q) = 631; - //(A1 => Q) = 472; - //(A2 => Q) = 407; - //(A3 => Q) = 238; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; endspecify endmodule +(* abc9_box, lib_whitebox *) module SRL16E ( output Q, input A0, A1, A2, A3, CE, @@ -2108,16 +2124,19 @@ module SRL16E ( $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472; if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472; - // Captured by $__ABC9_RAM6 - //(A0 => Q) = 631; - //(A1 => Q) = 472; - //(A2 => Q) = 407; - //(A3 => Q) = 238; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; endspecify endmodule +(* abc9_box, lib_whitebox *) module SRLC16 ( output Q, output Q15, @@ -2134,18 +2153,20 @@ module SRLC16 ( always @(posedge CLK) r <= { r[14:0], D }; specify - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 - (posedge CLK => (Q : 1'bx)) = 1472; // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 $setup(D , posedge CLK, 173); - // Captured by $__ABC9_RAM6 - //(A0 => Q) = 631; - //(A1 => Q) = 472; - //(A2 => Q) = 407; - //(A3 => Q) = 238; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 + (posedge CLK => (Q : 1'bx)) = 1472; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 + (posedge CLK => (Q15 : 1'bx)) = 1114; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; endspecify endmodule +(* abc9_box, lib_whitebox *) module SRLC16E ( output Q, output Q15, @@ -2172,18 +2193,23 @@ module SRLC16E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109); + $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109); // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472; if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472; - // Captured by $__ABC9_RAM6 - //(A0 => Q) = 642; - //(A1 => Q) = 631; - //(A2 => Q) = 472; - //(A3 => Q) = 407; - //(A4 => Q) = 238; + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114; + (A0 => Q) = 631; + (A1 => Q) = 472; + (A2 => Q) = 407; + (A3 => Q) = 238; endspecify endmodule +(* abc9_box, lib_whitebox *) module SRLC32E ( output Q, output Q31, @@ -2211,18 +2237,20 @@ module SRLC32E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912 $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173); $setup(D , negedge CLK &&& IS_CLK_INVERTED, 173); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 + $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109); + $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109); // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472; if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472; // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 - if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1114; - if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1114; - // Captured by $__ABC9_RAM6 - //(A0 => Q) = 642; - //(A1 => Q) = 631; - //(A2 => Q) = 472; - //(A3 => Q) = 407; - //(A4 => Q) = 238; + if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114; + if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114; + (A[0] => Q) = 642; + (A[1] => Q) = 631; + (A[2] => Q) = 472; + (A[3] => Q) = 407; + (A[4] => Q) = 238; endspecify endmodule @@ -2990,6 +3018,8 @@ endmodule // Virtex 6, Series 7. +(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG), + lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *) module DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d6ca9e57e..d05715ec2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_ffs", "('-abc9' only)")) { if (abc9 || help_mode) { if (dff || help_mode) - run("zinit -all", "('-dff' only)"); + run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)"); run("techmap -map " + ff_map_file); } } @@ -615,7 +615,6 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); - run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v"); std::string abc9_opts; std::string k = "synth_xilinx.abc9.W"; @@ -630,7 +629,6 @@ struct SynthXilinxPass : public ScriptPass if (dff) abc9_opts += " -dff"; run("abc9" + abc9_opts); - run("techmap -map +/xilinx/abc9_unmap.v"); } else { std::string abc_opts; -- cgit v1.2.3 From a323881e152c0d51728f3df773ac2f326544b379 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 14:13:38 -0700 Subject: xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells --- techlibs/ecp5/cells_sim.v | 29 ++++++++- techlibs/ice40/cells_sim.v | 153 ++++++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/cells_sim.v | 20 +++++- 3 files changed, 198 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 563592218..6f37823e4 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -186,6 +186,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- +(* abc9_box, lib_whitebox *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, @@ -222,10 +223,16 @@ module TRELLIS_DPR16X4 ( mem[WAD] <= DI; assign DO = mem[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify endmodule // --------------------------------------- +(* abc9_box, lib_whitebox *) module DPR16X4C ( input [3:0] DI, input WCK, WRE, @@ -281,6 +288,10 @@ module DPR16X4C ( assign DO = ram[RAD]; + specify + // TODO + (RAD *> DO) = 0; + endspecify endmodule // --------------------------------------- @@ -295,7 +306,7 @@ endmodule // --------------------------------------- `ifdef YOSYS -(* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *) +(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *) `endif module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter GSR = "ENABLED"; @@ -351,15 +362,27 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); $setup(DI, negedge CLK, 0); $setup(CE, negedge CLK, 0); $setup(LSR, negedge CLK, 0); - if (muxlsr) (negedge CLK => (Q : DI)) = 0; - if (!muxlsr && muxce) (negedge CLK => (Q : srval)) = 0; +`ifndef YOSYS + if (muxlsr) (negedge CLK => (Q : srval)) = 0; +`else + if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0; endspecify else specify $setup(DI, posedge CLK, 0); $setup(CE, posedge CLK, 0); $setup(LSR, posedge CLK, 0); +`ifndef YOSYS if (muxlsr) (posedge CLK => (Q : srval)) = 0; +`else + if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0; endspecify endgenerate diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 1b759a28f..ad572c877 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -372,6 +372,7 @@ module SB_DFFSR ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFR ( output `SB_DFF_REG, input C, R, D @@ -389,7 +390,13 @@ module SB_DFFR ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(negedge R, posedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 599; +`else + if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (!R) (posedge C => (Q : D)) = 540; endspecify @@ -402,7 +409,13 @@ module SB_DFFR ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(negedge R, posedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 883; +`else + if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (!R) (posedge C => (Q : D)) = 796; endspecify @@ -415,7 +428,13 @@ module SB_DFFR ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge R, posedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 1589; +`else + if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (!R) (posedge C => (Q : D)) = 1391; endspecify @@ -470,6 +489,7 @@ module SB_DFFSS ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFS ( output `SB_DFF_REG, input C, S, D @@ -487,7 +507,13 @@ module SB_DFFS ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(negedge S, posedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 599; +`else + if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (!S) (posedge C => (Q : D)) = 540; endspecify @@ -500,7 +526,13 @@ module SB_DFFS ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(negedge S, posedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 883; +`else + if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (!S) (posedge C => (Q : D)) = 796; endspecify @@ -513,7 +545,13 @@ module SB_DFFS ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge S, posedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 1589; +`else + if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (!S) (posedge C => (Q : D)) = 1391; endspecify @@ -576,6 +614,7 @@ module SB_DFFESR ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFER ( output `SB_DFF_REG, input C, E, R, D @@ -595,7 +634,13 @@ module SB_DFFER ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(negedge R, posedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 599; +`else + if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (E && !R) (posedge C => (Q : D)) = 540; endspecify @@ -610,7 +655,13 @@ module SB_DFFER ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(negedge R, posedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 883; +`else + if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (E && !R) (posedge C => (Q : D)) = 796; endspecify @@ -625,7 +676,13 @@ module SB_DFFER ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge R, posedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 1589; +`else + if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (E && !R) (posedge C => (Q : D)) = 1391; endspecify @@ -688,6 +745,7 @@ module SB_DFFESS ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFES ( output `SB_DFF_REG, input C, E, S, D @@ -707,7 +765,13 @@ module SB_DFFES ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(posedge S, posedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 599; +`else + if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (E && !S) (posedge C => (Q : D)) = 540; endspecify @@ -722,7 +786,13 @@ module SB_DFFES ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(posedge S, posedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 883; +`else + if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (E && !S) (posedge C => (Q : D)) = 796; endspecify @@ -737,7 +807,13 @@ module SB_DFFES ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(posedge S, posedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 1589; +`else + if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (E && !S) (posedge C => (Q : D)) = 1391; endspecify @@ -891,7 +967,13 @@ module SB_DFFNR ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(negedge R, negedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 599; +`else + if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (!R) (negedge C => (Q : D)) = 540; endspecify @@ -904,7 +986,13 @@ module SB_DFFNR ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(negedge R, negedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 883; +`else + if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (!R) (negedge C => (Q : D)) = 796; endspecify @@ -917,7 +1005,13 @@ module SB_DFFNR ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge R, negedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 1589; +`else + if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (!R) (negedge C => (Q : D)) = 1391; endspecify @@ -972,6 +1066,7 @@ module SB_DFFNSS ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFNS ( output `SB_DFF_REG, input C, S, D @@ -989,7 +1084,13 @@ module SB_DFFNS ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(negedge S, negedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 599; +`else + if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (!S) (negedge C => (Q : D)) = 540; endspecify @@ -1002,7 +1103,13 @@ module SB_DFFNS ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(negedge S, negedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 883; +`else + if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (!S) (negedge C => (Q : D)) = 796; endspecify @@ -1015,7 +1122,13 @@ module SB_DFFNS ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge S, negedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 1589; +`else + if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (!S) (negedge C => (Q : D)) = 1391; endspecify @@ -1078,6 +1191,7 @@ module SB_DFFNESR ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFNER ( output `SB_DFF_REG, input C, E, R, D @@ -1097,7 +1211,13 @@ module SB_DFFNER ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(R, negedge C, 2160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 599; +`else + if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (E && !R) (negedge C => (Q : D)) = 540; endspecify @@ -1112,7 +1232,13 @@ module SB_DFFNER ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(R, negedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 883; +`else + if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (E && !R) (negedge C => (Q : D)) = 796; endspecify @@ -1127,7 +1253,13 @@ module SB_DFFNER ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge R, negedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge R => (Q : 1'b0)) = 1589; +`else + if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (E && !R) (negedge C => (Q : D)) = 1391; endspecify @@ -1190,6 +1322,7 @@ module SB_DFFNESS ( `endif endmodule +(* abc9_box, lib_whitebox *) module SB_DFFNES ( output `SB_DFF_REG, input C, E, S, D @@ -1209,7 +1342,14 @@ module SB_DFFNES ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63 $setup(negedge S, negedge C, 160); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 599; +`else + if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 if (E && !S) (negedge C => (Q : D)) = 540; endspecify @@ -1224,7 +1364,13 @@ module SB_DFFNES ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63 $setup(negedge S, negedge C, 235); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 883; +`else + if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 if (E && !S) (negedge C => (Q : D)) = 796; endspecify @@ -1239,7 +1385,13 @@ module SB_DFFNES ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75 $setup(negedge S, negedge C, 424); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103 +`ifndef YOSYS (posedge S => (Q : 1'b1)) = 1589; +`else + if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 if (E && !S) (negedge C => (Q : D)) = 1391; endspecify @@ -2736,6 +2888,7 @@ module SB_IO_OD ( `endif endmodule +//(* abc9_box, lib_whitebox *) // TODO module SB_MAC16 ( input CLK, CE, input [15:0] C, A, B, D, diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index a6eb9a90e..cd611399e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -692,9 +692,14 @@ module FDCE ( $setup(CLR, posedge C &&& !IS_C_INVERTED, 404); $setup(CLR, negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; + if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; +`else if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path // but for facilitating a bypass box, let's pretend it's // a simple path +`endif if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; endspecify @@ -720,14 +725,18 @@ module FDCE_1 ( // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(CLR, negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + (posedge CLR => (Q : 1'b0)) = 764; +`else if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path // but for facilitating a bypass box, let's pretend it's // a simple path +`endif if (!CLR && CE) (negedge C => (Q : D)) = 303; endspecify endmodule -//(* abc9_box, lib_whitebox *) +(* abc9_box, lib_whitebox *) module FDPE ( output reg Q, (* clkbuf_sink *) @@ -762,9 +771,14 @@ module FDPE ( $setup(PRE, posedge C &&& !IS_C_INVERTED, 404); $setup(PRE, negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; + if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; +`else if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path // but for facilitating a bypass box, let's pretend it's // a simple path +`endif if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303; if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303; endspecify @@ -790,9 +804,13 @@ module FDPE_1 ( // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(PRE, negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 +`ifndef YOSYS + (posedge PRE => (Q : 1'b1)) = 764; +`else if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path // but for facilitating a bypass box, let's pretend it's // a simple path +`endif if (!PRE && CE) (negedge C => (Q : D)) = 303; endspecify endmodule -- cgit v1.2.3 From 6c34945371a0446159423b0d70f9f10dbc2c4d07 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 15:45:05 -0700 Subject: xilinx/ice40/ecp5: zinit requires selected wires, so select them all --- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 3e475baab..0e49ef01a 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -316,7 +316,7 @@ struct SynthEcp5Pass : public ScriptPass if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); if ((abc9 && dff) || help_mode) - run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff"); + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff"); run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index f2270dbca..27850b075 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -362,7 +362,7 @@ struct SynthIce40Pass : public ScriptPass run("simplemap t:$dff"); } if ((abc9 && dff) || help_mode) - run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff"); + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff"); run("techmap -map +/ice40/ff_map.v"); run("opt_expr -mux_undef"); run("simplemap"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d05715ec2..d0de73f83 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -598,7 +598,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_ffs", "('-abc9' only)")) { if (abc9 || help_mode) { if (dff || help_mode) - run("zinit -all t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)"); + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)"); run("techmap -map " + ff_map_file); } } @@ -608,7 +608,7 @@ struct SynthXilinxPass : public ScriptPass if (flatten_before_abc) run("flatten"); if (help_mode) - run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')"); + run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); else if (abc9) { if (lut_size != 6) log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n"); -- cgit v1.2.3 From 8cda29137e0e1c19e1115211ee695681bc901030 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 17:04:26 -0700 Subject: ecp5: TRELLIS_FF bypass path only in async mode --- techlibs/ecp5/cells_sim.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 6f37823e4..357fd9173 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -363,11 +363,11 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); $setup(CE, negedge CLK, 0); $setup(LSR, negedge CLK, 0); `ifndef YOSYS - if (muxlsr) (negedge CLK => (Q : srval)) = 0; + if (SRMODE == "ASYNC" && muxlsr) (negedge CLK => (Q : srval)) = 0; `else - if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path + if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path `endif if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0; endspecify @@ -377,11 +377,11 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); $setup(CE, posedge CLK, 0); $setup(LSR, posedge CLK, 0); `ifndef YOSYS - if (muxlsr) (posedge CLK => (Q : srval)) = 0; + if (SRMODE == "ASYNC" && muxlsr) (posedge CLK => (Q : srval)) = 0; `else - if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path - // but for facilitating a bypass box, let's pretend it's - // a simple path + if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path `endif if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0; endspecify -- cgit v1.2.3 From 57c478c537ef23c05ca34ecdf4c4334fd82c104e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 17:54:24 -0700 Subject: abc9: only do +/abc9_map if `DFF --- techlibs/common/abc9_map.v | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v index 5f1822485..57b3831d8 100644 --- a/techlibs/common/abc9_map.v +++ b/techlibs/common/abc9_map.v @@ -1,3 +1,4 @@ +`ifdef DFF (* techmap_celltype = "$_DFF_N_ $_DFF_P_" *) module $_DFF_x_(input C, D, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -23,3 +24,4 @@ module $_DFF_x_(input C, D, output Q); $error("Unrecognised _TECHMAP_CELLTYPE_"); endgenerate endmodule +`endif -- cgit v1.2.3 From ca4f8c94441c16392ffc02a6117f9b3883e7042e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Apr 2020 20:44:11 -0700 Subject: xilinx: gate specify/attributes from iverilog --- techlibs/xilinx/cells_sim.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index cd611399e..d87cfe91b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1678,7 +1678,6 @@ module RAM128X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; -`endif (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; @@ -1693,6 +1692,7 @@ module RAM128X1D ( (DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; (DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; (DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */; +`endif endspecify endmodule @@ -3036,8 +3036,10 @@ endmodule // Virtex 6, Series 7. +`ifdef YOSYS (* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG), lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *) +`endif module DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, -- cgit v1.2.3 From 39759d5f0ec9bfc0db3dd718cb035596da7f9668 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 14:12:06 -0700 Subject: ecp5: fix rebase mistake --- techlibs/ecp5/synth_ecp5.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 0e49ef01a..c13020cc1 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -348,10 +348,10 @@ struct SynthEcp5Pass : public ScriptPass else abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); if (nowidelut) - abc9_args += " -maxlut 4"; + abc9_opts += " -maxlut 4"; if (dff) - abc9_args += " -dff"; - run("abc9" + abc9_args); + abc9_opts += " -dff"; + run("abc9" + abc9_opts); run("techmap -map +/ecp5/abc9_unmap.v"); } else { std::string abc_args = " -dress"; -- cgit v1.2.3 From fdc340db8e93d5b50ef515a231f2fef18bdd8165 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 14:16:42 -0700 Subject: ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v --- techlibs/ecp5/Makefile.inc | 3 --- techlibs/ecp5/abc9_map.v | 27 --------------------------- techlibs/ecp5/abc9_unmap.v | 5 ----- techlibs/ecp5/synth_ecp5.cc | 11 +++-------- 4 files changed, 3 insertions(+), 43 deletions(-) delete mode 100644 techlibs/ecp5/abc9_map.v delete mode 100644 techlibs/ecp5/abc9_unmap.v (limited to 'techlibs') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 217151e96..9a337b2b6 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -23,9 +23,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) - -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v)) EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v deleted file mode 100644 index 113a35b91..000000000 --- a/techlibs/ecp5/abc9_map.v +++ /dev/null @@ -1,27 +0,0 @@ -// --------------------------------------- - -// Attach a (combinatorial) black-box onto the output -// of this LUTRAM primitive to capture its -// asynchronous read behaviour -module TRELLIS_DPR16X4 ( - (* techmap_autopurge *) input [3:0] DI, - (* techmap_autopurge *) input [3:0] WAD, - (* techmap_autopurge *) input WRE, - (* techmap_autopurge *) input WCK, - (* techmap_autopurge *) input [3:0] RAD, - output [3:0] DO -); - parameter WCKMUX = "WCK"; - parameter WREMUX = "WRE"; - parameter [63:0] INITVAL = 64'h0000000000000000; - wire [3:0] $DO; - - TRELLIS_DPR16X4 #( - .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) - ) _TECHMAP_REPLACE_ ( - .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), - .RAD(RAD), .DO($DO) - ); - - $__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO)); -endmodule diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v deleted file mode 100644 index cbdffdaf1..000000000 --- a/techlibs/ecp5/abc9_unmap.v +++ /dev/null @@ -1,5 +0,0 @@ -// --------------------------------------- - -module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO); - assign DO = $DO; -endmodule diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index c13020cc1..b99cbdf83 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -328,14 +328,10 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("map_luts")) { - if (abc2 || help_mode) { + if (abc2 || help_mode) run("abc", " (only if -abc2)"); - } - std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v"; - if (abc9) - techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1"; - if (!techmap_args.empty()) - run("techmap " + techmap_args); + if (asyncprld || help_mode) + run("techmap -map +/ecp5/latches_map.v", "(only if -asyncprld)"); if (abc9) { run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); @@ -352,7 +348,6 @@ struct SynthEcp5Pass : public ScriptPass if (dff) abc9_opts += " -dff"; run("abc9" + abc9_opts); - run("techmap -map +/ecp5/abc9_unmap.v"); } else { std::string abc_args = " -dress"; if (nowidelut) -- cgit v1.2.3 From cea614f5aeb78446c663240103f94f10e71681e2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 14:42:18 -0700 Subject: ecp5: latches_map.v if *not* -asyncprld --- techlibs/ecp5/synth_ecp5.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index b99cbdf83..e5c1f7550 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -330,8 +330,8 @@ struct SynthEcp5Pass : public ScriptPass { if (abc2 || help_mode) run("abc", " (only if -abc2)"); - if (asyncprld || help_mode) - run("techmap -map +/ecp5/latches_map.v", "(only if -asyncprld)"); + if (!asyncprld || help_mode) + run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)"); if (abc9) { run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); -- cgit v1.2.3 From e79127fcebf9c5aed47f6f56fcfc8a4c4f98705c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 18:02:05 -0700 Subject: Cleanup; reduce Module::derive() calls --- techlibs/common/abc9_model.v | 6 +++--- techlibs/common/abc9_unmap.v | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v index 41acf4d97..a86f6a436 100644 --- a/techlibs/common/abc9_model.v +++ b/techlibs/common/abc9_model.v @@ -1,5 +1,5 @@ (* abc9_box *) -module \$__ABC9_DELAY (input I, output O); +module $__ABC9_DELAY (input I, output O); parameter DELAY = 0; specify (I => O) = DELAY; @@ -7,7 +7,7 @@ module \$__ABC9_DELAY (input I, output O); endmodule (* abc9_flop, abc9_box, lib_whitebox *) -module $__DFF_N__$abc9_flop(input C, D, Q, (* init=INIT *) output n1); +module $__DFF_N__$abc9_flop (input C, D, Q, (* init=INIT *) output n1); parameter [0:0] INIT = 1'bx; assign n1 = D; specify @@ -17,7 +17,7 @@ module $__DFF_N__$abc9_flop(input C, D, Q, (* init=INIT *) output n1); endmodule (* abc9_flop, abc9_box, lib_whitebox *) -module $__DFF_P__$abc9_flop(input C, D, Q, (* init=INIT *) output n1); +module $__DFF_P__$abc9_flop (input C, D, Q, (* init=INIT *) output n1); parameter [0:0] INIT = 1'bx; assign n1 = D; specify diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v index 4dfac0cbb..d628a73ac 100644 --- a/techlibs/common/abc9_unmap.v +++ b/techlibs/common/abc9_unmap.v @@ -12,7 +12,7 @@ module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1); endmodule (* techmap_celltype = "$__DFF_N_ $__DFF_P_" *) -module $__DFF_N__$abc9_flop(input C, D, output Q); +module $__DFF_N__$abc9_flop (input C, D, output Q); parameter _TECHMAP_CELLTYPE_ = ""; generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_") $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); -- cgit v1.2.3 From 97a0a0431489568300b40c1d376af7b5d8cb7027 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 21:56:06 -0700 Subject: abc9_ops/xaiger: further reducing Module::derive() calls by ... replacing _all_ (* abc9_box *) instantiations with their derived types --- techlibs/common/abc9_map.v | 6 +++--- techlibs/common/abc9_model.v | 6 ++---- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v index 57b3831d8..182915842 100644 --- a/techlibs/common/abc9_map.v +++ b/techlibs/common/abc9_map.v @@ -3,10 +3,10 @@ module $_DFF_x_(input C, D, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; parameter _TECHMAP_CELLTYPE_ = ""; - wire D_; + (* init=_TECHMAP_WIREINIT_Q_ *) wire D_; generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin - $__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); + $__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); $_DFF_N_ ff (.C(C), .D(D_), .Q(Q)); end else @@ -14,7 +14,7 @@ module $_DFF_x_(input C, D, output Q); end else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin - $__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); + $__DFF_P__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); $_DFF_P_ ff (.C(C), .D(D_), .Q(Q)); end else diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v index a86f6a436..4fee60f75 100644 --- a/techlibs/common/abc9_model.v +++ b/techlibs/common/abc9_model.v @@ -7,8 +7,7 @@ module $__ABC9_DELAY (input I, output O); endmodule (* abc9_flop, abc9_box, lib_whitebox *) -module $__DFF_N__$abc9_flop (input C, D, Q, (* init=INIT *) output n1); - parameter [0:0] INIT = 1'bx; +module $__DFF_N__$abc9_flop (input C, D, Q, output n1); assign n1 = D; specify $setup(D, posedge C, 0); @@ -17,8 +16,7 @@ module $__DFF_N__$abc9_flop (input C, D, Q, (* init=INIT *) output n1); endmodule (* abc9_flop, abc9_box, lib_whitebox *) -module $__DFF_P__$abc9_flop (input C, D, Q, (* init=INIT *) output n1); - parameter [0:0] INIT = 1'bx; +module $__DFF_P__$abc9_flop (input C, D, Q, output n1); assign n1 = D; specify $setup(D, posedge C, 0); -- cgit v1.2.3 From 13f9d65b6fc09af76330c02ab420324b50db61da Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 00:29:45 -0700 Subject: abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it --- techlibs/common/abc9_map.v | 4 ++-- techlibs/common/abc9_unmap.v | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v index 182915842..bb2b4a4b1 100644 --- a/techlibs/common/abc9_map.v +++ b/techlibs/common/abc9_map.v @@ -3,14 +3,14 @@ module $_DFF_x_(input C, D, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; parameter _TECHMAP_CELLTYPE_ = ""; - (* init=_TECHMAP_WIREINIT_Q_ *) wire D_; + wire D_; generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin $__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_)); $_DFF_N_ ff (.C(C), .D(D_), .Q(Q)); end else - $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));// hide from abc9 using $__ prefix + $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix end else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v index d628a73ac..b765356d8 100644 --- a/techlibs/common/abc9_unmap.v +++ b/techlibs/common/abc9_unmap.v @@ -1,6 +1,5 @@ (* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *) -module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1); - parameter [0:0] INIT = 1'bx; +module $__DFF_x__$abc9_flop (input C, D, Q, output n1); parameter _TECHMAP_CELLTYPE_ = ""; generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop") $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); @@ -12,7 +11,7 @@ module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1); endmodule (* techmap_celltype = "$__DFF_N_ $__DFF_P_" *) -module $__DFF_N__$abc9_flop (input C, D, output Q); +module $__DFF_x_ (input C, D, output Q); parameter _TECHMAP_CELLTYPE_ = ""; generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_") $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); -- cgit v1.2.3 From 67fc0c3698693f049e805211c49d6219f17d7c7d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 16:44:35 -0700 Subject: abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ instead of moving them to $__ prefix --- techlibs/common/abc9_map.v | 4 ++-- techlibs/common/abc9_unmap.v | 12 ------------ 2 files changed, 2 insertions(+), 14 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v index bb2b4a4b1..6ed90b5f5 100644 --- a/techlibs/common/abc9_map.v +++ b/techlibs/common/abc9_map.v @@ -10,7 +10,7 @@ module $_DFF_x_(input C, D, output Q); $_DFF_N_ ff (.C(C), .D(D_), .Q(Q)); end else - $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix + (* abc9_keep *) $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); end else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin @@ -18,7 +18,7 @@ module $_DFF_x_(input C, D, output Q); $_DFF_P_ ff (.C(C), .D(D_), .Q(Q)); end else - $__DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix + (* abc9_keep *) $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); end else if (_TECHMAP_CELLTYPE_ != "") $error("Unrecognised _TECHMAP_CELLTYPE_"); diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v index b765356d8..bcbe91477 100644 --- a/techlibs/common/abc9_unmap.v +++ b/techlibs/common/abc9_unmap.v @@ -9,15 +9,3 @@ module $__DFF_x__$abc9_flop (input C, D, Q, output n1); $error("Unrecognised _TECHMAP_CELLTYPE_"); endgenerate endmodule - -(* techmap_celltype = "$__DFF_N_ $__DFF_P_" *) -module $__DFF_x_ (input C, D, output Q); - parameter _TECHMAP_CELLTYPE_ = ""; - generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_") - $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); - else if (_TECHMAP_CELLTYPE_ == "$__DFF_P_") - $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); - else if (_TECHMAP_CELLTYPE_ != "") - $error("Unrecognised _TECHMAP_CELLTYPE_"); - endgenerate -endmodule -- cgit v1.2.3 From aee439360bba642dcbffe5b803aa9a994b11d183 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Mon, 18 May 2020 18:15:03 +0200 Subject: Add force_downto and force_upto wire attributes. Fixes #2058. --- techlibs/achronix/speedster22i/cells_arith.v | 6 +++ techlibs/achronix/speedster22i/cells_map.v | 1 + techlibs/anlogic/arith_map.v | 9 ++++ techlibs/anlogic/cells_map.v | 1 + techlibs/common/adff2dff.v | 3 ++ techlibs/common/cmp2lcu.v | 12 +++++ techlibs/common/cmp2lut.v | 3 ++ techlibs/common/dff2ff.v | 2 + techlibs/common/mul2dsp.v | 18 +++++++ techlibs/common/techmap.v | 73 +++++++++++++++++++--------- techlibs/coolrunner2/cells_counter_map.v | 1 + techlibs/ecp5/arith_map.v | 10 ++++ techlibs/ecp5/cells_map.v | 1 + techlibs/efinix/arith_map.v | 11 ++++- techlibs/efinix/cells_map.v | 1 + techlibs/gowin/arith_map.v | 8 +++ techlibs/gowin/cells_map.v | 1 + techlibs/greenpak4/cells_map.v | 2 + techlibs/ice40/arith_map.v | 8 +++ techlibs/ice40/cells_map.v | 1 + techlibs/intel/arria10gx/cells_arith.v | 6 +++ techlibs/intel/arria10gx/cells_map.v | 1 + techlibs/intel/cyclone10lp/cells_arith.v | 6 +++ techlibs/intel/cyclone10lp/cells_map.v | 1 + techlibs/intel/cycloneiv/cells_arith.v | 6 +++ techlibs/intel/cycloneiv/cells_map.v | 1 + techlibs/intel/cycloneive/arith_map.v | 6 +++ techlibs/intel/cycloneive/cells_map.v | 1 + techlibs/intel/cyclonev/cells_arith.v | 6 +++ techlibs/intel/cyclonev/cells_map.v | 1 + techlibs/intel/max10/cells_arith.v | 6 +++ techlibs/intel/max10/cells_map.v | 1 + techlibs/intel_alm/common/alm_map.v | 1 + techlibs/intel_alm/common/arith_alm_map.v | 7 +++ techlibs/sf2/cells_map.v | 1 + techlibs/xilinx/arith_map.v | 23 +++++++++ techlibs/xilinx/cells_map.v | 6 +++ techlibs/xilinx/lut_map.v | 1 + techlibs/xilinx/mux_map.v | 3 ++ 39 files changed, 232 insertions(+), 24 deletions(-) (limited to 'techlibs') diff --git a/techlibs/achronix/speedster22i/cells_arith.v b/techlibs/achronix/speedster22i/cells_arith.v index e2194cbd7..8529706a7 100644 --- a/techlibs/achronix/speedster22i/cells_arith.v +++ b/techlibs/achronix/speedster22i/cells_arith.v @@ -26,8 +26,11 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -36,11 +39,14 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v index 9f647cbef..a19e53f49 100644 --- a/techlibs/achronix/speedster22i/cells_map.v +++ b/techlibs/achronix/speedster22i/cells_map.v @@ -38,6 +38,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index 1186543da..23e190bcb 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -26,24 +26,33 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; wire CIx; + (* force_downto *) wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) wire [Y_WIDTH-1:0] C = { COx, CIx }; wire dummy; diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v index 8ac087d9d..0bcea9856 100644 --- a/techlibs/anlogic/cells_map.v +++ b/techlibs/anlogic/cells_map.v @@ -32,6 +32,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v index 86744d415..eca0110eb 100644 --- a/techlibs/common/adff2dff.v +++ b/techlibs/common/adff2dff.v @@ -6,8 +6,11 @@ module adff2dff (CLK, ARST, D, Q); parameter ARST_VALUE = 0; input CLK, ARST; + (* force_downto *) input [WIDTH-1:0] D; + (* force_downto *) output reg [WIDTH-1:0] Q; + (* force_downto *) wire reg [WIDTH-1:0] NEXT_Q; wire [1023:0] _TECHMAP_DO_ = "proc;;"; diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v index e42f346d1..a221727e7 100644 --- a/techlibs/common/cmp2lcu.v +++ b/techlibs/common/cmp2lcu.v @@ -12,8 +12,11 @@ parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; +(* force_downto *) input [A_WIDTH-1:0] A; +(* force_downto *) input [B_WIDTH-1:0] B; +(* force_downto *) output [Y_WIDTH-1:0] Y; parameter _TECHMAP_CELLTYPE_ = ""; @@ -32,7 +35,9 @@ generate else begin // Perform sign extension on A and B localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH; + (* force_downto *) wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A}; + (* force_downto *) wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B}; // For $ge operation, start with the assumption that A and B are // equal (propagating this equality if A and B turn out to be so) @@ -54,9 +59,13 @@ parameter LCU_WIDTH = 1; parameter BUDGET = 0; parameter CI = 0; +(* force_downto *) input [AB_WIDTH-1:0] A; // A from original $gt/$ge +(* force_downto *) input [AB_WIDTH-1:0] B; // B from original $gt/$ge +(* force_downto *) input [LCU_WIDTH-1:0] P; // P of $lcu +(* force_downto *) input [LCU_WIDTH-1:0] G; // G of $lcu output Y; @@ -66,6 +75,7 @@ parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0; generate if (AB_WIDTH == 0) begin + (* force_downto *) wire [LCU_WIDTH-1:0] CO; $lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO)); assign Y = CO[LCU_WIDTH-1]; @@ -104,8 +114,10 @@ generate else begin // Propagate only if all pairs are equal // (inconclusive evidence to say A >= B) + (* force_downto *) wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP}; // Generate if any comparisons call for it + (* force_downto *) wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG}; end if (AB_WIDTH == 1) diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v index 8ecd356cc..ec8f98e8d 100644 --- a/techlibs/common/cmp2lut.v +++ b/techlibs/common/cmp2lut.v @@ -16,8 +16,11 @@ parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; +(* force_downto *) input [A_WIDTH-1:0] A; +(* force_downto *) input [B_WIDTH-1:0] B; +(* force_downto *) output [Y_WIDTH-1:0] Y; parameter _TECHMAP_CELLTYPE_ = ""; diff --git a/techlibs/common/dff2ff.v b/techlibs/common/dff2ff.v index 2dc4d20d3..33a79ffff 100644 --- a/techlibs/common/dff2ff.v +++ b/techlibs/common/dff2ff.v @@ -4,7 +4,9 @@ module dff2ff (CLK, D, Q); parameter CLK_POLARITY = 1; input CLK; + (* force_downto *) input [WIDTH-1:0] D; + (* force_downto *) output reg [WIDTH-1:0] Q; wire [1023:0] _TECHMAP_DO_ = "proc;;"; diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 4cabb4453..bec47d01f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -57,8 +57,11 @@ module _80_mul (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; parameter _TECHMAP_CELLTYPE_ = ""; @@ -119,13 +122,19 @@ module _80_mul (A, B, Y); localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH; if (A_SIGNED && B_SIGNED) begin + (* force_downto *) wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + (* force_downto *) wire signed [last_Y_WIDTH-1:0] last_partial; + (* force_downto *) wire signed [Y_WIDTH-1:0] partial_sum [n:0]; end else begin + (* force_downto *) wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + (* force_downto *) wire [last_Y_WIDTH-1:0] last_partial; + (* force_downto *) wire [Y_WIDTH-1:0] partial_sum [n:0]; end @@ -170,13 +179,19 @@ module _80_mul (A, B, Y); localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH; if (A_SIGNED && B_SIGNED) begin + (* force_downto *) wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + (* force_downto *) wire signed [last_Y_WIDTH-1:0] last_partial; + (* force_downto *) wire signed [Y_WIDTH-1:0] partial_sum [n:0]; end else begin + (* force_downto *) wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + (* force_downto *) wire [last_Y_WIDTH-1:0] last_partial; + (* force_downto *) wire [Y_WIDTH-1:0] partial_sum [n:0]; end @@ -249,8 +264,11 @@ module _90_soft_mul (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; // Indirection necessary since mapping diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 225cff449..c1efc378b 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -85,8 +85,11 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y); localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl"; localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr"; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH); @@ -96,6 +99,7 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y); wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;"; integer i; + (* force_downto *) reg [WIDTH-1:0] buffer; reg overflow; @@ -125,8 +129,11 @@ module _90_shift_shiftx (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; parameter _TECHMAP_CELLTYPE_ = ""; @@ -173,6 +180,7 @@ module _90_shift_shiftx (A, B, Y); wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;"; integer i; + (* force_downto *) reg [WIDTH-1:0] buffer; reg overflow; @@ -216,9 +224,12 @@ endmodule module _90_fa (A, B, C, X, Y); parameter WIDTH = 1; + (* force_downto *) input [WIDTH-1:0] A, B, C; + (* force_downto *) output [WIDTH-1:0] X, Y; + (* force_downto *) wire [WIDTH-1:0] t1, t2, t3; assign t1 = A ^ B, t2 = A & B, t3 = C & t1; @@ -229,12 +240,15 @@ endmodule module _90_lcu (P, G, CI, CO); parameter WIDTH = 2; + (* force_downto *) input [WIDTH-1:0] P, G; input CI; + (* force_downto *) output [WIDTH-1:0] CO; integer i, j; + (* force_downto *) reg [WIDTH-1:0] p, g; wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast"; @@ -278,38 +292,26 @@ module _90_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; - wire [Y_WIDTH-1:0] AA, BB; + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - if (A_WIDTH == 0) begin - wire [Y_WIDTH-1:0] B_buf; - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - assign AA = {Y_WIDTH{1'b0}}; - assign BB = BI ? ~B_buf : B_buf; - end - else if (B_WIDTH == 0) begin - wire [Y_WIDTH-1:0] A_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - - assign AA = A_buf; - assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}}; - end - else begin - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - assign AA = A_buf; - assign BB = BI ? ~B_buf : B_buf; - end + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO)); @@ -335,15 +337,19 @@ endmodule module \$__div_mod_u (A, B, Y, R); parameter WIDTH = 1; + (* force_downto *) input [WIDTH-1:0] A, B; + (* force_downto *) output [WIDTH-1:0] Y, R; + (* force_downto *) wire [WIDTH*WIDTH-1:0] chaindata; assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)]; genvar i; generate begin for (i = 0; i < WIDTH; i=i+1) begin:stage + (* force_downto *) wire [WIDTH-1:0] stage_in; if (i == 0) begin:cp @@ -369,14 +375,19 @@ module \$__div_mod (A, B, Y, R); A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH : B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y, R; + (* force_downto *) wire [WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u; assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf; assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf; @@ -402,8 +413,11 @@ module _90_div (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; \$__div_mod #( @@ -427,8 +441,11 @@ module _90_mod (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; \$__div_mod #( @@ -457,8 +474,11 @@ module _90_pow (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; wire _TECHMAP_FAIL_ = 1; @@ -474,20 +494,27 @@ module _90_pmux (A, B, S, Y); parameter WIDTH = 1; parameter S_WIDTH = 1; + (* force_downto *) input [WIDTH-1:0] A; + (* force_downto *) input [WIDTH*S_WIDTH-1:0] B; + (* force_downto *) input [S_WIDTH-1:0] S; + (* force_downto *) output [WIDTH-1:0] Y; + (* force_downto *) wire [WIDTH-1:0] Y_B; genvar i, j; generate + (* force_downto *) wire [WIDTH*S_WIDTH-1:0] B_AND_S; for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}}; end:B_AND for (i = 0; i < WIDTH; i = i + 1) begin:B_OR + (* force_downto *) wire [S_WIDTH-1:0] B_AND_BITS; for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i]; diff --git a/techlibs/coolrunner2/cells_counter_map.v b/techlibs/coolrunner2/cells_counter_map.v index b474fa522..f9c44c80f 100644 --- a/techlibs/coolrunner2/cells_counter_map.v +++ b/techlibs/coolrunner2/cells_counter_map.v @@ -3,6 +3,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); input wire CE; input wire CLK; output wire OUT; + (* force_downto *) output wire[WIDTH-1:0] POUT; input wire RST; input wire UP; diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 17bde0497..ffd42469c 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -26,15 +26,20 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); @@ -48,10 +53,15 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); localparam Y_WIDTH2 = round_up2(Y_WIDTH); + (* force_downto *) wire [Y_WIDTH2-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) wire [Y_WIDTH2-1:0] BX = B_buf; + (* force_downto *) wire [Y_WIDTH2-1:0] C = {CO, CI}; + (* force_downto *) wire [Y_WIDTH2-1:0] FCO, Y1; genvar i; diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index c031703a9..e19ac9ab9 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -70,6 +70,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 178f57bc5..4dac360b9 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -26,24 +26,33 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; wire CIx; + (* force_downto *) wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) wire [Y_WIDTH-1:0] C = { COx, CIx }; EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) @@ -76,4 +85,4 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); /* End implementation */ assign X = AA ^ BB; -endmodule \ No newline at end of file +endmodule diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v index 3ecec3bac..1090f8b27 100644 --- a/techlibs/efinix/cells_map.v +++ b/techlibs/efinix/cells_map.v @@ -34,6 +34,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index b6f9e8c38..42aaba870 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -26,21 +26,29 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = B_buf; + (* force_downto *) wire [Y_WIDTH-1:0] C = {CO, CI}; genvar i; diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index aee912256..b44350616 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -232,6 +232,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index 51c85183d..316be3f73 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -115,6 +115,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; @@ -150,6 +151,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); input wire CE; input wire CLK; output reg OUT; + (* force_downto *) output reg[WIDTH-1:0] POUT; input wire RST; input wire UP; diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index ed4140e44..3950e882b 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -25,21 +25,29 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) wire [Y_WIDTH-1:0] C = {CO, CI}; genvar i; diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index e9ccca239..7e5c07879 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -2,6 +2,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v index 89fb4561f..6a52a0f95 100644 --- a/techlibs/intel/arria10gx/cells_arith.v +++ b/techlibs/intel/arria10gx/cells_arith.v @@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v index 1430e8551..83f5881da 100644 --- a/techlibs/intel/arria10gx/cells_map.v +++ b/techlibs/intel/arria10gx/cells_map.v @@ -30,6 +30,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate diff --git a/techlibs/intel/cyclone10lp/cells_arith.v b/techlibs/intel/cyclone10lp/cells_arith.v index 5ae8d6cea..d8c46e865 100644 --- a/techlibs/intel/cyclone10lp/cells_arith.v +++ b/techlibs/intel/cyclone10lp/cells_arith.v @@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; diff --git a/techlibs/intel/cyclone10lp/cells_map.v b/techlibs/intel/cyclone10lp/cells_map.v index c2f6f403c..2a80ea678 100644 --- a/techlibs/intel/cyclone10lp/cells_map.v +++ b/techlibs/intel/cyclone10lp/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate diff --git a/techlibs/intel/cycloneiv/cells_arith.v b/techlibs/intel/cycloneiv/cells_arith.v index 010a4b5da..f7bc3cd65 100644 --- a/techlibs/intel/cycloneiv/cells_arith.v +++ b/techlibs/intel/cycloneiv/cells_arith.v @@ -70,8 +70,11 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -79,11 +82,14 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH < 6; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH:0] C = {CO, CI}; diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v index 191488430..9d8a5a2b7 100644 --- a/techlibs/intel/cycloneiv/cells_map.v +++ b/techlibs/intel/cycloneiv/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v index 49e36aa25..a755e10db 100644 --- a/techlibs/intel/cycloneive/arith_map.v +++ b/techlibs/intel/cycloneive/arith_map.v @@ -66,8 +66,11 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -75,11 +78,14 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH < 5; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH:0] C = {CO, CI}; diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v index abeb92eef..fead2837b 100644 --- a/techlibs/intel/cycloneive/cells_map.v +++ b/techlibs/intel/cycloneive/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v index 89fb4561f..6a52a0f95 100644 --- a/techlibs/intel/cyclonev/cells_arith.v +++ b/techlibs/intel/cyclonev/cells_arith.v @@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index f8d142bc9..eb4cd54d1 100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; wire VCC; diff --git a/techlibs/intel/max10/cells_arith.v b/techlibs/intel/max10/cells_arith.v index e2194cbd7..8529706a7 100644 --- a/techlibs/intel/max10/cells_arith.v +++ b/techlibs/intel/max10/cells_arith.v @@ -26,8 +26,11 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; @@ -36,11 +39,14 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v index 6d604e072..6a4072049 100644 --- a/techlibs/intel/max10/cells_map.v +++ b/techlibs/intel/max10/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate diff --git a/techlibs/intel_alm/common/alm_map.v b/techlibs/intel_alm/common/alm_map.v index fe646c5d6..6697b2e78 100644 --- a/techlibs/intel_alm/common/alm_map.v +++ b/techlibs/intel_alm/common/alm_map.v @@ -3,6 +3,7 @@ module \$lut (A, Y); parameter WIDTH = 1; parameter LUT = 0; +(* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/intel_alm/common/arith_alm_map.v b/techlibs/intel_alm/common/arith_alm_map.v index ddf81d9d0..8515eeb56 100644 --- a/techlibs/intel_alm/common/arith_alm_map.v +++ b/techlibs/intel_alm/common/arith_alm_map.v @@ -11,17 +11,24 @@ parameter Y_WIDTH = 1; parameter _TECHMAP_CONSTMSK_CI_ = 0; parameter _TECHMAP_CONSTVAL_CI_ = 0; +(* force_downto *) input [A_WIDTH-1:0] A; +(* force_downto *) input [B_WIDTH-1:0] B; input CI, BI; +(* force_downto *) output [Y_WIDTH-1:0] X, Y, CO; +(* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); +(* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; +(* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; +(* force_downto *) wire [Y_WIDTH-1:0] BX = B_buf; wire [Y_WIDTH:0] ALM_CARRY; diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v index 6ad7807d2..9fddc0f41 100644 --- a/techlibs/sf2/cells_map.v +++ b/techlibs/sf2/cells_map.v @@ -59,6 +59,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 2b8b0dcc1..2fc216908 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -24,9 +24,11 @@ module _80_xilinx_lcu (P, G, CI, CO); parameter WIDTH = 2; + (* force_downto *) input [WIDTH-1:0] P, G; input CI; + (* force_downto *) output [WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = WIDTH <= 2; @@ -41,7 +43,9 @@ module _80_xilinx_lcu (P, G, CI, CO); generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin + (* force_downto *) wire [WIDTH-1:0] C = {CO, CI}; + (* force_downto *) wire [WIDTH-1:0] S = P & ~G; generate for (i = 0; i < WIDTH; i = i + 1) begin:slice @@ -59,8 +63,11 @@ end else begin localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam PAD_WIDTH = MAX_WIDTH - WIDTH; + (* force_downto *) wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G}; + (* force_downto *) wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G}; + (* force_downto *) wire [MAX_WIDTH-1:0] C; assign CO = C; @@ -103,20 +110,27 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); parameter _TECHMAP_CONSTVAL_CI_ = 0; parameter _TECHMAP_CONSTMSK_CI_ = 0; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; + (* force_downto *) output [Y_WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; genvar i; @@ -129,7 +143,9 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); generate if (`LUT_SIZE == 4) begin + (* force_downto *) wire [Y_WIDTH-1:0] C = {CO, CI}; + (* force_downto *) wire [Y_WIDTH-1:0] S = {AA ^ BB}; genvar i; @@ -149,6 +165,7 @@ generate if (`LUT_SIZE == 4) begin end else if (EXPLICIT_CARRY) begin + (* force_downto *) wire [Y_WIDTH-1:0] S = AA ^ BB; wire CINIT; @@ -161,7 +178,9 @@ end else if (EXPLICIT_CARRY) begin // So we maintain two wire sets, CO_CHAIN is the carry that is for VPR, // e.g. off fabric dedicated chain. CO is the carry outputs that are // available to the fabric. + (* force_downto *) wire [Y_WIDTH-1:0] CO_CHAIN; + (* force_downto *) wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT}; // If carry chain is being initialized to a constant, techmap the constant @@ -250,10 +269,14 @@ end else begin localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH; + (* force_downto *) wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; + (* force_downto *) wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA}; + (* force_downto *) wire [MAX_WIDTH-1:0] O; + (* force_downto *) wire [MAX_WIDTH-1:0] C; assign Y = O, CO = C; diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index cc180f2b9..801949d22 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -184,8 +184,11 @@ module \$__XILINX_SHIFTX (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0; @@ -321,8 +324,11 @@ module _90__XILINX_SHIFTX (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v index ec2e3b234..2ab6075f1 100644 --- a/techlibs/xilinx/lut_map.v +++ b/techlibs/xilinx/lut_map.v @@ -26,6 +26,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v index 91aaf2118..bb31d21ec 100644 --- a/techlibs/xilinx/mux_map.v +++ b/techlibs/xilinx/mux_map.v @@ -30,8 +30,11 @@ module \$shiftx (A, B, Y); parameter B_WIDTH = 1; parameter Y_WIDTH = 1; + (* force_downto *) input [A_WIDTH-1:0] A; + (* force_downto *) input [B_WIDTH-1:0] B; + (* force_downto *) output [Y_WIDTH-1:0] Y; parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; -- cgit v1.2.3 From 76e0cc82768957bd1dd473c559ec88ee2bd4d7bb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 23 May 2020 08:17:40 -0700 Subject: ecp5: cleanup unused +/ecp5/abc9_model.v --- techlibs/ecp5/Makefile.inc | 1 - techlibs/ecp5/abc9_model.v | 12 ------------ techlibs/ecp5/synth_ecp5.cc | 1 - 3 files changed, 14 deletions(-) delete mode 100644 techlibs/ecp5/abc9_model.v (limited to 'techlibs') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 9a337b2b6..9d564c78c 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -23,7 +23,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v)) EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v deleted file mode 100644 index b7ecd7358..000000000 --- a/techlibs/ecp5/abc9_model.v +++ /dev/null @@ -1,12 +0,0 @@ -// --------------------------------------- - -(* abc9_box *) -module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO); - specify - ($DO => DO) = 0; - (RAD[0] *> DO) = 141; - (RAD[1] *> DO) = 379; - (RAD[2] *> DO) = 275; - (RAD[3] *> DO) = 379; - endspecify -endmodule diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index e5c1f7550..aceb36abc 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -334,7 +334,6 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)"); if (abc9) { - run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v"); std::string abc9_opts; if (nowidelut) abc9_opts += " -maxlut 4"; -- cgit v1.2.3 From 5b81df57c8c6779077c69ed8247fce7647616ade Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 May 2020 09:47:08 -0700 Subject: xilinx: tidy up cells_sim.v a little --- techlibs/xilinx/cells_sim.v | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d87cfe91b..f5850d8a2 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -3387,10 +3387,10 @@ module DSP48E1 ( reg signed [24:0] Dr; reg signed [17:0] Br1, Br2; reg signed [47:0] Cr; - reg [4:0] INMODEr = 5'b0; - reg [6:0] OPMODEr = 7'b0; - reg [3:0] ALUMODEr = 4'b0; - reg [2:0] CARRYINSELr = 3'b0; + reg [4:0] INMODEr; + reg [6:0] OPMODEr; + reg [3:0] ALUMODEr; + reg [2:0] CARRYINSELr; generate // Configurable A register @@ -3572,11 +3572,13 @@ module DSP48E1 ( // Carry in wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17]; - reg CARRYINr = 1'b0, A24_xnor_B17 = 1'b0; + reg CARRYINr, A24_xnor_B17; generate + if (CARRYINREG == 1) initial CARRYINr = 1'b0; if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end else always @* CARRYINr = CARRYIN; + if (MREG == 1) initial A24_xnor_B17 = 1'b0; if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end else always @* A24_xnor_B17 = A24_xnor_B17d; endgenerate -- cgit v1.2.3 From 17163cf43a6b6eec9aac44f6a4463dda54b8ed68 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 8 Apr 2020 19:30:47 +0200 Subject: Add flooring modulo operator The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. --- techlibs/common/simlib.v | 48 ++++++++++++++++++++++++++++ techlibs/common/techmap.v | 79 +++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 124 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2cdddeabb..57fc07caa 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1021,6 +1021,14 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $mod (A, B, Y) +//- +//- Modulo/remainder of division with truncated result (rounded towards 0). +//- +//- Invariant: $div(A, B) * B + $mod(A, B) == A +//- module \$mod (A, B, Y); parameter A_SIGNED = 0; @@ -1043,6 +1051,46 @@ endgenerate endmodule +// -------------------------------------------------------- + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $modfloor (A, B, Y) +//- +//- Modulo/remainder of division with floored result (rounded towards negative infinity). +//- +//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A +//- +module \$modfloor (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + +generate + if (A_SIGNED && B_SIGNED) begin:BLOCK1 + localparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH; + wire [WIDTH-1:0] B_buf, Y_trunc; + assign B_buf = $signed(B); + assign Y_trunc = $signed(A) % $signed(B); + // flooring mod is the same as truncating mod for positive division results (A and B have + // the same sign), as well as when there's no remainder. + // For all other cases, they behave as `floor - trunc = B` + assign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc); + end else begin:BLOCK2 + // no difference between truncating and flooring for unsigned + assign Y = A % B; + end +endgenerate + +endmodule + // -------------------------------------------------------- `ifndef SIMLIB_NOPOW diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index c1efc378b..95223180d 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -364,7 +364,8 @@ module \$__div_mod_u (A, B, Y, R); end endgenerate endmodule -module \$__div_mod (A, B, Y, R); +// truncating signed division/modulo +module \$__div_mod_trunc (A, B, Y, R); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -420,7 +421,7 @@ module _90_div (A, B, Y); (* force_downto *) output [Y_WIDTH-1:0] Y; - \$__div_mod #( + \$__div_mod_trunc #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -448,7 +449,79 @@ module _90_mod (A, B, Y); (* force_downto *) output [Y_WIDTH-1:0] Y; - \$__div_mod #( + \$__div_mod_trunc #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) div_mod ( + .A(A), + .B(B), + .R(Y) + ); +endmodule + +// flooring signed division/modulo +module \$__div_mod_floor (A, B, Y, R); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + localparam WIDTH = + A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH : + B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y, R; + + wire [WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s; + assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf; + assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf; + + \$__div_mod_u #( + .WIDTH(WIDTH) + ) div_mod_u ( + .A(A_buf_u), + .B(B_buf_u), + .Y(Y_u), + .R(R_u) + ); + + // For negative results, if there was a remainder, subtract one to turn + // the round towards 0 into a round towards -inf + assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u; + + // truncating modulo + assign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u; + // Flooring modulo differs from truncating modulo only if it is nonzero and + // A and B have different signs - then `floor - trunc = B` + assign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s; +endmodule + +(* techmap_celltype = "$modfloor" *) +module _90_modfloor (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] Y; + + \$__div_mod_floor #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), -- cgit v1.2.3 From edd8ff2c0778d97808869488cc7394151456c4ca Mon Sep 17 00:00:00 2001 From: Xiretza Date: Tue, 21 Apr 2020 12:51:58 +0200 Subject: Add flooring division operator The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. --- techlibs/common/simlib.v | 43 +++++++++++++++++++++++++++++++++++++++++++ techlibs/common/techmap.v | 28 ++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) (limited to 'techlibs') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 57fc07caa..125b8e013 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -997,6 +997,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $div (A, B, Y) +//- +//- Division with truncated result (rounded towards 0). +//- module \$div (A, B, Y); parameter A_SIGNED = 0; @@ -1053,6 +1059,43 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $divfloor (A, B, Y) +//- +//- Division with floored result (rounded towards negative infinity). +//- +module \$divfloor (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + +generate + if (A_SIGNED && B_SIGNED) begin:BLOCK1 + localparam WIDTH = + A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH : + B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH; + wire [WIDTH:0] A_buf, B_buf, N_buf; + assign A_buf = $signed(A); + assign B_buf = $signed(B); + assign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1)); + assign Y = $signed(N_buf) / $signed(B_buf); + end else begin:BLOCK2 + assign Y = A / B; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $modfloor (A, B, Y) diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 95223180d..eafe8d4da 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -506,6 +506,34 @@ module \$__div_mod_floor (A, B, Y, R); assign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s; endmodule +(* techmap_celltype = "$divfloor" *) +module _90_divfloor (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] Y; + + \$__div_mod_floor #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) div_mod ( + .A(A), + .B(B), + .Y(Y) + ); +endmodule + (* techmap_celltype = "$modfloor" *) module _90_modfloor (A, B, Y); parameter A_SIGNED = 0; -- cgit v1.2.3