From f1a206ba03c5b6fba2672754d09cc649a60beeb8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:17:14 -0700 Subject: Revert "Remove sequential extension" This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. --- techlibs/xilinx/abc_map.v | 97 ++++++++++++++++++++++++++++++++ techlibs/xilinx/abc_model.v | 89 ++++++++++++++++++++++++++++++ techlibs/xilinx/abc_unmap.v | 119 ++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/abc_xc7.box | 41 ++++++++++++++ techlibs/xilinx/cells_sim.v | 24 +++----- techlibs/xilinx/synth_xilinx.cc | 6 +- 6 files changed, 359 insertions(+), 17 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 121862692..a760b3d6d 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -20,6 +20,103 @@ // ============================================================================ +module FDRE (output reg Q, input C, CE, D, R); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + wire \$nextQ ; + \$__ABC_FDRE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_R_INVERTED), + .CLK_POLARITY(!IS_C_INVERTED), + .EN_POLARITY(1'b1) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); +endmodule +module FDRE_1 (output reg Q, input C, CE, D, R); + parameter [0:0] INIT = 1'b0; + wire \$nextQ ; + \$__ABC_FDRE_1 #( + .INIT(|0), + .CLK_POLARITY(1'b0), + .EN_POLARITY(1'b1) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); +endmodule + +module FDCE (output reg Q, input C, CE, D, CLR); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + wire \$nextQ , \$currQ ; + \$__ABC_FDCE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_CLR_INVERTED(IS_CLR_INVERTED), + .CLK_POLARITY(!IS_C_INVERTED), + .EN_POLARITY(1'b1) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); + \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q)); +endmodule +module FDCE_1 (output reg Q, input C, CE, D, CLR); + parameter [0:0] INIT = 1'b0; + wire \$nextQ , \$currQ ; + \$__ABC_FDCE_1 #( + .INIT(INIT), + .CLK_POLARITY(1'b0), + .EN_POLARITY(1'b1) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); + \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q)); +endmodule + +module FDPE (output reg Q, input C, CE, D, PRE); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + wire \$nextQ , \$currQ ; + \$__ABC_FDPE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_PRE_INVERTED(IS_PRE_INVERTED), + .CLK_POLARITY(!IS_C_INVERTED), + .EN_POLARITY(1'b1) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); + \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q)); +endmodule +module FDPE_1 (output reg Q, input C, CE, D, PRE); + parameter [0:0] INIT = 1'b0; + wire \$nextQ , \$currQ ; + \$__ABC_FDPE_1 #( + .INIT(INIT), + .CLK_POLARITY(1'b0), + .EN_POLARITY(1'b1) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); + \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q)); +endmodule + module RAM32X1D ( output DPO, SPO, input D, diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index e3e9686b5..7162bd213 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -26,6 +26,94 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule +module \$__ABC_FF_ (input C, D, output Q); +endmodule + +(* abc_box_id = 1000 *) +module \$__ABC_ASYNC (input A, S, output Y); +endmodule + +(* abc_box_id=1001, lib_whitebox, abc_flop *) +module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input R, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); +endmodule + +(* abc_box_id=1002, lib_whitebox, abc_flop *) +module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input R, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); +endmodule + +(* abc_box_id=1003, lib_whitebox, abc_flop *) +module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input CLR, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; +endmodule + +(* abc_box_id=1004, lib_whitebox, abc_flop *) +module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input CLR, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !CLR) ? D : \$pastQ ; +endmodule + +(* abc_box_id=1005, lib_whitebox, abc_flop *) +module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input PRE, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; +endmodule + +(* abc_box_id=1006, lib_whitebox, abc_flop *) +module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input PRE, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !PRE) ? D : \$pastQ ; +endmodule + (* abc_box_id=2000 *) module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y); endmodule @@ -33,6 +121,7 @@ endmodule module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y); endmodule + module \$__ABC_RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc_arrival=1153 *) output DPO, SPO, diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 779fc5aac..d00d27e2e 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -20,6 +20,125 @@ // ============================================================================ +module \$__ABC_ASYNC (input A, S, output Y); + assign Y = A; +endmodule + +module \$__ABC_FDRE (output Q, + input C, + input CE, + input D, + input R, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + + FDRE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_R_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .R(R) + ); +endmodule + +module \$__ABC_FDRE_1 (output Q, + input C, + input CE, + input D, + input R, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); + + FDRE_1 #( + .INIT(INIT), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .R(R) + ); +endmodule + +module \$__ABC_FDCE (output Q, + input C, + input CE, + input D, + input CLR, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + + FDCE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_CLR_INVERTED(IS_CLR_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) + ); +endmodule + +module \$__ABC_FDCE_1 (output Q, + input C, + input CE, + input D, + input CLR, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + + FDCE_1 #( + .INIT(INIT), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) + ); +endmodule + +module \$__ABC_FDPE (output Q, + input C, + input CE, + input D, + input PRE, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + + FDPE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_PRE_INVERTED(IS_PRE_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) + ); +endmodule + +module \$__ABC_FDPE_1 (output Q, + input C, + input CE, + input D, + input PRE, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + + FDPE_1 #( + .INIT(INIT), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) + ); +endmodule + module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y); assign Y = A; endmodule diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 61b89b8af..c08af6320 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -38,6 +38,47 @@ CARRY4 4 1 10 8 592 540 520 356 - 512 548 292 - 228 580 526 507 398 385 508 528 378 380 114 +# Box to emulate async behaviour of FD[CP]* +# Inputs: A S +# Outputs: Y +$__ABC_ASYNC 1000 0 2 1 +0 764 + +# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to +# reflect the -46ps Tsu +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 + +# Inputs: C CE D R \$pastQ +# Outputs: Q +FDRE 1001 1 5 1 +0 151 0 446 0 + +# Inputs: C CE D R \$pastQ +# Outputs: Q +FDRE_1 1002 1 5 1 +0 151 0 446 0 + +# Inputs: C CE CLR D \$pastQ +# Outputs: Q +FDCE 1003 1 5 1 +0 151 806 0 0 + +# Inputs: C CE CLR D \$pastQ +# Outputs: Q +FDCE_1 1004 1 5 1 +0 151 806 0 0 + +# Inputs: C CE D PRE \$pastQ +# Outputs: Q +FDPE 1005 1 5 1 +0 151 0 806 0 + +# Inputs: C CE D PRE \$pastQ +# Outputs: Q +FDPE_1 1006 1 5 1 +0 151 0 806 0 + # SLICEM/A6LUT # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} # Inputs: A S0 S1 S2 S3 S4 S5 diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d879a56ee..1ab718ccc 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -211,8 +211,7 @@ endmodule `endif -module FDRE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, R); +module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -224,8 +223,7 @@ module FDRE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDSE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, S); +module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -237,8 +235,7 @@ module FDSE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDCE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, CLR); +module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -252,8 +249,7 @@ module FDCE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDPE ((* abc_arrival=303 *) output reg Q, - input C, CE, D, PRE); +module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -267,29 +263,25 @@ module FDPE ((* abc_arrival=303 *) output reg Q, endcase endgenerate endmodule -module FDRE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, R); +module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; endmodule -module FDSE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, S); +module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; endmodule -module FDCE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, CLR); +module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule -module FDPE_1 ((* abc_arrival=303 *) output reg Q, - input C, CE, D, PRE); +module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b9c4df82f..d28cd2428 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -379,6 +379,8 @@ struct SynthXilinxPass : public ScriptPass std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v"; if (widemux > 0) techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); + if (abc9) + techmap_args += " -map +/xilinx/ff_map.v"; run("techmap " + techmap_args); run("clean"); } @@ -409,9 +411,11 @@ struct SynthXilinxPass : public ScriptPass // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"; + std::string techmap_args = "-map +/xilinx/lut_map.v"; if (abc9) techmap_args += " -map +/xilinx/abc_unmap.v"; + else + techmap_args += " -map +/xilinx/ff_map.v"; run("techmap " + techmap_args); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); -- cgit v1.2.3 From 79b6edb6397c530a7304eb4334f95324a4208aba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 28 Sep 2019 23:48:17 -0700 Subject: Big rework; flop info now mostly in cells_sim.v --- techlibs/xilinx/abc_map.v | 77 ++++++----- techlibs/xilinx/abc_model.v | 90 +----------- techlibs/xilinx/abc_unmap.v | 122 +---------------- techlibs/xilinx/abc_xc7.box | 22 ++- techlibs/xilinx/cells_sim.v | 294 +++++++++++++++++++++++++++++++++------- techlibs/xilinx/synth_xilinx.cc | 4 +- 6 files changed, 314 insertions(+), 295 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 9f96d16be..056f66bbb 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -26,27 +26,23 @@ module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; wire \$nextQ ; - \$__ABC_FDRE #( + FDRE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_R_INVERTED), - .CLK_POLARITY(!IS_C_INVERTED), - .EN_POLARITY(1'b1) + .IS_R_INVERTED(IS_R_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R) + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R) ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; wire \$nextQ ; - \$__ABC_FDRE_1 #( - .INIT(|0), - .CLK_POLARITY(1'b0), - .EN_POLARITY(1'b1) + FDRE_1 #( + .INIT(|0), ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R) + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R) ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); endmodule @@ -57,28 +53,24 @@ module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; wire \$nextQ , \$currQ ; - \$__ABC_FDCE #( + FDCE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), - .IS_CLR_INVERTED(IS_CLR_INVERTED), - .CLK_POLARITY(!IS_C_INVERTED), - .EN_POLARITY(1'b1) + .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR) ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); - \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q)); + \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; wire \$nextQ , \$currQ ; - \$__ABC_FDCE_1 #( - .INIT(INIT), - .CLK_POLARITY(1'b0), - .EN_POLARITY(1'b1) + FDCE_1 #( + .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR) ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q)); @@ -90,33 +82,56 @@ module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; wire \$nextQ , \$currQ ; - \$__ABC_FDPE #( + FDPE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), - .CLK_POLARITY(!IS_C_INVERTED), - .EN_POLARITY(1'b1) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE) ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); - \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q)); + \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; wire \$nextQ , \$currQ ; - \$__ABC_FDPE_1 #( - .INIT(INIT), - .CLK_POLARITY(1'b0), - .EN_POLARITY(1'b1) + FDPE_1 #( + .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE) ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q)); endmodule +module FDSE (output reg Q, input C, CE, D, S); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + wire \$nextQ ; + FDSE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); +endmodule +module FDSE_1 (output reg Q, input C, CE, D, S); + parameter [0:0] INIT = 1'b0; + wire \$nextQ ; + FDSE_1 #( + .INIT(|0), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S) + ); + \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); +endmodule + module RAM32X1D ( output DPO, SPO, input D, diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index d94ddb7e5..a2914464d 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -26,97 +26,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule -module \$__ABC_FF_ (input C, D, output Q); +module \$__ABC_FF_ (input D, output Q); endmodule (* abc_box_id = 1000 *) module \$__ABC_ASYNC (input A, S, output Y); endmodule - -(* abc_box_id=1001, lib_whitebox, abc_flop *) -module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input R, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); -endmodule - -(* abc_box_id=1002, lib_whitebox, abc_flop *) -module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input R, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); -endmodule - -(* abc_box_id=1003, lib_whitebox, abc_flop *) -module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input CLR, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; -endmodule - -(* abc_box_id=1004, lib_whitebox, abc_flop *) -module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input CLR, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !CLR) ? D : \$pastQ ; -endmodule - -(* abc_box_id=1005, lib_whitebox, abc_flop *) -module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input PRE, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; -endmodule - -(* abc_box_id=1006, lib_whitebox, abc_flop *) -module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input PRE, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !PRE) ? D : \$pastQ ; -endmodule - -(* abc_box_id=2000 *) -module \$__ABC_LUT6 (input A, input [5:0] S, output Y); -endmodule -(* abc_box_id=2001 *) -module \$__ABC_LUT7 (input A, input [6:0] S, output Y); -endmodule diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index c24571747..bf8253adb 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -24,124 +24,6 @@ module \$__ABC_ASYNC (input A, S, output Y); assign Y = A; endmodule -module \$__ABC_FDRE (output Q, - input C, - input CE, - input D, - input R, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - - FDRE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_R_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .R(R) - ); -endmodule - -module \$__ABC_FDRE_1 (output Q, - input C, - input CE, - input D, - input R, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); - - FDRE_1 #( - .INIT(INIT), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .R(R) - ); -endmodule - -module \$__ABC_FDCE (output Q, - input C, - input CE, - input D, - input CLR, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - - FDCE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_CLR_INVERTED(IS_CLR_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) - ); -endmodule - -module \$__ABC_FDCE_1 (output Q, - input C, - input CE, - input D, - input CLR, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - - FDCE_1 #( - .INIT(INIT), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) - ); -endmodule - -module \$__ABC_FDPE (output Q, - input C, - input CE, - input D, - input PRE, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - - FDPE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_PRE_INVERTED(IS_PRE_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) - ); -endmodule - -module \$__ABC_FDPE_1 (output Q, - input C, - input CE, - input D, - input PRE, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - - FDPE_1 #( - .INIT(INIT), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) - ); -endmodule - -module \$__ABC_LUT6 (input A, input [5:0] S, output Y); - assign Y = A; -endmodule -module \$__ABC_LUT7 (input A, input [6:0] S, output Y); - assign Y = A; +module \$__ABC_FF_ (input D, output Q); + assign Q = D; endmodule diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index aebb8b975..daaa4d16f 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -52,36 +52,46 @@ $__ABC_ASYNC 1000 0 2 1 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 -# Inputs: C CE D R \$pastQ +# Inputs: C CE D R \$currQ # Outputs: Q FDRE 1001 1 5 1 0 151 0 446 0 -# Inputs: C CE D R \$pastQ +# Inputs: C CE D R \$currQ # Outputs: Q FDRE_1 1002 1 5 1 0 151 0 446 0 -# Inputs: C CE CLR D \$pastQ +# Inputs: C CE CLR D \$currQ # Outputs: Q FDCE 1003 1 5 1 0 151 806 0 0 -# Inputs: C CE CLR D \$pastQ +# Inputs: C CE CLR D \$currQ # Outputs: Q FDCE_1 1004 1 5 1 0 151 806 0 0 -# Inputs: C CE D PRE \$pastQ +# Inputs: C CE D PRE \$currQ # Outputs: Q FDPE 1005 1 5 1 0 151 0 806 0 -# Inputs: C CE D PRE \$pastQ +# Inputs: C CE D PRE \$currQ # Outputs: Q FDPE_1 1006 1 5 1 0 151 0 806 0 +# Inputs: C CE D S \$currQ +# Outputs: Q +FDSE 1007 1 5 1 +0 151 0 446 0 + +# Inputs: C CE D S \$currQ +# Outputs: Q +FDSE_1 1008 1 5 1 +0 151 0 446 0 + # SLICEM/A6LUT # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} # Necessary since RAMD* and SRL* have both combinatorial (i.e. diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ef4340d10..ee9d48684 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -240,6 +240,7 @@ endmodule // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 +(* abc_box_id=1001, lib_whitebox, abc9_flop *) module FDRE ( (* abc_arrival=303 *) output reg Q, @@ -257,35 +258,72 @@ module FDRE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; + wire \$currQ ; + reg \$nextQ ; + always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b0: always @(posedge C) Q <= \$nextQ ; + 1'b1: always @(negedge C) Q <= \$nextQ ; endcase endgenerate +`endif endmodule -module FDSE ( +(* abc_box_id=1002, lib_whitebox, abc9_flop *) +module FDRE_1 ( (* abc_arrival=303 *) output reg Q, (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) input C, - input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, - (* invertible_pin = "IS_S_INVERTED" *) - input S + input CE, D, R ); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; + parameter [0:0] INIT = 1'b0; initial Q <= INIT; - generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase endgenerate + wire \$currQ ; + reg \$nextQ ; + always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; + always @(negedge C) Q <= \$nextQ ; +`endif endmodule +(* abc_box_id=1003, lib_whitebox, abc9_flop *) module FDCE ( (* abc_arrival=303 *) output reg Q, @@ -303,14 +341,78 @@ module FDCE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + // Since this is an async flop, async behaviour is also dealt with + // using the $_ABC_ASYNC box by abc_map.v + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) - 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; endcase endgenerate +`endif endmodule +(* abc_box_id=1004, lib_whitebox, abc9_flop *) +module FDCE_1 ( + (* abc_arrival=303 *) + output reg Q, + (* clkbuf_sink *) + input C, + input CE, D, CLR +); + parameter [0:0] INIT = 1'b0; + initial Q <= INIT; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + // Since this is an async flop, async behaviour is also dealt with + // using the $_ABC_ASYNC box by abc_map.v + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; + always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ; +`endif +endmodule + +(* abc_box_id=1005, lib_whitebox, abc9_flop *) module FDPE ( (* abc_arrival=303 *) output reg Q, @@ -328,60 +430,158 @@ module FDPE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + // Since this is an async flop, async behaviour is also dealt with + // using the $_ABC_ASYNC box by abc_map.v + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) - 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; endcase endgenerate +`endif endmodule -module FDRE_1 ( - (* abc_arrival=303 *) - output reg Q, - (* clkbuf_sink *) - input C, - input CE, D, R -); - parameter [0:0] INIT = 1'b0; - initial Q <= INIT; - always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; -endmodule - -module FDSE_1 ( +(* abc_box_id=1006, lib_whitebox, abc9_flop *) +module FDPE_1 ( (* abc_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, - input CE, D, S + input CE, D, PRE ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + // Since this is an async flop, async behaviour is also dealt with + // using the $_ABC_ASYNC box by abc_map.v + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; + always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ; +`endif endmodule -module FDCE_1 ( +(* abc_box_id=1007, lib_whitebox, abc9_flop *) +module FDSE ( (* abc_arrival=303 *) output reg Q, (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) input C, - input CE, D, CLR + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_S_INVERTED" *) + input S ); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; - always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; + wire \$currQ ; + reg \$nextQ ; + always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; + generate case (|IS_C_INVERTED) + 1'b0: always @(posedge C) Q <= \$nextQ ; + 1'b1: always @(negedge C) Q <= \$nextQ ; + endcase endgenerate +`endif endmodule -module FDPE_1 ( +(* abc_box_id=1008, lib_whitebox, abc9_flop *) +module FDSE_1 ( (* abc_arrival=303 *) output reg Q, (* clkbuf_sink *) input C, - input CE, D, PRE + input CE, D, S ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; + wire \$currQ ; + reg \$nextQ ; + always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ; +`ifdef _ABC + // `abc9' requires that complex flops be split into a combinatorial + // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `\$currQ' wire. + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + always @* Q = \$nextQ ; +`else + assign \$currQ = Q; + always @(negedge C) Q <= \$nextQ ; +`endif endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 888b5ed7b..f5143ca82 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -276,9 +276,9 @@ struct SynthXilinxPass : public ScriptPass if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); if (help_mode) run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); -- cgit v1.2.3 From 18ebb86edbade4a94833dead59d69fddd980f5bd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 29 Sep 2019 11:25:34 -0700 Subject: FDCE_1 does not have IS_CLR_INVERTED --- techlibs/xilinx/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ee9d48684..cf39bd45b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -408,7 +408,7 @@ module FDCE_1 ( always @* Q = \$nextQ ; `else assign \$currQ = Q; - always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ; + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; `endif endmodule -- cgit v1.2.3 From f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 29 Sep 2019 21:55:53 -0700 Subject: Missing endmodule --- techlibs/xilinx/abc_model.v | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index b302e46f6..8255804c2 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -35,6 +35,7 @@ endmodule (* abc_box_id = 1000 *) module \$__ABC_ASYNC (input A, S, output Y); +endmodule // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} // Necessary since RAMD* and SRL* have both combinatorial (i.e. -- cgit v1.2.3 From 5e9ae90cbba4e9c2abfe5d6a1b90c2256aae1615 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:39:24 -0700 Subject: Add explanation to abc_map.v --- techlibs/xilinx/abc_map.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index cb252b828..6a0e18abe 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -18,8 +18,24 @@ * */ +// The following techmapping rules are intended to be run (with -max_iter 1) +// before invoking the `abc9` pass in order to transform the design into +// a format that it understands. +// +// For example, (complex) flip-flops are expected to be described as an +// combinatorial box (containing all control logic such as clock enable +// or synchronous resets) followed by a basic D-Q flop. + // ============================================================================ +// The purpose of the following FD* rules are to wrap the flop (which, when +// called with the `_ABC' macro set captures contains only its combinatorial +// behaviour) with: +// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9 +// the location of its basic D-Q flop +// (b) a special \$currQ connection that feeds back into the (combinatorial) +// FD* cell to facilitate clock-enable behaviour -- note that \$currQ +// isn't a real input port, it is one that is understood only by abc9 module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; -- cgit v1.2.3 From e529872b0170ba269db2d00c96108c86b260e864 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 16:33:40 -0700 Subject: Remove need for $currQ port connection --- techlibs/xilinx/abc_map.v | 69 ++++++++++--------- techlibs/xilinx/cells_sim.v | 160 ++++++++++++++++++++++---------------------- 2 files changed, 118 insertions(+), 111 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 6a0e18abe..4eec77df9 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -33,34 +33,35 @@ // behaviour) with: // (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9 // the location of its basic D-Q flop -// (b) a special \$currQ connection that feeds back into the (combinatorial) -// FD* cell to facilitate clock-enable behaviour -- note that \$currQ -// isn't a real input port, it is one that is understood only by abc9 +// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback +// into the (combinatorial) FD* cell to facilitate clock-enable behaviour module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; - wire \$nextQ ; + wire $nextQ; FDRE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_R_INVERTED(IS_R_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R) + .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; - wire \$nextQ ; + wire $nextQ; FDRE_1 #( .INIT(|0), ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R) + .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDCE (output reg Q, input C, CE, D, CLR); @@ -68,28 +69,30 @@ module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire \$nextQ , \$currQ ; + wire $currQ, $nextQ; FDCE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); - \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; - wire \$nextQ , \$currQ ; + wire $nextQ, $currQ; FDCE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); - \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); endmodule module FDPE (output reg Q, input C, CE, D, PRE); @@ -97,28 +100,30 @@ module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire \$nextQ , \$currQ ; + wire $nextQ, $currQ; FDPE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); - \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; - wire \$nextQ , \$currQ ; + wire $nextQ, $currQ; FDPE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); - \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); endmodule module FDSE (output reg Q, input C, CE, D, S); @@ -126,26 +131,28 @@ module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; - wire \$nextQ ; + wire $nextQ; FDSE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_S_INVERTED(IS_S_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S) + .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; - wire \$nextQ ; + wire $nextQ; FDSE_1 #( .INIT(|0), ) _TECHMAP_REPLACE_ ( - .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S) + .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); - \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); + wire _TECHMAP_REPLACE_.$currQ = Q; + \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3aa686e81..7ab28b0aa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -258,31 +258,31 @@ module FDRE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; + always @* Q = $nextQ; `else - assign \$currQ = Q; + assign $currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) Q <= \$nextQ ; - 1'b1: always @(negedge C) Q <= \$nextQ ; + 1'b0: always @(posedge C) Q <= $nextQ; + 1'b1: always @(negedge C) Q <= $nextQ; endcase endgenerate `endif endmodule @@ -297,29 +297,29 @@ module FDRE_1 ( ); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + always @* Q = $nextQ; `else - assign \$currQ = Q; - always @(negedge C) Q <= \$nextQ ; + assign $currQ = Q; + always @(negedge C) Q <= $nextQ; `endif endmodule @@ -341,15 +341,15 @@ module FDCE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with // using the $_ABC_ASYNC box by abc_map.v @@ -357,19 +357,19 @@ module FDCE ( // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + always @* Q = $nextQ; `else - assign \$currQ = Q; + assign $currQ = Q; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) - 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; - 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; - 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; - 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ; + 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ; + 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ; + 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ; endcase endgenerate `endif endmodule @@ -384,15 +384,15 @@ module FDCE_1 ( ); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (CE) Q <= D; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with // using the $_ABC_ASYNC box by abc_map.v @@ -400,15 +400,15 @@ module FDCE_1 ( // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + always @* Q = $nextQ; `else - assign \$currQ = Q; - always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; + assign $currQ = Q; + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ; `endif endmodule @@ -430,15 +430,15 @@ module FDPE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with // using the $_ABC_ASYNC box by abc_map.v @@ -446,19 +446,19 @@ module FDPE ( // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + always @* Q = $nextQ; `else - assign \$currQ = Q; + assign $currQ = Q; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) - 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; - 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; - 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; - 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ; endcase endgenerate `endif endmodule @@ -473,15 +473,15 @@ module FDPE_1 ( ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (CE) Q <= D; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Since this is an async flop, async behaviour is also dealt with // using the $_ABC_ASYNC box by abc_map.v @@ -489,15 +489,15 @@ module FDPE_1 ( // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + always @* Q = $nextQ; `else - assign \$currQ = Q; - always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ; + assign $currQ = Q; + always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ; `endif endmodule @@ -519,31 +519,31 @@ module FDSE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, IS_C_INVERTED}; + wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; + always @* Q = $nextQ; `else - assign \$currQ = Q; + assign $currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) Q <= \$nextQ ; - 1'b1: always @(negedge C) Q <= \$nextQ ; + 1'b0: always @(posedge C) Q <= $nextQ; + 1'b1: always @(negedge C) Q <= $nextQ; endcase endgenerate `endif endmodule @@ -558,29 +558,29 @@ module FDSE_1 ( ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ; + wire $currQ; + reg $nextQ; + always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // In order to achieve clock-enable behaviour, the current value // of the sequential output is required which Yosys will - // connect to the special `\$currQ' wire. + // connect to the special `$currQ' wire. // Special signal indicating clock domain // (used to partition the module so that `abc9' only performs // sequential synthesis (reachability analysis) correctly on // one domain at a time) - wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; // Special signal indicating control domain // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) - wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; - always @* Q = \$nextQ ; + wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + always @* Q = $nextQ; `else - assign \$currQ = Q; - always @(negedge C) Q <= \$nextQ ; + assign $currQ = Q; + always @(negedge C) Q <= $nextQ; `endif endmodule -- cgit v1.2.3 From 03ebe43e3edce03d3dc24f80c05e16cdb7b76748 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 1 Oct 2019 13:05:56 -0700 Subject: Escape Verilog identifiers for legality outside of Yosys --- techlibs/xilinx/cells_sim.v | 96 ++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 48 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 7ab28b0aa..84139cd9c 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -258,9 +258,9 @@ module FDRE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -277,12 +277,12 @@ module FDRE ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) Q <= $nextQ; - 1'b1: always @(negedge C) Q <= $nextQ; + 1'b0: always @(posedge C) Q <= \$nextQ ; + 1'b1: always @(negedge C) Q <= \$nextQ ; endcase endgenerate `endif endmodule @@ -297,9 +297,9 @@ module FDRE_1 ( ); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -316,10 +316,10 @@ module FDRE_1 ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; - always @(negedge C) Q <= $nextQ; + always @(negedge C) Q <= \$nextQ ; `endif endmodule @@ -341,9 +341,9 @@ module FDCE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -362,14 +362,14 @@ module FDCE ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) - 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ; - 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ; - 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ; - 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ; + 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; endcase endgenerate `endif endmodule @@ -384,9 +384,9 @@ module FDCE_1 ( ); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (CE) Q <= D; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -405,10 +405,10 @@ module FDCE_1 ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; - always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ; + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; `endif endmodule @@ -430,9 +430,9 @@ module FDPE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -451,14 +451,14 @@ module FDPE ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) - 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ; - 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ; - 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ; - 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ; + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; endcase endgenerate `endif endmodule @@ -473,9 +473,9 @@ module FDPE_1 ( ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (CE) Q <= D; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (CE) Q <= D; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -494,10 +494,10 @@ module FDPE_1 ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; - always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ; + always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ; `endif endmodule @@ -519,9 +519,9 @@ module FDSE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -538,12 +538,12 @@ module FDSE ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) Q <= $nextQ; - 1'b1: always @(negedge C) Q <= $nextQ; + 1'b0: always @(posedge C) Q <= \$nextQ ; + 1'b1: always @(negedge C) Q <= \$nextQ ; endcase endgenerate `endif endmodule @@ -558,9 +558,9 @@ module FDSE_1 ( ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - wire $currQ; - reg $nextQ; - always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ; + wire \$currQ ; + reg \$nextQ ; + always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -577,10 +577,10 @@ module FDSE_1 ( // (which, combined with this spell type, encodes to `abc9' // which flops may be merged together) wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; - always @* Q = $nextQ; + always @* Q = \$nextQ ; `else assign $currQ = Q; - always @(negedge C) Q <= $nextQ; + always @(negedge C) Q <= \$nextQ ; `endif endmodule -- cgit v1.2.3 From 5299884f049e73c395fdff090b345b15d54aab1e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 1 Oct 2019 13:41:08 -0700 Subject: More fixes --- techlibs/xilinx/cells_sim.v | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 84139cd9c..04aa60f91 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -260,7 +260,7 @@ module FDRE ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ; + always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -279,7 +279,7 @@ module FDRE ( wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) Q <= \$nextQ ; 1'b1: always @(negedge C) Q <= \$nextQ ; @@ -299,7 +299,7 @@ module FDRE_1 ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = \$currQ ; + always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -318,7 +318,7 @@ module FDRE_1 ( wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; always @(negedge C) Q <= \$nextQ ; `endif endmodule @@ -343,7 +343,7 @@ module FDCE ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -364,7 +364,7 @@ module FDCE ( wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; @@ -386,7 +386,7 @@ module FDCE_1 ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (CE) Q <= D; else $nextQ = \$currQ ; + always @* if (CE) Q <= D; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -407,7 +407,7 @@ module FDCE_1 ( wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; `endif endmodule @@ -432,7 +432,7 @@ module FDPE ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ; + always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -453,7 +453,7 @@ module FDPE ( wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; @@ -475,7 +475,7 @@ module FDPE_1 ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (CE) Q <= D; else $nextQ = \$currQ ; + always @* if (CE) Q <= D; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -496,7 +496,7 @@ module FDPE_1 ( wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ; `endif endmodule @@ -521,7 +521,7 @@ module FDSE ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ; + always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -540,7 +540,7 @@ module FDSE ( wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) Q <= \$nextQ ; 1'b1: always @(negedge C) Q <= \$nextQ ; @@ -560,7 +560,7 @@ module FDSE_1 ( initial Q <= INIT; wire \$currQ ; reg \$nextQ ; - always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = \$currQ ; + always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ; `ifdef _ABC // `abc9' requires that complex flops be split into a combinatorial // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) @@ -579,7 +579,7 @@ module FDSE_1 ( wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; always @* Q = \$nextQ ; `else - assign $currQ = Q; + assign \$currQ = Q; always @(negedge C) Q <= \$nextQ ; `endif endmodule -- cgit v1.2.3 From 655f1b2ac559f73a7d781ae25afd1ab3b898afc0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:11:25 -0700 Subject: English --- techlibs/xilinx/abc_map.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 4eec77df9..db996fbc3 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -29,11 +29,11 @@ // ============================================================================ // The purpose of the following FD* rules are to wrap the flop (which, when -// called with the `_ABC' macro set captures contains only its combinatorial +// called with the `_ABC' macro set captures only its combinatorial // behaviour) with: // (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9 -// the location of its basic D-Q flop -// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback +// the connectivity of its basic D-Q flop +// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; -- cgit v1.2.3 From 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:21:14 -0700 Subject: Fix merge issues --- techlibs/xilinx/abc9_map.v | 18 +++++++++--------- techlibs/xilinx/abc9_unmap.v | 1 + 2 files changed, 10 insertions(+), 9 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 0b81be15f..05063f86d 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -31,7 +31,7 @@ // The purpose of the following FD* rules are to wrap the flop (which, when // called with the `_ABC' macro set captures only its combinatorial // behaviour) with: -// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9 +// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop // (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour @@ -50,7 +50,7 @@ module FDRE (output reg Q, input C, CE, D, R); .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -61,7 +61,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDCE (output reg Q, input C, CE, D, CLR); @@ -79,7 +79,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); @@ -91,7 +91,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); endmodule @@ -110,7 +110,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); @@ -122,7 +122,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); endmodule @@ -141,7 +141,7 @@ module FDSE (output reg Q, input C, CE, D, S); .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; @@ -152,7 +152,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index f97b0bc66..21fe78d08 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -26,6 +26,7 @@ endmodule module \$__ABC9_FF_ (input D, output Q); assign Q = D; +endmodule module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); assign Y = A; -- cgit v1.2.3 From d4212d128b5985cf09f5e7f14bc06e7323e644ac Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:27:05 -0700 Subject: Use read_args for read_verilog --- techlibs/xilinx/synth_xilinx.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 16b607aac..caeeb3266 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,10 +283,13 @@ struct SynthXilinxPass : public ScriptPass ff_map_file = "+/xilinx/xc7_ff_map.v"; if (check_label("begin")) { + std::string read_args; if (vpr) - run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); - else - run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); + read_args += " -D_EXPLICIT_CARRY"; + if (abc9) + read_args += " -D_ABC9"; + read_args += " -lib +/xilinx/cells_sim.v"; + run("read_verilog" + read_args); if (help_mode) run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); -- cgit v1.2.3 From a2ef93f03a1f75c25329c66d0e7d69da71e88e1f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:56:38 -0700 Subject: abc -> abc9 --- techlibs/xilinx/synth_xilinx.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c598acf2..07f3d9a8a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); - std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; + std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); abc9_opts += " -nomfs"; if (nowidelut) - abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; + abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else - abc9_opts += " -lut +/xilinx/abc_xc7.lut"; + abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); } else { -- cgit v1.2.3 From 3879ca13983a6e3f7d4653b1d80dacd14fbe82df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 22:55:18 -0700 Subject: Do not require changes to cells_sim.v; try and work out comb model --- techlibs/xilinx/abc9_map.v | 199 ++++++++++++++++++++++++++++++++++---- techlibs/xilinx/abc9_model.v | 5 +- techlibs/xilinx/abc9_xc7.box | 2 +- techlibs/xilinx/cells_sim.v | 224 ++++--------------------------------------- 4 files changed, 200 insertions(+), 230 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 05063f86d..ef7a1a09f 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -49,8 +49,57 @@ module FDRE (output reg Q, input C, CE, D, R); ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - wire _TECHMAP_REPLACE_.$currQ = Q; + // `abc9' requires that complex flops be split into a combinatorial box + // feeding a simple flop ($_ABC9_FF_). + // Yosys will automatically analyse the simulation model (described in + // cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in + // order to extract the combinatorial control logic left behind. + // Specifically, a simulation model similar to the one below: + // + // ++===================================++ + // || Sim model || + // || /\/\/\/\ || + // D -->>-----< > +------+ || + // R -->>-----< Comb. > |$_DFF_| || + // CE -->>-----< logic >-----| [NP]_|---+---->>-- Q + // || +--< > +------+ | || + // || | \/\/\/\/ | || + // || | | || + // || +----------------------------+ || + // || || + // ++===================================++ + // + // is transformed into: + // + // ++==================++ + // || Comb box || + // || || + // || /\/\/\/\ || + // D -->>-----< > || +------+ + // R -->>-----< Comb. > || |$_ABC_| + // CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q + // $currQ +-->>-----< > || +------+ | + // | || \/\/\/\/ || | + // | || || | + // | ++==================++ | + // | | + // +----------------------------------------------+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this cell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = Q; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -60,8 +109,22 @@ module FDRE_1 (output reg Q, input C, CE, D, R); ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = Q; endmodule module FDCE (output reg Q, input C, CE, D, CLR); @@ -69,18 +132,38 @@ module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire $currQ, $nextQ; + wire $nextQ, $currQ; FDCE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(IS_CLR_INVERTED) + // ^^^ Note that async + // control is disabled + // and captured by + // $__ABC9_ASYNC below ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); + // Since this is an async flop, async behaviour is also dealt with + // using the $_ABC9_ASYNC box by abc9_map.v + \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; @@ -88,11 +171,29 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); FDCE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0) + // ^^^ Note that async + // control is disabled + // and captured by + // $__ABC9_ASYNC below ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule module FDPE (output reg Q, input C, CE, D, PRE); @@ -107,11 +208,29 @@ module FDPE (output reg Q, input C, CE, D, PRE); .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED) + // ^^^ Note that async + // control is disabled + // and captured by + // $__ABC9_ASYNC below ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; @@ -119,11 +238,29 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); FDPE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0) + // ^^^ Note that async + // control is disabled + // and captured by + // $__ABC9_ASYNC below ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule module FDSE (output reg Q, input C, CE, D, S); @@ -140,8 +277,22 @@ module FDSE (output reg Q, input C, CE, D, S); ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; @@ -151,8 +302,22 @@ module FDSE_1 (output reg Q, input C, CE, D, S); ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); - wire _TECHMAP_REPLACE_.$currQ = Q; \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + + // Special signal indicating clock domain + // (used to partition the module so that `abc9' only performs + // sequential synthesis (reachability analysis) correctly on + // one domain at a time) + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + // Special signal indicating control domain + // (which, combined with this spell type, encodes to `abc9' + // which flops may be merged together) + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + // Special signal indicating the current value of the flip-flop + // In order to achieve clock-enable behaviour, the current value + // of the sequential output is required which Yosys will + // connect to the special `$currQ' wire. + wire _TECHMAP_REPLACE_.$currQ = Q; endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 74b5cf66a..c17d6744a 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -30,11 +30,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule -module \$__ABC_FF_ (input D, output Q); -endmodule - (* abc_box_id = 1000 *) -module \$__ABC_ASYNC (input A, S, output Y); +module \$__ABC9_ASYNC (input A, S, output Y); endmodule // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 6814b101f..24b1898a4 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -44,7 +44,7 @@ CARRY4 4 1 10 8 # Box to emulate async behaviour of FD[CP]* # Inputs: A S # Outputs: Y -$__ABC_ASYNC 1000 0 2 1 +$__ABC9_ASYNC 1000 0 2 1 0 764 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 309ee500a..35d9aac96 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -258,33 +258,10 @@ module FDRE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) Q <= \$nextQ ; - 1'b1: always @(negedge C) Q <= \$nextQ ; + 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`endif endmodule (* abc9_box_id=1002, lib_whitebox, abc9_flop *) @@ -297,30 +274,7 @@ module FDRE_1 ( ); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; - always @(negedge C) Q <= \$nextQ ; -`endif + always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; endmodule (* abc9_box_id=1003, lib_whitebox, abc9_flop *) @@ -341,37 +295,12 @@ module FDCE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC9_ASYNC box by abc9_map.v - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) - 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; - 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; - 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ; - 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ; + 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`endif endmodule (* abc9_box_id=1004, lib_whitebox, abc9_flop *) @@ -384,32 +313,7 @@ module FDCE_1 ( ); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC9_ASYNC box by abc9_map.v - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; - always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ; -`endif + always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule (* abc9_box_id=1005, lib_whitebox, abc9_flop *) @@ -430,37 +334,12 @@ module FDPE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC9_ASYNC box by abc9_map.v - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) - 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; - 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; - 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ; - 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ; + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ; endcase endgenerate -`endif endmodule (* abc9_box_id=1006, lib_whitebox, abc9_flop *) @@ -473,32 +352,7 @@ module FDPE_1 ( ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (CE) Q <= D; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC9_ASYNC box by abc9_map.v - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; - always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ; -`endif + always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule (* abc9_box_id=1007, lib_whitebox, abc9_flop *) @@ -519,33 +373,10 @@ module FDSE ( parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) Q <= \$nextQ ; - 1'b1: always @(negedge C) Q <= \$nextQ ; + 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`endif endmodule (* abc9_box_id=1008, lib_whitebox, abc9_flop *) @@ -558,30 +389,7 @@ module FDSE_1 ( ); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - wire \$currQ ; - reg \$nextQ ; - always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ; -`ifdef _ABC9 - // `abc9' requires that complex flops be split into a combinatorial - // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v) - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. - - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) - wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) - wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; - always @* Q = \$nextQ ; -`else - assign \$currQ = Q; - always @(negedge C) Q <= \$nextQ ; -`endif + always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; endmodule module LDCE ( -- cgit v1.2.3 From 1dc22607c38486d9e1a2b56f749d1eca35d405d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 7 Oct 2019 12:21:52 -0700 Subject: Remove -D_ABC9 --- techlibs/xilinx/synth_xilinx.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 07f3d9a8a..a99aef7c7 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,8 +286,6 @@ struct SynthXilinxPass : public ScriptPass std::string read_args; if (vpr) read_args += " -D_EXPLICIT_CARRY"; - if (abc9) - read_args += " -D_ABC9"; read_args += " -lib +/xilinx/cells_sim.v"; run("read_verilog" + read_args); -- cgit v1.2.3 From bae3d8705d844912699b0ed502630040ce4efa85 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 7 Oct 2019 12:54:45 -0700 Subject: Update comments in abc9_map.v --- techlibs/xilinx/abc9_map.v | 188 ++++++++++++++------------------------------- 1 file changed, 57 insertions(+), 131 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index ef7a1a09f..feaf979ad 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -28,12 +28,53 @@ // ============================================================================ -// The purpose of the following FD* rules are to wrap the flop (which, when -// called with the `_ABC' macro set captures only its combinatorial -// behaviour) with: +// `abc9' requires that complex flops be split into a combinatorial box +// feeding a simple flop ($_ABC9_FF_). +// Yosys will automatically analyse the simulation model (described in +// cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in +// order to extract the combinatorial control logic left behind. +// Specifically, a simulation model similar to the one below: +// +// ++===================================++ +// || Sim model || +// || /\/\/\/\ || +// D -->>-----< > +------+ || +// R -->>-----< Comb. > |$_DFF_| || +// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q +// || +--< > +------+ | || +// || | \/\/\/\/ | || +// || | | || +// || +----------------------------+ || +// || || +// ++===================================++ +// +// is transformed into: +// +// ++==================++ +// || Comb box || +// || || +// || /\/\/\/\ || +// D -->>-----< > || +------+ +// R -->>-----< Comb. > || |$_ABC_| +// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q +// $currQ +-->>-----< > || +------+ | +// | || \/\/\/\/ || | +// | || || | +// | ++==================++ | +// | | +// +----------------------------------------------+ +// +// The purpose of the following FD* rules are to wrap the flop with: // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop -// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback +// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock +// domain (used when partitioning the module so that `abc9' only +// performs sequential synthesis (with reachability analysis) correctly on +// one domain at a time) +// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control +// domain (which, combined with this cell type, encodes to `abc9' which +// flops may be merged together) +// (d) a special _TECHMAP_REPLACE_.$currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -49,56 +90,11 @@ module FDRE (output reg Q, input C, CE, D, R); ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - // `abc9' requires that complex flops be split into a combinatorial box - // feeding a simple flop ($_ABC9_FF_). - // Yosys will automatically analyse the simulation model (described in - // cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in - // order to extract the combinatorial control logic left behind. - // Specifically, a simulation model similar to the one below: - // - // ++===================================++ - // || Sim model || - // || /\/\/\/\ || - // D -->>-----< > +------+ || - // R -->>-----< Comb. > |$_DFF_| || - // CE -->>-----< logic >-----| [NP]_|---+---->>-- Q - // || +--< > +------+ | || - // || | \/\/\/\/ | || - // || | | || - // || +----------------------------+ || - // || || - // ++===================================++ - // - // is transformed into: - // - // ++==================++ - // || Comb box || - // || || - // || /\/\/\/\ || - // D -->>-----< > || +------+ - // R -->>-----< Comb. > || |$_ABC_| - // CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q - // $currQ +-->>-----< > || +------+ | - // | || \/\/\/\/ || | - // | || || | - // | ++==================++ | - // | | - // +----------------------------------------------+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this cell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = Q; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); @@ -111,19 +107,9 @@ module FDRE_1 (output reg Q, input C, CE, D, R); ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = Q; endmodule @@ -142,7 +128,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(IS_CLR_INVERTED) // ^^^ Note that async // control is disabled - // and captured by + // here but captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); @@ -150,19 +136,9 @@ module FDCE (output reg Q, input C, CE, D, CLR); // using the $_ABC9_ASYNC box by abc9_map.v \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); @@ -174,25 +150,15 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0) // ^^^ Note that async // control is disabled - // and captured by + // here but captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule @@ -211,25 +177,15 @@ module FDPE (output reg Q, input C, CE, D, PRE); .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED) // ^^^ Note that async // control is disabled - // and captured by + // here but captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); @@ -241,25 +197,15 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0) // ^^^ Note that async // control is disabled - // and captured by + // here but captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = $currQ; endmodule @@ -279,19 +225,9 @@ module FDSE (output reg Q, input C, CE, D, S); ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); @@ -304,19 +240,9 @@ module FDSE_1 (output reg Q, input C, CE, D, S); ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); - // Special signal indicating clock domain - // (used to partition the module so that `abc9' only performs - // sequential synthesis (reachability analysis) correctly on - // one domain at a time) + // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - // Special signal indicating control domain - // (which, combined with this spell type, encodes to `abc9' - // which flops may be merged together) wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; - // Special signal indicating the current value of the flip-flop - // In order to achieve clock-enable behaviour, the current value - // of the sequential output is required which Yosys will - // connect to the special `$currQ' wire. wire _TECHMAP_REPLACE_.$currQ = Q; endmodule -- cgit v1.2.3 From b2e34f932ac37e66435d413ab7a9f0074dc0343f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 7 Oct 2019 15:31:43 -0700 Subject: Rename $currQ to $abc9_currQ --- techlibs/xilinx/abc9_map.v | 92 +++++++++++++++++++++++----------------------- 1 file changed, 46 insertions(+), 46 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index feaf979ad..ee319a8e3 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -35,34 +35,34 @@ // order to extract the combinatorial control logic left behind. // Specifically, a simulation model similar to the one below: // -// ++===================================++ -// || Sim model || -// || /\/\/\/\ || -// D -->>-----< > +------+ || -// R -->>-----< Comb. > |$_DFF_| || -// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q -// || +--< > +------+ | || -// || | \/\/\/\/ | || -// || | | || -// || +----------------------------+ || -// || || -// ++===================================++ +// ++===================================++ +// || Sim model || +// || /\/\/\/\ || +// D -->>-----< > +------+ || +// R -->>-----< Comb. > |$_DFF_| || +// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q +// || +--< > +------+ | || +// || | \/\/\/\/ | || +// || | | || +// || +----------------------------+ || +// || || +// ++===================================++ // // is transformed into: // -// ++==================++ -// || Comb box || -// || || -// || /\/\/\/\ || -// D -->>-----< > || +------+ -// R -->>-----< Comb. > || |$_ABC_| -// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q -// $currQ +-->>-----< > || +------+ | -// | || \/\/\/\/ || | -// | || || | -// | ++==================++ | -// | | -// +----------------------------------------------+ +// ++==================++ +// || Comb box || +// || || +// || /\/\/\/\ || +// D -->>-----< > || +------+ +// R -->>-----< Comb. > || |$_ABC_| +// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q +// $abc9_currQ +-->>-----< > || +------+ | +// | || \/\/\/\/ || | +// | || || | +// | ++==================++ | +// | | +// +----------------------------------------------+ // // The purpose of the following FD* rules are to wrap the flop with: // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 @@ -74,7 +74,7 @@ // (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control // domain (which, combined with this cell type, encodes to `abc9' which // flops may be merged together) -// (d) a special _TECHMAP_REPLACE_.$currQ wire that will be used for feedback +// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -95,7 +95,7 @@ module FDRE (output reg Q, input C, CE, D, R); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; - wire _TECHMAP_REPLACE_.$currQ = Q; + wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -110,7 +110,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; - wire _TECHMAP_REPLACE_.$currQ = Q; + wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDCE (output reg Q, input C, CE, D, CLR); @@ -118,7 +118,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire $nextQ, $currQ; + wire $nextQ, $abc9_currQ; FDCE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), @@ -131,19 +131,19 @@ module FDCE (output reg Q, input C, CE, D, CLR); // here but captured by // $__ABC9_ASYNC below ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); // Since this is an async flop, async behaviour is also dealt with // using the $_ABC9_ASYNC box by abc9_map.v - \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; - wire _TECHMAP_REPLACE_.$currQ = $currQ; + wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; - wire $nextQ, $currQ; + wire $nextQ, $abc9_currQ; FDCE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( @@ -153,13 +153,13 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); // here but captured by // $__ABC9_ASYNC below ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; - wire _TECHMAP_REPLACE_.$currQ = $currQ; + wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE (output reg Q, input C, CE, D, PRE); @@ -167,7 +167,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire $nextQ, $currQ; + wire $nextQ, $abc9_currQ; FDPE #( .INIT(INIT), .IS_C_INVERTED(IS_C_INVERTED), @@ -180,17 +180,17 @@ module FDPE (output reg Q, input C, CE, D, PRE); // here but captured by // $__ABC9_ASYNC below ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; - wire _TECHMAP_REPLACE_.$currQ = $currQ; + wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; - wire $nextQ, $currQ; + wire $nextQ, $abc9_currQ; FDPE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( @@ -200,13 +200,13 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); // here but captured by // $__ABC9_ASYNC below ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); - \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; - wire _TECHMAP_REPLACE_.$currQ = $currQ; + wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDSE (output reg Q, input C, CE, D, S); @@ -228,7 +228,7 @@ module FDSE (output reg Q, input C, CE, D, S); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; - wire _TECHMAP_REPLACE_.$currQ = Q; + wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; @@ -243,7 +243,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; - wire _TECHMAP_REPLACE_.$currQ = Q; + wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module RAM32X1D ( -- cgit v1.2.3 From 4f0818275fe44c451be59235616061be8ff5e382 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 7 Oct 2019 15:58:55 -0700 Subject: Cleanup --- techlibs/xilinx/abc9_map.v | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index ee319a8e3..95546db37 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -25,11 +25,6 @@ // For example, (complex) flip-flops are expected to be described as an // combinatorial box (containing all control logic such as clock enable // or synchronous resets) followed by a basic D-Q flop. - -// ============================================================================ - -// `abc9' requires that complex flops be split into a combinatorial box -// feeding a simple flop ($_ABC9_FF_). // Yosys will automatically analyse the simulation model (described in // cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in // order to extract the combinatorial control logic left behind. @@ -55,8 +50,8 @@ // || || // || /\/\/\/\ || // D -->>-----< > || +------+ -// R -->>-----< Comb. > || |$_ABC_| -// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q +// R -->>-----< Comb. > || |$__ABC| +// CE -->>-----< logic >--->>-- $nextQ --| _FF_ |--+-->> Q // $abc9_currQ +-->>-----< > || +------+ | // | || \/\/\/\/ || | // | || || | -- cgit v1.2.3 From 344619079d42e541fee8dc370318d9927cd6fb95 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 19 Nov 2019 16:57:07 -0800 Subject: Do not drop async control signals in abc_map.v --- techlibs/xilinx/abc9_map.v | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 95546db37..fc224e832 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -120,10 +120,11 @@ module FDCE (output reg Q, input C, CE, D, CLR); .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(IS_CLR_INVERTED) + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) // ^^^ Note that async - // control is disabled - // here but captured by + // control is not directly + // supported by abc9 but its + // behaviour is captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); @@ -142,10 +143,11 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); FDCE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0) + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) // ^^^ Note that async - // control is disabled - // here but captured by + // control is not directly + // supported by abc9 but its + // behaviour is captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); @@ -169,10 +171,11 @@ module FDPE (output reg Q, input C, CE, D, PRE); .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED) + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) // ^^^ Note that async - // control is disabled - // here but captured by + // control is not directly + // supported by abc9 but its + // behaviour is captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); @@ -189,10 +192,11 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); FDPE_1 #( .INIT(INIT) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0) + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) // ^^^ Note that async - // control is disabled - // here but captured by + // control is not directly + // supported by abc9 but its + // behaviour is captured by // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); -- cgit v1.2.3 From df63d75ff35e1441360a4b28a12b32b3d00f1190 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Nov 2019 11:26:59 -0800 Subject: Fix INIT values --- techlibs/xilinx/abc9_map.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 95546db37..d2c0abeb6 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -96,7 +96,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; wire $nextQ; FDRE_1 #( - .INIT(|0), + .INIT(INIT), ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); @@ -205,7 +205,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); endmodule module FDSE (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; @@ -226,10 +226,10 @@ module FDSE (output reg Q, input C, CE, D, S); wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; wire $nextQ; FDSE_1 #( - .INIT(|0), + .INIT(INIT), ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); -- cgit v1.2.3 From af3055fe8354e0a082bd8415448fcbeb5ee435f6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Nov 2019 14:30:56 -0800 Subject: Add blackbox model for $__ABC9_FF_ so that clock partitioning works --- techlibs/xilinx/abc9_model.v | 3 +++ 1 file changed, 3 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index c17d6744a..cc0e5ec41 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -30,6 +30,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule +module \$__ABC9_FF_ (input D, output Q); +endmodule + (* abc_box_id = 1000 *) module \$__ABC9_ASYNC (input A, S, output Y); endmodule -- cgit v1.2.3 From 97b22413e533a7fca7a3542dd802321097bdc55c Mon Sep 17 00:00:00 2001 From: Martin Pietryka Date: Sat, 23 Nov 2019 06:18:23 +0100 Subject: coolrunner2: remove spurious log_pop() call, fixes #1463 This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka --- techlibs/coolrunner2/synth_coolrunner2.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index 21bbcaef4..014c68622 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -194,8 +194,6 @@ struct SynthCoolrunner2Pass : public ScriptPass if (!json_file.empty() || help_mode) run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); } - - log_pop(); } } SynthCoolrunner2Pass; -- cgit v1.2.3 From eb11c06a69c3b50e39cf363926992b40a9c440c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 23 Nov 2019 10:18:22 -0800 Subject: For abc9, run clkpart before ff_map and after abc9 --- techlibs/xilinx/synth_xilinx.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b5c203d1f..7105ba429 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -513,6 +513,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_ffs")) { if (abc9 || help_mode) { + run("clkpart -set_attr clkpart 1", "('-abc9' only)"); run("techmap -map " + ff_map_file, "('-abc9' only)"); } } @@ -537,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); + run("clkpart -unpart clkpart"); } else { if (nowidelut) -- cgit v1.2.3 From 6c79abbf5a3f0ea44f119d1f1ab3262778cf99ce Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 25 Nov 2019 14:33:21 +0100 Subject: gowin: add and test dff init values --- techlibs/gowin/cells_map.v | 225 +++++++++++++++++++++++++++++++++++------- techlibs/gowin/synth_gowin.cc | 15 ++- 2 files changed, 199 insertions(+), 41 deletions(-) (limited to 'techlibs') diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 9845e56a7..9c8b5aec1 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -1,82 +1,231 @@ +`default_nettype none //All DFF* have INIT, but the hardware is always initialised to the reset //value regardless. The parameter is ignored. // DFFN D Flip-Flop with Negative-Edge Clock -module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); + generate + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0)); + else + DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + // DFF D Flip-Flop -module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); + generate + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0)); + else + DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule // DFFE D Flip-Flop with Clock Enable -module \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule -module \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule +module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); + generate + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0)); + else + DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); + generate + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0)); + else + DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule // DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable -module \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule -module \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule +module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); + generate + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0)); + else + DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); + generate + if (_TECHMAP_WIREINIT_Q_ === 1'b1) + DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0)); + else + DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule // DFFR D Flip-Flop with Synchronous Reset -module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule -module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule + +module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset -module \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule -module \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFRE D Flip-Flop with Clock Enable and Synchronous Reset -module \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule -module \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule +module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset -module \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule -module \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule +module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFS D Flip-Flop with Synchronous Set -module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule +module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set -module \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule -module \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule +module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFSE D Flip-Flop with Clock Enable and Synchronous Set -module \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule -module \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule +module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set -module \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule -module \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule +module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFP D Flip-Flop with Asynchronous Preset -module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule +module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset -module \$_DFF_NP1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule +module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFC D Flip-Flop with Asynchronous Clear -module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule +module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear -module \$_DFF_NP0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule +module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset -module \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule -module \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule +module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset -module \$__DFFE_NP1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule -module \$__DFFE_NN1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule +module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule +module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; +endmodule // DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear -module \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule -module \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule +module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule // DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear -module \$__DFFE_NP0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule -module \$__DFFE_NN0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule +module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule +module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); + wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; +endmodule module \$lut (A, Y); diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 3c1426414..49fde540c 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -67,6 +67,9 @@ struct SynthGowinPass : public ScriptPass log(" -nowidelut\n"); log(" do not use muxes to implement LUTs larger than LUT4s\n"); log("\n"); + log(" -noiopads\n"); + log(" do not emit IOB at top level ports\n"); + log("\n"); log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); @@ -77,7 +80,7 @@ struct SynthGowinPass : public ScriptPass } string top_opt, vout_file; - bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9; + bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads; void clear_flags() YS_OVERRIDE { @@ -90,6 +93,7 @@ struct SynthGowinPass : public ScriptPass nodram = false; nowidelut = false; abc9 = false; + noiopads = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -144,6 +148,10 @@ struct SynthGowinPass : public ScriptPass abc9 = true; continue; } + if (args[argidx] == "-noiopads") { + noiopads = true; + continue; + } break; } extra_args(args, argidx, design); @@ -236,8 +244,9 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); - run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " - "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); + if (!noiopads || help_mode) + run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " + "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); run("clean"); } -- cgit v1.2.3 From 72d03dc910da379779f2f7a0a0406dd61593d696 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 25 Nov 2019 14:50:34 +0100 Subject: attempt to fix formatting --- techlibs/gowin/cells_map.v | 308 ++++++++++++++++++++++----------------------- 1 file changed, 154 insertions(+), 154 deletions(-) (limited to 'techlibs') diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 9c8b5aec1..aee912256 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -2,281 +2,281 @@ //All DFF* have INIT, but the hardware is always initialised to the reset //value regardless. The parameter is ignored. -// DFFN D Flip-Flop with Negative-Edge Clock -module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); +// DFFN D Flip-Flop with Negative-Edge Clock +module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); generate - if (_TECHMAP_WIREINIT_Q_ === 1'b1) + if (_TECHMAP_WIREINIT_Q_ === 1'b1) DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0)); - else + else DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); - endgenerate + endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -// DFF D Flip-Flop -module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); +// DFF D Flip-Flop +module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q); generate - if (_TECHMAP_WIREINIT_Q_ === 1'b1) + if (_TECHMAP_WIREINIT_Q_ === 1'b1) DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0)); - else + else DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); - endgenerate + endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -// DFFE D Flip-Flop with Clock Enable -module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); +// DFFE D Flip-Flop with Clock Enable +module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); generate - if (_TECHMAP_WIREINIT_Q_ === 1'b1) + if (_TECHMAP_WIREINIT_Q_ === 1'b1) DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0)); - else + else DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); - endgenerate + endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); +module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); generate - if (_TECHMAP_WIREINIT_Q_ === 1'b1) + if (_TECHMAP_WIREINIT_Q_ === 1'b1) DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0)); - else + else DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); - endgenerate + endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable -module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); +// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable +module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); generate - if (_TECHMAP_WIREINIT_Q_ === 1'b1) + if (_TECHMAP_WIREINIT_Q_ === 1'b1) DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0)); - else + else DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); - endgenerate + endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); +module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q); generate - if (_TECHMAP_WIREINIT_Q_ === 1'b1) + if (_TECHMAP_WIREINIT_Q_ === 1'b1) DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0)); - else + else DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); - endgenerate + endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -// DFFR D Flip-Flop with Synchronous Reset -module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); +// DFFR D Flip-Flop with Synchronous Reset +module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); +module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset -module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); +// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset +module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); +module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset -module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); +// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset +module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); +module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset -module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); +// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset +module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); +module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFS D Flip-Flop with Synchronous Set -module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); +// DFFS D Flip-Flop with Synchronous Set +module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); +module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set -module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); +// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set +module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); +module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFSE D Flip-Flop with Clock Enable and Synchronous Set -module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); +// DFFSE D Flip-Flop with Clock Enable and Synchronous Set +module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); +module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set -module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); +// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set +module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); +module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFP D Flip-Flop with Asynchronous Preset -module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); +// DFFP D Flip-Flop with Asynchronous Preset +module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); +module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset -module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); +// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset +module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); +module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFC D Flip-Flop with Asynchronous Clear -module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); +// DFFC D Flip-Flop with Asynchronous Clear +module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); +module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear -module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); +// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear +module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); - DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); +module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q); + DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset -module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); +// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset +module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); +module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset -module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); +// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset +module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); +module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0; endmodule -// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear -module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); +// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear +module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); +module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear -module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); +// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear +module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule -module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); - DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); +module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q); + DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1; endmodule module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; + parameter WIDTH = 0; + parameter LUT = 0; - input [WIDTH-1:0] A; - output Y; + input [WIDTH-1:0] A; + output Y; - generate - if (WIDTH == 1) begin - LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), - .I0(A[0])); - end else - if (WIDTH == 2) begin - LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), - .I0(A[0]), .I1(A[1])); - end else - if (WIDTH == 3) begin - LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), - .I0(A[0]), .I1(A[1]), .I2(A[2])); - end else - if (WIDTH == 4) begin - LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), - .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); - end else - if (WIDTH == 5) begin - wire f0, f1; - \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0)); - \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1)); - MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y)); - end else - if (WIDTH == 6) begin - wire f0, f1; - \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0)); - \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1)); - MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y)); - end else - if (WIDTH == 7) begin - wire f0, f1; - \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0)); - \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1)); - MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y)); - end else - if (WIDTH == 8) begin - wire f0, f1; - \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); - \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); - MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y)); - end else begin - wire _TECHMAP_FAIL_ = 1; - end - endgenerate + generate + if (WIDTH == 1) begin + LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), + .I0(A[0])); + end else + if (WIDTH == 2) begin + LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), + .I0(A[0]), .I1(A[1])); + end else + if (WIDTH == 3) begin + LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2])); + end else + if (WIDTH == 4) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end else + if (WIDTH == 5) begin + wire f0, f1; + \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0)); + \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1)); + MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y)); + end else + if (WIDTH == 6) begin + wire f0, f1; + \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0)); + \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1)); + MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y)); + end else + if (WIDTH == 7) begin + wire f0, f1; + \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0)); + \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1)); + MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y)); + end else + if (WIDTH == 8) begin + wire f0, f1; + \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); + \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); + MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y)); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate endmodule -- cgit v1.2.3 From 7562e7304e2592ddd5a914ec723a6563c14141e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 24 Nov 2019 14:17:46 +0100 Subject: xilinx: Use INV instead of LUT1 when applicable --- techlibs/xilinx/lut_map.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v index 13d3c3268..62d501632 100644 --- a/techlibs/xilinx/lut_map.v +++ b/techlibs/xilinx/lut_map.v @@ -56,8 +56,12 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin - LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[0])); + if (P_LUT == 2'b01) begin + INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0])); + end else begin + LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0])); + end end else if (WIDTH == 2) begin LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), -- cgit v1.2.3 From 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 24 Nov 2019 16:05:45 +0100 Subject: clkbufmap: Add support for inverters in clock path. --- techlibs/xilinx/cells_sim.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5faddcd52..fa33f4596 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -126,7 +126,11 @@ endmodule // assign O = IO, IO = T ? 1'bz : I; // endmodule -module INV(output O, input I); +module INV( + (* clkbuf_inv = "I" *) + output O, + input I +); assign O = !I; endmodule -- cgit v1.2.3 From 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 Nov 2019 12:36:13 -0800 Subject: Special abc9_clock wire to contain only clock signal --- techlibs/xilinx/abc9_map.v | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 9913b229f..29ddf7133 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -62,10 +62,8 @@ // The purpose of the following FD* rules are to wrap the flop with: // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop -// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock -// domain (used when partitioning the module so that `abc9' only -// performs sequential synthesis (with reachability analysis) correctly on -// one domain at a time) +// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock +// signal, used to extract the delay target // (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control // domain (which, combined with this cell type, encodes to `abc9' which // flops may be merged together) @@ -88,7 +86,7 @@ module FDRE (output reg Q, input C, CE, D, R); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule @@ -103,7 +101,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule @@ -133,7 +131,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -154,7 +152,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -182,7 +180,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -203,7 +201,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -225,7 +223,7 @@ module FDSE (output reg Q, input C, CE, D, S); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule @@ -240,7 +238,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule -- cgit v1.2.3 From 0466c48533ad2831a95c6b63c3a190adb76499e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 26 Nov 2019 05:04:28 +0100 Subject: xilinx: Add simulation models for IOBUF and OBUFT. --- techlibs/xilinx/cells_sim.v | 28 ++++++++++++++++++++++++++++ techlibs/xilinx/cells_xtra.py | 4 ++-- techlibs/xilinx/cells_xtra.v | 23 ----------------------- 3 files changed, 30 insertions(+), 25 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index fa33f4596..1be43f9d4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -59,6 +59,34 @@ module OBUF( assign O = I; endmodule +module IOBUF ( + (* iopad_external_pin *) + inout IO, + output O, + input I, + input T +); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign IO = T ? 1'bz : I; + assign O = IO; +endmodule + +module OBUFT ( + (* iopad_external_pin *) + output O, + input I, + input T +); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign O = T ? 1'bz : I; +endmodule + module BUFG( (* clkbuf_driver *) output O, diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index f401ebe78..82e403f78 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -326,7 +326,7 @@ CELLS = [ Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), # I/O. - Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), + # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), @@ -342,7 +342,7 @@ CELLS = [ Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), # Output + tristate. - Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), + # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), # Pulls. Cell('KEEPER'), diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index ce0949f2c..671d16e8a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -8160,18 +8160,6 @@ module IBUFGDS_DIFF_OUT (...); input IB; endmodule -module IOBUF (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input T; -endmodule - module IOBUF_DCIEN (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -8373,17 +8361,6 @@ module OBUFDS_DPHY (...); input LPTX_T; endmodule -module OBUFT (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - input I; - input T; -endmodule - module OBUFTDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; -- cgit v1.2.3 From 739f5309062f6e60809a2ebe4eda4602cca6fc41 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Nov 2019 14:51:39 -0800 Subject: Move 'clean' from map_luts to finalize --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7105ba429..6e8ced0df 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -560,7 +560,6 @@ struct SynthXilinxPass : public ScriptPass else techmap_args += " -map " + ff_map_file; run("techmap " + techmap_args); - run("clean"); } if (check_label("finalize")) { @@ -575,6 +574,7 @@ struct SynthXilinxPass : public ScriptPass run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); if (help_mode || ise) run("extractinv -inv INV O:I", "(only if '-ise')"); + run("clean"); } if (check_label("check")) { -- cgit v1.2.3 From df8dc6d1fb1f9fc47a8356b5f0bf572a1ea140d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 27 Nov 2019 09:10:34 -0800 Subject: ean call after abc{,9} --- techlibs/xilinx/synth_xilinx.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6e8ced0df..5bc55387b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -538,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); + run("clean"); run("clkpart -unpart clkpart"); } else { @@ -545,8 +546,8 @@ struct SynthXilinxPass : public ScriptPass run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + run("clean"); } - run("clean"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming -- cgit v1.2.3 From 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b Mon Sep 17 00:00:00 2001 From: Diego H Date: Tue, 26 Nov 2019 17:14:41 -0600 Subject: Adjusting Vivado's BRAM min bits threshold for RAMB18E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index f1161114e..ee961fff8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp endmatch +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. + -- cgit v1.2.3 From b1ab7c16c41f0a14b8b14a041367f2259b3c0e37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 28 Nov 2019 12:59:43 -0800 Subject: clkpart -unpart into 'finalize' --- techlibs/xilinx/synth_xilinx.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5bc55387b..554c42d68 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -538,16 +538,14 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); - run("clean"); - run("clkpart -unpart clkpart"); } else { if (nowidelut) run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); - run("clean"); } + run("clean"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming @@ -564,6 +562,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("finalize")) { + if (help_mode || abc9) + run("clkpart -unpart clkpart", "(only if 'abc9')"); + bool do_iopad = iopad || (ise && !noiopad); if (help_mode || !noclkbuf) { if (help_mode || do_iopad) -- cgit v1.2.3 From 2badaa9adbf3fa976ac7e9d967e7d098de429bed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 29 Nov 2019 15:55:29 +0000 Subject: xilinx: Add missing blackbox cell for BUFPLL. --- techlibs/xilinx/cells_xtra.py | 1 + techlibs/xilinx/cells_xtra.v | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 82e403f78..01e7101d1 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -372,6 +372,7 @@ CELLS = [ Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}), Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), # Clock buffers (IO and regional) -- Virtex. diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 671d16e8a..00a8a5f8a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -5240,9 +5240,13 @@ module RAMB18E1 (...); parameter IS_RSTRAMB_INVERTED = 1'b0; parameter IS_RSTREGARSTREG_INVERTED = 1'b0; parameter IS_RSTREGB_INVERTED = 1'b0; + (* abc9_arrival=2454 *) output [15:0] DOADO; + (* abc9_arrival=2454 *) output [15:0] DOBDO; + (* abc9_arrival=2454 *) output [1:0] DOPADOP; + (* abc9_arrival=2454 *) output [1:0] DOPBDOP; (* clkbuf_sink *) (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) @@ -5452,9 +5456,13 @@ module RAMB36E1 (...); parameter IS_RSTREGB_INVERTED = 1'b0; output CASCADEOUTA; output CASCADEOUTB; + (* abc9_arrival=2454 *) output [31:0] DOADO; + (* abc9_arrival=2454 *) output [31:0] DOBDO; + (* abc9_arrival=2454 *) output [3:0] DOPADOP; + (* abc9_arrival=2454 *) output [3:0] DOPBDOP; output [7:0] ECCPARITY; output [8:0] RDADDRECC; @@ -8527,6 +8535,18 @@ module BUFIO2FB (...); input I; endmodule +module BUFPLL (...); + parameter integer DIVIDE = 1; + parameter ENABLE_SYNC = "TRUE"; + (* clkbuf_driver *) + output IOCLK; + output LOCK; + output SERDESSTROBE; + input GCLK; + input LOCKED; + input PLLIN; +endmodule + module BUFPLL_MCB (...); parameter integer DIVIDE = 2; parameter LOCK_SRC = "LOCK_TO_0"; -- cgit v1.2.3 From 19bfb4195818be12e6fb962de29ca32444498c22 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 2 Dec 2019 14:17:06 -0800 Subject: Add INIT value to abc9_control --- techlibs/xilinx/abc9_map.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 29ddf7133..b8defcb64 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -87,7 +87,7 @@ module FDRE (output reg Q, input C, CE, D, R); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, R, IS_R_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); @@ -102,7 +102,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule @@ -132,7 +132,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); @@ -153,7 +153,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -181,7 +181,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); @@ -202,7 +202,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -224,7 +224,7 @@ module FDSE (output reg Q, input C, CE, D, S); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, S, IS_S_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); @@ -239,7 +239,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule -- cgit v1.2.3 From a3b25b4af899b78d7401ec2ea7cd988d6209e226 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Tue, 3 Dec 2019 15:12:25 +0100 Subject: Use -match-init to not synth contradicting init values --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 49fde540c..6cf058f29 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -216,7 +216,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_ffs")) { run("dffsr2dff"); - run("dff2dffs"); + run("dff2dffs -match-init"); run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); -- cgit v1.2.3 From 0add5965c7bb369bc9dd883c559bcd890d911c14 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 3 Dec 2019 14:27:45 -0800 Subject: techmap abc_unmap.v before xilinx_srl -fixed --- techlibs/xilinx/synth_xilinx.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 554c42d68..3fffd81f6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -538,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); + run("techmap -map +/xilinx/abc9_unmap.v"); } else { if (nowidelut) @@ -553,12 +554,10 @@ struct SynthXilinxPass : public ScriptPass run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"; if (help_mode) - techmap_args += " [-map " + ff_map_file + "]"; - else if (abc9) - techmap_args += " -map +/xilinx/abc9_unmap.v"; - else - techmap_args += " -map " + ff_map_file; - run("techmap " + techmap_args); + techmap_args += stringf("[-map %s]", ff_map_file.c_str()); + else if (!abc9) + techmap_args += stringf(" -map %s", ff_map_file.c_str()); + run("techmap " + techmap_args, "(option without '-abc9')"); } if (check_label("finalize")) { -- cgit v1.2.3 From 1ea9ce0ad7d2a44b88353be3a44eedf306ac786e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 3 Dec 2019 14:48:39 -0800 Subject: ice40_opt to ignore (* keep *) -ed cells --- techlibs/ice40/ice40_opt.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index ea56d3f4d..aa5c43649 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -41,6 +41,11 @@ static void run_ice40_opts(Module *module) for (auto cell : module->selected_cells()) { + if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER")) + continue; + if (cell->has_keep_attr()) + continue; + if (cell->type == "\\SB_LUT4") { sb_lut_cells.push_back(cell); -- cgit v1.2.3 From ed3f35917531e5757699261aae92135f59205bf2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 3 Dec 2019 14:49:10 -0800 Subject: $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve name and attr --- techlibs/ice40/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 662423f0a..efd763ef6 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -65,7 +65,7 @@ endmodule `ifndef NO_ADDER module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); parameter LUT = 0; - SB_CARRY carry ( + SB_CARRY _TECHMAP_REPLACE_ ( .I0(A), .I1(B), .CI(CI), -- cgit v1.2.3 From f98aa1c13fdba69a2ceedd1f3b6613816c60a637 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 3 Dec 2019 15:40:44 -0800 Subject: Revert "Add INIT value to abc9_control" This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22. --- techlibs/xilinx/abc9_map.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index b8defcb64..29ddf7133 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -87,7 +87,7 @@ module FDRE (output reg Q, input C, CE, D, R); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, R, IS_R_INVERTED}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); @@ -102,7 +102,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule @@ -132,7 +132,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); @@ -153,7 +153,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -181,7 +181,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); @@ -202,7 +202,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -224,7 +224,7 @@ module FDSE (output reg Q, input C, CE, D, S); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, S, IS_S_INVERTED}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); @@ -239,7 +239,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; - wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule -- cgit v1.2.3 From a181ff66d3094e5740b0c803e6fafa8e91bb11e5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 3 Dec 2019 18:47:09 -0800 Subject: Add abc9_init wire, attach to abc9_flop cell --- techlibs/xilinx/abc9_map.v | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 29ddf7133..98a4457ae 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -64,10 +64,12 @@ // the connectivity of its basic D-Q flop // (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock // signal, used to extract the delay target -// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control +// (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control // domain (which, combined with this cell type, encodes to `abc9' which // flops may be merged together) -// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback +// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial +// state +// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -88,6 +90,7 @@ module FDRE (output reg Q, input C, CE, D, R); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); @@ -103,6 +106,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule @@ -133,6 +137,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); @@ -154,6 +159,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -182,6 +188,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); @@ -203,6 +210,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -225,6 +233,7 @@ module FDSE (output reg Q, input C, CE, D, S); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); @@ -240,6 +249,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule -- cgit v1.2.3 From 10014e2643cdedd2050f072eb5d1b8d01dccc406 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 4 Dec 2019 06:31:09 +0100 Subject: xilinx: Add models for LUTRAM cells. (#1537) --- techlibs/xilinx/cells_sim.v | 797 ++++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/cells_xtra.py | 68 ++-- techlibs/xilinx/cells_xtra.v | 590 ------------------------------- 3 files changed, 831 insertions(+), 624 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 1be43f9d4..3ed0759db 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -471,6 +471,473 @@ module LDPE ( else if (GE && g) Q = D; endmodule +// LUTRAM. + +// Single port. + +module RAM16X1S ( + output O, + input A0, A1, A2, A3, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + reg [15:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM16X1S_1 ( + output O, + input A0, A1, A2, A3, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + reg [15:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM32X1S ( + output O, + input A0, A1, A2, A3, A4, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + reg [31:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM32X1S_1 ( + output O, + input A0, A1, A2, A3, A4, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + reg [31:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM64X1S ( + output O, + input A0, A1, A2, A3, A4, A5, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + reg [63:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM64X1S_1 ( + output O, + input A0, A1, A2, A3, A4, A5, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + reg [63:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM128X1S ( + output O, + input A0, A1, A2, A3, A4, A5, A6, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0}; + reg [127:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM128X1S_1 ( + output O, + input A0, A1, A2, A3, A4, A5, A6, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0}; + reg [127:0] mem = INIT; + assign O = mem[a]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM256X1S ( + output O, + input [7:0] A, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [255:0] INIT = 256'h0; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [255:0] mem = INIT; + assign O = mem[A]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule + +module RAM512X1S ( + output O, + input [8:0] A, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [511:0] INIT = 512'h0; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [511:0] mem = INIT; + assign O = mem[A]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule + +// Single port, wide. + +module RAM16X2S ( + output O0, O1, + input A0, A1, A2, A3, + input D0, D1, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [15:0] mem0 = INIT_00; + reg [15:0] mem1 = INIT_01; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + end +endmodule + +module RAM32X2S ( + output O0, O1, + input A0, A1, A2, A3, A4, + input D0, D1, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [31:0] mem0 = INIT_00; + reg [31:0] mem1 = INIT_01; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + end +endmodule + +module RAM64X2S ( + output O0, O1, + input A0, A1, A2, A3, A4, A5, + input D0, D1, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_00 = 64'h0000000000000000; + parameter [63:0] INIT_01 = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [63:0] mem0 = INIT_00; + reg [63:0] mem1 = INIT_01; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + end +endmodule + +module RAM16X4S ( + output O0, O1, O2, O3, + input A0, A1, A2, A3, + input D0, D1, D2, D3, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [15:0] INIT_02 = 16'h0000; + parameter [15:0] INIT_03 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [15:0] mem0 = INIT_00; + reg [15:0] mem1 = INIT_01; + reg [15:0] mem2 = INIT_02; + reg [15:0] mem3 = INIT_03; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + assign O2 = mem2[a]; + assign O3 = mem3[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + mem2[a] <= D2; + mem3[a] <= D3; + end +endmodule + +module RAM32X4S ( + output O0, O1, O2, O3, + input A0, A1, A2, A3, A4, + input D0, D1, D2, D3, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [31:0] INIT_02 = 32'h00000000; + parameter [31:0] INIT_03 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [31:0] mem0 = INIT_00; + reg [31:0] mem1 = INIT_01; + reg [31:0] mem2 = INIT_02; + reg [31:0] mem3 = INIT_03; + assign O0 = mem0[a]; + assign O1 = mem1[a]; + assign O2 = mem2[a]; + assign O3 = mem3[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D0; + mem1[a] <= D1; + mem2[a] <= D2; + mem3[a] <= D3; + end +endmodule + +module RAM16X8S ( + output [7:0] O, + input A0, A1, A2, A3, + input [7:0] D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [15:0] INIT_02 = 16'h0000; + parameter [15:0] INIT_03 = 16'h0000; + parameter [15:0] INIT_04 = 16'h0000; + parameter [15:0] INIT_05 = 16'h0000; + parameter [15:0] INIT_06 = 16'h0000; + parameter [15:0] INIT_07 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [15:0] mem0 = INIT_00; + reg [15:0] mem1 = INIT_01; + reg [15:0] mem2 = INIT_02; + reg [15:0] mem3 = INIT_03; + reg [15:0] mem4 = INIT_04; + reg [15:0] mem5 = INIT_05; + reg [15:0] mem6 = INIT_06; + reg [15:0] mem7 = INIT_07; + assign O[0] = mem0[a]; + assign O[1] = mem1[a]; + assign O[2] = mem2[a]; + assign O[3] = mem3[a]; + assign O[4] = mem4[a]; + assign O[5] = mem5[a]; + assign O[6] = mem6[a]; + assign O[7] = mem7[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D[0]; + mem1[a] <= D[1]; + mem2[a] <= D[2]; + mem3[a] <= D[3]; + mem4[a] <= D[4]; + mem5[a] <= D[5]; + mem6[a] <= D[6]; + mem7[a] <= D[7]; + end +endmodule + +module RAM32X8S ( + output [7:0] O, + input A0, A1, A2, A3, A4, + input [7:0] D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [31:0] INIT_02 = 32'h00000000; + parameter [31:0] INIT_03 = 32'h00000000; + parameter [31:0] INIT_04 = 32'h00000000; + parameter [31:0] INIT_05 = 32'h00000000; + parameter [31:0] INIT_06 = 32'h00000000; + parameter [31:0] INIT_07 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire clk = WCLK ^ IS_WCLK_INVERTED; + reg [31:0] mem0 = INIT_00; + reg [31:0] mem1 = INIT_01; + reg [31:0] mem2 = INIT_02; + reg [31:0] mem3 = INIT_03; + reg [31:0] mem4 = INIT_04; + reg [31:0] mem5 = INIT_05; + reg [31:0] mem6 = INIT_06; + reg [31:0] mem7 = INIT_07; + assign O[0] = mem0[a]; + assign O[1] = mem1[a]; + assign O[2] = mem2[a]; + assign O[3] = mem3[a]; + assign O[4] = mem4[a]; + assign O[5] = mem5[a]; + assign O[6] = mem6[a]; + assign O[7] = mem7[a]; + always @(posedge clk) + if (WE) begin + mem0[a] <= D[0]; + mem1[a] <= D[1]; + mem2[a] <= D[2]; + mem3[a] <= D[3]; + mem4[a] <= D[4]; + mem5[a] <= D[5]; + mem6[a] <= D[6]; + mem7[a] <= D[7]; + end +endmodule + +// Dual port. + +module RAM16X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, + input DPRA0, DPRA1, DPRA2, DPRA3 +); + parameter INIT = 16'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0}; + reg [15:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + +module RAM16X1D_1 ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, + input DPRA0, DPRA1, DPRA2, DPRA3 +); + parameter INIT = 16'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [3:0] a = {A3, A2, A1, A0}; + wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0}; + reg [15:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc9_arrival=1153 *) @@ -494,6 +961,29 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +module RAM32X1D_1 ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc9_arrival=1153 *) + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [31:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + module RAM64X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc9_arrival=1153 *) @@ -517,6 +1007,29 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +module RAM64X1D_1 ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc9_arrival=1153 *) + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter INIT = 64'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [5:0] a = {A5, A4, A3, A2, A1, A0}; + wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [63:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(negedge clk) if (WE) mem[a] <= D; +endmodule + module RAM128X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc9_arrival=1153 *) @@ -537,6 +1050,290 @@ module RAM128X1D ( always @(posedge clk) if (WE) mem[A] <= D; endmodule +module RAM256X1D ( + output DPO, SPO, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input [7:0] A, DPRA +); + parameter INIT = 256'h0; + parameter IS_WCLK_INVERTED = 1'b0; + reg [255:0] mem = INIT; + assign SPO = mem[A]; + assign DPO = mem[DPRA]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[A] <= D; +endmodule + +// Multi port. + +module RAM32M ( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + assign DOA = mem_a[2*ADDRA+:2]; + assign DOB = mem_b[2*ADDRB+:2]; + assign DOC = mem_c[2*ADDRC+:2]; + assign DOD = mem_d[2*ADDRD+:2]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[2*ADDRD+:2] <= DIA; + mem_b[2*ADDRD+:2] <= DIB; + mem_c[2*ADDRD+:2] <= DIC; + mem_d[2*ADDRD+:2] <= DID; + end +endmodule + +module RAM32M16 ( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + output [1:0] DOE, + output [1:0] DOF, + output [1:0] DOG, + output [1:0] DOH, + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input [4:0] ADDRE, + input [4:0] ADDRF, + input [4:0] ADDRG, + input [4:0] ADDRH, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input [1:0] DIE, + input [1:0] DIF, + input [1:0] DIG, + input [1:0] DIH, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + reg [63:0] mem_e = INIT_E; + reg [63:0] mem_f = INIT_F; + reg [63:0] mem_g = INIT_G; + reg [63:0] mem_h = INIT_H; + assign DOA = mem_a[2*ADDRA+:2]; + assign DOB = mem_b[2*ADDRB+:2]; + assign DOC = mem_c[2*ADDRC+:2]; + assign DOD = mem_d[2*ADDRD+:2]; + assign DOE = mem_e[2*ADDRE+:2]; + assign DOF = mem_f[2*ADDRF+:2]; + assign DOG = mem_g[2*ADDRG+:2]; + assign DOH = mem_h[2*ADDRH+:2]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[2*ADDRH+:2] <= DIA; + mem_b[2*ADDRH+:2] <= DIB; + mem_c[2*ADDRH+:2] <= DIC; + mem_d[2*ADDRH+:2] <= DID; + mem_e[2*ADDRH+:2] <= DIE; + mem_f[2*ADDRH+:2] <= DIF; + mem_g[2*ADDRH+:2] <= DIG; + mem_h[2*ADDRH+:2] <= DIH; + end +endmodule + +module RAM64M ( + output DOA, + output DOB, + output DOC, + output DOD, + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input DIA, + input DIB, + input DIC, + input DID, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[ADDRD] <= DIA; + mem_b[ADDRD] <= DIB; + mem_c[ADDRD] <= DIC; + mem_d[ADDRD] <= DID; + end +endmodule + +module RAM64M8 ( + output DOA, + output DOB, + output DOC, + output DOD, + output DOE, + output DOF, + output DOG, + output DOH, + input [4:0] ADDRA, + input [4:0] ADDRB, + input [4:0] ADDRC, + input [4:0] ADDRD, + input [4:0] ADDRE, + input [4:0] ADDRF, + input [4:0] ADDRG, + input [4:0] ADDRH, + input DIA, + input DIB, + input DIC, + input DID, + input DIE, + input DIF, + input DIG, + input DIH, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + reg [63:0] mem_e = INIT_E; + reg [63:0] mem_f = INIT_F; + reg [63:0] mem_g = INIT_G; + reg [63:0] mem_h = INIT_H; + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + assign DOE = mem_e[ADDRE]; + assign DOF = mem_f[ADDRF]; + assign DOG = mem_g[ADDRG]; + assign DOH = mem_h[ADDRH]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[ADDRH] <= DIA; + mem_b[ADDRH] <= DIB; + mem_c[ADDRH] <= DIC; + mem_d[ADDRH] <= DID; + mem_e[ADDRH] <= DIE; + mem_f[ADDRH] <= DIF; + mem_g[ADDRH] <= DIG; + mem_h[ADDRH] <= DIH; + end +endmodule + +// ROM. + +module ROM16X1 ( + output O, + input A0, A1, A2, A3 +); + parameter [15:0] INIT = 16'h0; + assign O = INIT[{A3, A2, A1, A0}]; +endmodule + +module ROM32X1 ( + output O, + input A0, A1, A2, A3, A4 +); + parameter [31:0] INIT = 32'h0; + assign O = INIT[{A4, A3, A2, A1, A0}]; +endmodule + +module ROM64X1 ( + output O, + input A0, A1, A2, A3, A4, A5 +); + parameter [63:0] INIT = 64'h0; + assign O = INIT[{A5, A4, A3, A2, A1, A0}]; +endmodule + +module ROM128X1 ( + output O, + input A0, A1, A2, A3, A4, A5, A6 +); + parameter [127:0] INIT = 128'h0; + assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}]; +endmodule + +module ROM256X1 ( + output O, + input A0, A1, A2, A3, A4, A5, A6, A7 +); + parameter [255:0] INIT = 256'h0; + assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}]; +endmodule + +// Shift registers. + module SRL16E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 (* abc9_arrival=1472 *) diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 01e7101d1..e4c580b9d 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -28,40 +28,40 @@ CELLS = [ # - UG974 (Ultrascale) # CLB -- RAM/ROM. - Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('ROM16X1'), - Cell('ROM32X1'), - Cell('ROM64X1'), - Cell('ROM128X1'), - Cell('ROM256X1'), + # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('ROM16X1'), + # Cell('ROM32X1'), + # Cell('ROM64X1'), + # Cell('ROM128X1'), + # Cell('ROM256X1'), # CLB -- registers/latches. # Virtex 1/2/4/5, Spartan 3. diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 00a8a5f8a..8ac596459 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -1,595 +1,5 @@ // Created by cells_xtra.py from Xilinx models -module RAM16X1S (...); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM16X1S_1 (...); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S_1 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S_1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM128X1S (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM128X1S_1 (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1S (...); - parameter [255:0] INIT = 256'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [7:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM512X1S (...); - parameter [511:0] INIT = 512'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [8:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM16X2S (...); - parameter [15:0] INIT_00 = 16'h0000; - parameter [15:0] INIT_01 = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X2S (...); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X2S (...); - parameter [63:0] INIT_00 = 64'h0000000000000000; - parameter [63:0] INIT_01 = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM16X4S (...); - parameter [15:0] INIT_00 = 16'h0000; - parameter [15:0] INIT_01 = 16'h0000; - parameter [15:0] INIT_02 = 16'h0000; - parameter [15:0] INIT_03 = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - output O2; - output O3; - input A0; - input A1; - input A2; - input A3; - input D0; - input D1; - input D2; - input D3; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X4S (...); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [31:0] INIT_02 = 32'h00000000; - parameter [31:0] INIT_03 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - output O2; - output O3; - input A0; - input A1; - input A2; - input A3; - input A4; - input D0; - input D1; - input D2; - input D3; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM16X8S (...); - parameter [15:0] INIT_00 = 16'h0000; - parameter [15:0] INIT_01 = 16'h0000; - parameter [15:0] INIT_02 = 16'h0000; - parameter [15:0] INIT_03 = 16'h0000; - parameter [15:0] INIT_04 = 16'h0000; - parameter [15:0] INIT_05 = 16'h0000; - parameter [15:0] INIT_06 = 16'h0000; - parameter [15:0] INIT_07 = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [7:0] O; - input A0; - input A1; - input A2; - input A3; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; - input [7:0] D; -endmodule - -module RAM32X8S (...); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [31:0] INIT_02 = 32'h00000000; - parameter [31:0] INIT_03 = 32'h00000000; - parameter [31:0] INIT_04 = 32'h00000000; - parameter [31:0] INIT_05 = 32'h00000000; - parameter [31:0] INIT_06 = 32'h00000000; - parameter [31:0] INIT_07 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [7:0] O; - input A0; - input A1; - input A2; - input A3; - input A4; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; - input [7:0] D; -endmodule - -module RAM16X1D (...); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO; - output SPO; - input A0; - input A1; - input A2; - input A3; - input D; - input DPRA0; - input DPRA1; - input DPRA2; - input DPRA3; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM16X1D_1 (...); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO; - output SPO; - input A0; - input A1; - input A2; - input A3; - input D; - input DPRA0; - input DPRA1; - input DPRA2; - input DPRA3; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1D_1 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO; - output SPO; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - input DPRA0; - input DPRA1; - input DPRA2; - input DPRA3; - input DPRA4; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1D_1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO; - output SPO; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - input DPRA0; - input DPRA1; - input DPRA2; - input DPRA3; - input DPRA4; - input DPRA5; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1D (...); - parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO; - output SPO; - input [7:0] A; - input D; - input [7:0] DPRA; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M16 (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - output [1:0] DOE; - output [1:0] DOF; - output [1:0] DOG; - output [1:0] DOH; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [4:0] ADDRE; - input [4:0] ADDRF; - input [4:0] ADDRG; - input [4:0] ADDRH; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - input [1:0] DIE; - input [1:0] DIF; - input [1:0] DIG; - input [1:0] DIH; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input DIA; - input DIB; - input DIC; - input DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M8 (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - output DOE; - output DOF; - output DOG; - output DOH; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input [5:0] ADDRE; - input [5:0] ADDRF; - input [5:0] ADDRG; - input [5:0] ADDRH; - input DIA; - input DIB; - input DIC; - input DID; - input DIE; - input DIF; - input DIG; - input DIH; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module ROM16X1 (...); - parameter [127:0] INIT = 16'h0000; - output O; - input A0; - input A1; - input A2; - input A3; -endmodule - -module ROM32X1 (...); - parameter [31:0] INIT = 32'h00000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; -endmodule - -module ROM64X1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; -endmodule - -module ROM128X1 (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; -endmodule - -module ROM256X1 (...); - parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input A7; -endmodule - module FDCPE (...); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; -- cgit v1.2.3 From fcce94010f3282e7f7d3f602b3e710cb7ce524ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 4 Dec 2019 09:44:00 +0100 Subject: xilinx: Add tristate buffer mapping. (#1528) Fixes #1225. --- techlibs/xilinx/cells_map.v | 8 ++++++++ techlibs/xilinx/synth_xilinx.cc | 17 ++++++++--------- 2 files changed, 16 insertions(+), 9 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index a15884ec4..de2068bc5 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -363,3 +363,11 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); else MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule + +module \$__XILINX_TINOUTPAD (input I, OE, output O, inout IO); + IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .IO(IO)); +endmodule + +module \$__XILINX_TOUTPAD (input I, OE, output O); + OBUFT _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE)); +endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3d4a65c5d..2c5686a35 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -282,6 +282,7 @@ struct SynthXilinxPass : public ScriptPass void script() YS_OVERRIDE { + bool do_iopad = iopad || (ise && !noiopad); std::string ff_map_file; if (help_mode) ff_map_file = "+/xilinx/{family}_ff_map.v"; @@ -305,6 +306,8 @@ struct SynthXilinxPass : public ScriptPass run("proc"); if (flatten || help_mode) run("flatten", "(with '-flatten')"); + run("tribuf -logic"); + run("deminout"); run("opt_expr"); run("opt_clean"); run("check"); @@ -503,6 +506,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_cells")) { + // Needs to be done before logic optimization, so that inverters (OE vs T) are handled. + if (help_mode || do_iopad) + run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v"; if (widemux > 0) techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); @@ -561,15 +567,8 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("finalize")) { - bool do_iopad = iopad || (ise && !noiopad); - if (help_mode || !noclkbuf) { - if (help_mode || do_iopad) - run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')"); - else - run("clkbufmap -buf BUFG O:I"); - } - if (help_mode || do_iopad) - run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); + if (help_mode || !noclkbuf) + run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')"); if (help_mode || ise) run("extractinv -inv INV O:I", "(only if '-ise')"); } -- cgit v1.2.3 From 31ef4cc7048b9da557ee78bb791c5bb7210e9fc5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Dec 2019 16:11:02 -0800 Subject: abc9_map.v to do `zinit' and make INIT = 1'b0 --- techlibs/xilinx/abc9_map.v | 182 ++++++++++++++++++++++++++++----------------- 1 file changed, 112 insertions(+), 70 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 98a4457ae..8939b46a0 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -71,43 +71,55 @@ // state // (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour +// In order to perform sequential synthesis, `abc9' also requires that +// the initial value of all flops be zero. module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; - wire $nextQ; + wire DD, QQ, $nextQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDRE #( - .INIT(INIT), + .INIT(1'b0), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_R_INVERTED(IS_R_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) + .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = Q; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; - wire $nextQ; + wire DD, QQ, $nextQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDRE_1 #( - .INIT(INIT), + .INIT(1'b0), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) + .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R) ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = Q; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule module FDCE (output reg Q, input C, CE, D, CLR); @@ -115,103 +127,123 @@ module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire $nextQ, $abc9_currQ; + wire DD, QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDCE #( - .INIT(INIT), + .INIT(1'b0), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below + .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); // Since this is an async flop, async behaviour is also dealt with // using the $_ABC9_ASYNC box by abc9_map.v - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; - wire $nextQ, $abc9_currQ; + wire DD, QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDCE_1 #( - .INIT(INIT) + .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below + .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE (output reg Q, input C, CE, D, PRE); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire $nextQ, $abc9_currQ; + wire DD, QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDPE #( - .INIT(INIT), + .INIT(1'b0), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below + .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); - parameter [0:0] INIT = 1'b0; - wire $nextQ, $abc9_currQ; + parameter [0:0] INIT = 1'b1; + wire DD, QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDPE_1 #( - .INIT(INIT) + .INIT(1'b0), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below + .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q)); + \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule module FDSE (output reg Q, input C, CE, D, S); @@ -219,38 +251,48 @@ module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; - wire $nextQ; + wire DD, QQ, $nextQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDSE #( - .INIT(INIT), + .INIT(1'b0), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), .IS_S_INVERTED(IS_S_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) + .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S) ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = Q; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; - wire $nextQ; + wire DD, QQ, $nextQ; + generate if (INIT == 1'b1) + assign DD = ~D, Q = ~QQ; + else + assign DD = D, Q = QQ; + endgenerate FDSE_1 #( - .INIT(INIT), + .INIT(1'b0), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) + .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S) ); - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT; - wire _TECHMAP_REPLACE_.$abc9_currQ = Q; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule module RAM32X1D ( -- cgit v1.2.3 From b43986c5a1e9c41865139df9c0b5f9750c26762c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Dec 2019 16:34:34 -0800 Subject: output reg Q -> output Q to suppress warning --- techlibs/xilinx/abc9_map.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 8939b46a0..d84b9a8fa 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -73,7 +73,7 @@ // into the (combinatorial) FD* cell to facilitate clock-enable behaviour // In order to perform sequential synthesis, `abc9' also requires that // the initial value of all flops be zero. -module FDRE (output reg Q, input C, CE, D, R); +module FDRE (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -100,7 +100,7 @@ module FDRE (output reg Q, input C, CE, D, R); wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule -module FDRE_1 (output reg Q, input C, CE, D, R); +module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; wire DD, QQ, $nextQ; generate if (INIT == 1'b1) @@ -122,7 +122,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule -module FDCE (output reg Q, input C, CE, D, CLR); +module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -157,7 +157,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule -module FDCE_1 (output reg Q, input C, CE, D, CLR); +module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; wire DD, QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) @@ -185,7 +185,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule -module FDPE (output reg Q, input C, CE, D, PRE); +module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -218,7 +218,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule -module FDPE_1 (output reg Q, input C, CE, D, PRE); +module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; wire DD, QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) @@ -246,7 +246,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule -module FDSE (output reg Q, input C, CE, D, S); +module FDSE (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -273,7 +273,7 @@ module FDSE (output reg Q, input C, CE, D, S); wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule -module FDSE_1 (output reg Q, input C, CE, D, S); +module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; wire DD, QQ, $nextQ; generate if (INIT == 1'b1) -- cgit v1.2.3 From 258a34e6f148928e80f13416b28d6bba6988c78a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Dec 2019 20:33:24 -0800 Subject: Oh deary me --- techlibs/xilinx/cells_sim.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d845b324f..2fda3b8fd 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -378,10 +378,10 @@ module FDPE ( parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) - 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ; - 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ; - 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ; - 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ; + 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate endmodule -- cgit v1.2.3 From 19bc429482418aa42861ca0f195d86bc9577e320 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Dec 2019 21:36:41 -0800 Subject: abc9_map.v to transform INIT=1 to INIT=0 --- techlibs/xilinx/abc9_map.v | 319 ++++++++++++++++++++++++++++----------------- 1 file changed, 201 insertions(+), 118 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index d84b9a8fa..3fa5f5a1c 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -71,27 +71,39 @@ // state // (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour +// // In order to perform sequential synthesis, `abc9' also requires that // the initial value of all flops be zero. + module FDRE (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; - wire DD, QQ, $nextQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; + wire QQ, $nextQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDSE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_R_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R) + ); + end + else begin + assign Q = QQ; + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_R_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) + ); + end endgenerate - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_R_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R) - ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals @@ -102,17 +114,24 @@ module FDRE (output Q, input C, CE, D, R); endmodule module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; - wire DD, QQ, $nextQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; + wire QQ, $nextQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDSE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R) + ); + end + else begin + assign Q = QQ; + FDRE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) + ); + end endgenerate - FDRE_1 #( - .INIT(1'b0), - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R) - ); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals @@ -127,25 +146,39 @@ module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire DD, QQ, $nextQ, $abc9_currQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; - endgenerate - FDCE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_CLR_INVERTED(IS_CLR_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below - ); + wire QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDPE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_PRE_INVERTED(IS_CLR_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end + else begin + assign Q = QQ; + FDCE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_CLR_INVERTED(IS_CLR_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); // Since this is an async flop, async behaviour is also dealt with // using the $_ABC9_ASYNC box by abc9_map.v @@ -159,22 +192,32 @@ module FDCE (output Q, input C, CE, D, CLR); endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; - wire DD, QQ, $nextQ, $abc9_currQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; - endgenerate - FDCE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below - ); + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDPE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end + else begin + assign Q = QQ; + FDCE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); @@ -190,25 +233,39 @@ module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire DD, QQ, $nextQ, $abc9_currQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; - endgenerate - FDPE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_PRE_INVERTED(IS_PRE_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below - ); + wire QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDCE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_CLR_INVERTED(IS_PRE_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end + else begin + assign Q = QQ; + FDPE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_PRE_INVERTED(IS_PRE_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); @@ -220,22 +277,33 @@ module FDPE (output Q, input C, CE, D, PRE); endmodule module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; - wire DD, QQ, $nextQ, $abc9_currQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; - endgenerate - FDPE_1 #( - .INIT(1'b0), - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) - // ^^^ Note that async - // control is not directly - // supported by abc9 but its - // behaviour is captured by - // $__ABC9_ASYNC below - ); + wire QQ, $nextQ, $abc9_currQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDCE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end + else begin + assign Q = QQ; + FDPE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + // ^^^ Note that async + // control is not directly + // supported by abc9 but its + // behaviour is captured by + // $__ABC9_ASYNC below + ); + end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); @@ -251,20 +319,29 @@ module FDSE (output Q, input C, CE, D, S); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; - wire DD, QQ, $nextQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; - endgenerate - FDSE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_S_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S) - ); + wire QQ, $nextQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S) + ); + end + else begin + assign Q = QQ; + FDSE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) + ); + end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals @@ -275,17 +352,23 @@ module FDSE (output Q, input C, CE, D, S); endmodule module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; - wire DD, QQ, $nextQ; - generate if (INIT == 1'b1) - assign DD = ~D, Q = ~QQ; - else - assign DD = D, Q = QQ; - endgenerate - FDSE_1 #( - .INIT(1'b0), - ) _TECHMAP_REPLACE_ ( - .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S) - ); + wire QQ, $nextQ; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDRE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S) + ); + end + else begin + assign Q = QQ; + FDSE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) + ); + end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals -- cgit v1.2.3 From 0d248dd7bae707505071b309b55bac75facccab8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Dec 2019 23:04:40 -0800 Subject: Missing wire declaration --- techlibs/xilinx/abc9_map.v | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 3fa5f5a1c..d2159f82d 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -192,6 +192,7 @@ module FDCE (output Q, input C, CE, D, CLR); endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; + wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDPE_1 #( -- cgit v1.2.3 From 864bff14f11fc67bac40f77e5bf17c7fc61ad9f6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Dec 2019 11:11:53 -0800 Subject: Revert "Special abc9_clock wire to contain only clock signal" This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d. --- techlibs/xilinx/abc9_map.v | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index d2159f82d..4d76a5232 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -62,8 +62,10 @@ // The purpose of the following FD* rules are to wrap the flop with: // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop -// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock -// signal, used to extract the delay target +// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock +// domain (used when partitioning the module so that `abc9' only +// performs sequential synthesis (with reachability analysis) correctly on +// one domain at a time) and used to infert the delay target // (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control // domain (which, combined with this cell type, encodes to `abc9' which // flops may be merged together) @@ -107,7 +109,7 @@ module FDRE (output Q, input C, CE, D, R); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; @@ -135,7 +137,7 @@ module FDRE_1 (output Q, input C, CE, D, R); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; @@ -185,7 +187,7 @@ module FDCE (output Q, input C, CE, D, CLR); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; @@ -223,7 +225,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; @@ -271,7 +273,7 @@ module FDPE (output Q, input C, CE, D, PRE); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; @@ -309,7 +311,7 @@ module FDPE_1 (output Q, input C, CE, D, PRE); \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; @@ -346,7 +348,7 @@ module FDSE (output Q, input C, CE, D, S); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; @@ -373,7 +375,7 @@ module FDSE_1 (output Q, input C, CE, D, S); \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); // Special signals - wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C; + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -- cgit v1.2.3 From 02786b0aa0eb45a53b92b86b192d5ae5846366bd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Dec 2019 17:25:26 -0800 Subject: Remove clkpart --- techlibs/xilinx/synth_xilinx.cc | 4 ---- 1 file changed, 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3fffd81f6..30be9832c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -513,7 +513,6 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_ffs")) { if (abc9 || help_mode) { - run("clkpart -set_attr clkpart 1", "('-abc9' only)"); run("techmap -map " + ff_map_file, "('-abc9' only)"); } } @@ -561,9 +560,6 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("finalize")) { - if (help_mode || abc9) - run("clkpart -unpart clkpart", "(only if 'abc9')"); - bool do_iopad = iopad || (ise && !noiopad); if (help_mode || !noclkbuf) { if (help_mode || do_iopad) -- cgit v1.2.3 From ec0acc9f85af0d21ea722375788b372cc416f173 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Dec 2019 23:18:27 -0800 Subject: abc9 to use mergeability class to differentiate sync/async --- techlibs/xilinx/abc9_map.v | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 4d76a5232..d5d5a89f6 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -62,16 +62,18 @@ // The purpose of the following FD* rules are to wrap the flop with: // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop -// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock +// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to +// capture asynchronous behaviour +// (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock // domain (used when partitioning the module so that `abc9' only // performs sequential synthesis (with reachability analysis) correctly on // one domain at a time) and used to infert the delay target -// (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control +// (d) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control // domain (which, combined with this cell type, encodes to `abc9' which // flops may be merged together) -// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial +// (e) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial // state -// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback +// (f) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour // // In order to perform sequential synthesis, `abc9' also requires that @@ -110,7 +112,7 @@ module FDRE (output Q, input C, CE, D, R); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule @@ -138,7 +140,7 @@ module FDRE_1 (output Q, input C, CE, D, R); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule @@ -188,7 +190,7 @@ module FDCE (output Q, input C, CE, D, CLR); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -226,7 +228,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -274,7 +276,7 @@ module FDPE (output Q, input C, CE, D, PRE); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -312,7 +314,8 @@ module FDPE_1 (output Q, input C, CE, D, PRE); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; +>>>>>>> d3b23690... abc9 to use mergeability class to differentiate sync/async wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -349,7 +352,7 @@ module FDSE (output Q, input C, CE, D, S); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule @@ -376,7 +379,7 @@ module FDSE_1 (output Q, input C, CE, D, S); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule -- cgit v1.2.3 From c767525441ebc6a21b29bf0c1208049cd38adc8e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Dec 2019 16:23:09 -0800 Subject: Remove creation of $abc9_control_wire --- techlibs/xilinx/abc9_map.v | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index d5d5a89f6..49000ea25 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -65,15 +65,14 @@ // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to // capture asynchronous behaviour // (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock -// domain (used when partitioning the module so that `abc9' only +// domain and polarity (used when partitioning the module so that `abc9' only // performs sequential synthesis (with reachability analysis) correctly on -// one domain at a time) and used to infert the delay target -// (d) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control -// domain (which, combined with this cell type, encodes to `abc9' which -// flops may be merged together) -// (e) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial +// one domain at a time) and also used to infer the optional delay target +// from the (* abc9_clock_period = %d *) attribute attached to any wire +// within +// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial // state -// (f) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback +// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour // // In order to perform sequential synthesis, `abc9' also requires that @@ -112,7 +111,6 @@ module FDRE (output Q, input C, CE, D, R); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule @@ -140,7 +138,6 @@ module FDRE_1 (output Q, input C, CE, D, R); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule @@ -190,7 +187,6 @@ module FDCE (output Q, input C, CE, D, CLR); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -228,7 +224,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -276,7 +271,6 @@ module FDPE (output Q, input C, CE, D, PRE); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -314,8 +308,6 @@ module FDPE_1 (output Q, input C, CE, D, PRE); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */}; ->>>>>>> d3b23690... abc9 to use mergeability class to differentiate sync/async wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; endmodule @@ -352,7 +344,6 @@ module FDSE (output Q, input C, CE, D, S); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule @@ -379,7 +370,6 @@ module FDSE_1 (output Q, input C, CE, D, S); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; endmodule -- cgit v1.2.3 From 98c9ea605b5cb2eb540ae5b804a18f8921f0bc46 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Dec 2019 17:05:02 -0800 Subject: techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger --- techlibs/ecp5/synth_ecp5.cc | 5 +++++ techlibs/ice40/synth_ice40.cc | 5 +++++ techlibs/xilinx/synth_xilinx.cc | 5 +++++ 3 files changed, 15 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 4cbb56ea1..b099c25d3 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -312,6 +312,11 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 901194b06..2f0bdb130 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2c5686a35..8c30148c0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -533,6 +533,11 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); + run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); + run("wbflip @abc9_boxes"); + run("techmap -autoproc @abc9_boxes"); + run("aigmap @abc9_boxes"); + run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); -- cgit v1.2.3 From 184c0e796a0e6870c025808b1902da5f3771b721 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 7 Dec 2019 13:04:36 +0000 Subject: ecp5: Add support for mapping PRLD FFs Signed-off-by: David Shah --- techlibs/ecp5/cells_map.v | 15 +++++++++++++++ techlibs/ecp5/synth_ecp5.cc | 17 +++++++++++++---- 2 files changed, 28 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 71ae9237b..10e89a3e0 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), . module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +`ifdef ASYNC_PRLD +module \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule +module \$_DLATCH_P_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(E), .DI(1'b0), .M(D), .Q(Q)); endmodule + +module \$_DFFSR_NNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_NNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule +module \$_DFFSR_NPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_NPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule + +module \$_DFFSR_PNN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_PNP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!S || R), .DI(D), .M(!R), .Q(Q)); endmodule +module \$_DFFSR_PPN_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || !R), .DI(D), .M(R), .Q(Q)); endmodule +module \$_DFFSR_PPP_ (input C, S, R, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(S || R), .DI(D), .M(!R), .Q(Q)); endmodule +`endif + `include "cells_ff.vh" `include "cells_io.vh" diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 4cbb56ea1..b71bb2395 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -79,6 +79,9 @@ struct SynthEcp5Pass : public ScriptPass log(" -nowidelut\n"); log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); log("\n"); + log(" -asyncprld\n"); + log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n"); + log("\n"); log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); @@ -99,7 +102,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr; void clear_flags() YS_OVERRIDE { @@ -112,6 +115,7 @@ struct SynthEcp5Pass : public ScriptPass nobram = false; nolutram = false; nowidelut = false; + asyncprld = false; flatten = true; retime = false; abc2 = false; @@ -176,6 +180,10 @@ struct SynthEcp5Pass : public ScriptPass nobram = true; continue; } + if (args[argidx] == "-asyncprld") { + asyncprld = true; + continue; + } if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") { nolutram = true; continue; @@ -292,7 +300,7 @@ struct SynthEcp5Pass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); - run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); + run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); run("opt_expr -undriven -mux_undef"); run("simplemap"); run("ecp5_ffinit"); @@ -306,10 +314,11 @@ struct SynthEcp5Pass : public ScriptPass if (abc2 || help_mode) { run("abc", " (only if -abc2)"); } - std::string techmap_args = "-map +/ecp5/latches_map.v"; + std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v"; if (abc9) techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1"; - run("techmap " + techmap_args); + if (!asyncprld || abc9) + run("techmap " + techmap_args); if (abc9) { run("read_verilog -icells -lib +/ecp5/abc9_model.v"); -- cgit v1.2.3 From e05372778a26e5cbc5166f208eddc6a1b42ed198 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Dec 2019 11:48:28 -0800 Subject: ice40_wrapcarry to really preserve attributes via -unwrap option --- techlibs/ice40/cells_map.v | 19 ------------------- techlibs/ice40/synth_ice40.cc | 1 + 2 files changed, 1 insertion(+), 19 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index efd763ef6..759549e30 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -61,22 +61,3 @@ module \$lut (A, Y); endgenerate endmodule `endif - -`ifndef NO_ADDER -module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); - parameter LUT = 0; - SB_CARRY _TECHMAP_REPLACE_ ( - .I0(A), - .I1(B), - .CI(CI), - .CO(CO) - ); - \$lut #( - .WIDTH(4), - .LUT(LUT) - ) lut ( - .A({I0,A,B,I3}), - .Y(O) - ); -endmodule -`endif diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 901194b06..ed7a16c08 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -363,6 +363,7 @@ struct SynthIce40Pass : public ScriptPass else run(abc + " -dress -lut 4", "(skip if -noabc)"); } + run("ice40_wrapcarry -unwrap"); run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("clean"); run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); -- cgit v1.2.3 From 500ed9b501386b38faf6388b43c42abdbc0ee3ec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Dec 2019 12:45:22 -0800 Subject: Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 --- techlibs/ice40/arith_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index 26b24db9e..00a07247b 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -50,7 +50,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); // A[2]: 1111 0000 1111 0000 // A[3]: 1111 1111 0000 0000 .LUT(16'b 0110_1001_1001_0110) - ) fadd ( + ) carry ( .A(AA[i]), .B(BB[i]), .CI(C[i]), -- cgit v1.2.3 From fb203d2a2c02c3df1a2c6a92ec196e579495c8d4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Dec 2019 14:29:29 -0800 Subject: ice40_opt to restore attributes/name when unwrapping --- techlibs/ice40/ice40_opt.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index aa5c43649..371ceb623 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -117,6 +117,21 @@ static void run_ice40_opts(Module *module) if (GetSize(replacement_output)) { optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); + auto it = cell->attributes.find(ID(SB_LUT4.name)); + if (it != cell->attributes.end()) { + module->rename(cell, it->second.decode_string()); + decltype(Cell::attributes) new_attr; + for (const auto &a : cell->attributes) + if (a.first.begins_with("\\SB_LUT4.\\")) + new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; + else if (a.first == ID(src)) + new_attr.insert(std::make_pair(a.first, a.second)); + else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) + continue; + else + log_abort(); + cell->attributes = std::move(new_attr); + } module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", -- cgit v1.2.3 From 49c2e59b2a4fce770bdaa74177adff0ee995f90d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Dec 2019 15:44:19 -0800 Subject: Fix comment --- techlibs/xilinx/abc9_xc7.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 24b1898a4..4e632c0fa 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -107,7 +107,7 @@ $__ABC9_LUT6 2000 0 7 1 # SLICEM/A6LUT + F7BMUX # Box to emulate comb/seq behaviour of RAMD128 # Inputs: A S0 S1 S2 S3 S4 S5 S6 -# Outputs: DPO SPO +# Outputs: Y $__ABC9_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 -- cgit v1.2.3 From eab3272cdeed697bdb9664c2d8a133d336addb7c Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Tue, 10 Dec 2019 13:31:45 +0000 Subject: synth_intel: cyclone10 -> cyclone10lp --- techlibs/intel/Makefile.inc | 2 +- techlibs/intel/cyclone10/cells_arith.v | 65 --------------- techlibs/intel/cyclone10/cells_map.v | 109 ------------------------ techlibs/intel/cyclone10/cells_sim.v | 137 ------------------------------- techlibs/intel/cyclone10lp/cells_arith.v | 65 +++++++++++++++ techlibs/intel/cyclone10lp/cells_map.v | 109 ++++++++++++++++++++++++ techlibs/intel/cyclone10lp/cells_sim.v | 137 +++++++++++++++++++++++++++++++ techlibs/intel/synth_intel.cc | 6 +- 8 files changed, 315 insertions(+), 315 deletions(-) delete mode 100644 techlibs/intel/cyclone10/cells_arith.v delete mode 100644 techlibs/intel/cyclone10/cells_map.v delete mode 100644 techlibs/intel/cyclone10/cells_sim.v create mode 100644 techlibs/intel/cyclone10lp/cells_arith.v create mode 100644 techlibs/intel/cyclone10lp/cells_map.v create mode 100644 techlibs/intel/cyclone10lp/cells_sim.v (limited to 'techlibs') diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 4e8f423c8..92a83b5af 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k. $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) # Add the cell models and mappings for the VQM backend -families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive +families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) diff --git a/techlibs/intel/cyclone10/cells_arith.v b/techlibs/intel/cyclone10/cells_arith.v deleted file mode 100644 index 5ae8d6cea..000000000 --- a/techlibs/intel/cyclone10/cells_arith.v +++ /dev/null @@ -1,65 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// NOTE: This is still WIP. -(* techmap_celltype = "$alu" *) -module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - input [A_WIDTH-1:0] A; - input [B_WIDTH-1:0] B; - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - //output [Y_WIDTH-1:0] CO; - output CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; - - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - wire [Y_WIDTH-1:0] AA = A_buf; - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - //wire [Y_WIDTH:0] C = {CO, CI}; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; - - /* Start implementation */ - (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - - genvar i; - generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); - assign CO = COx[Y_WIDTH]; - end - else - cyclone10lp_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); - end: slice - endgenerate - /* End implementation */ - assign X = AA ^ BB; - -endmodule diff --git a/techlibs/intel/cyclone10/cells_map.v b/techlibs/intel/cyclone10/cells_map.v deleted file mode 100644 index c2f6f403c..000000000 --- a/techlibs/intel/cyclone10/cells_map.v +++ /dev/null @@ -1,109 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -// > c60k28 (Viacheslav, VT) [at] yandex [dot] com -// > Intel FPGA technology mapping. User must first simulate the generated \ -// > netlist before going to test it on board. -// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. - -// Normal mode DFF negedge clk, negedge reset -module \$_DFF_N_ (input D, C, output Q); - parameter WYSIWYG="TRUE"; - parameter power_up=1'bx; - dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule -// Normal mode DFF -module \$_DFF_P_ (input D, C, output Q); - parameter WYSIWYG="TRUE"; - parameter power_up=1'bx; - dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule - -// Async Active Low Reset DFF -module \$_DFF_PN0_ (input D, C, R, output Q); - parameter WYSIWYG="TRUE"; - parameter power_up=1'bx; - dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule -// Async Active High Reset DFF -module \$_DFF_PP0_ (input D, C, R, output Q); - parameter WYSIWYG="TRUE"; - parameter power_up=1'bx; - wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule - -module \$__DFFE_PP0 (input D, C, E, R, output Q); - parameter WYSIWYG="TRUE"; - parameter power_up=1'bx; - wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); -endmodule - -// Input buffer map -module \$__inpad (input I, output O); - cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); -endmodule - -// Output buffer map -module \$__outpad (input I, output O); - cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); -endmodule - -// LUT Map -/* 0 -> datac - 1 -> cin */ -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - input [WIDTH-1:0] A; - output Y; - generate - if (WIDTH == 1) begin - assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end else - if (WIDTH == 2) begin - cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}), - .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(1'b1), - .datad(1'b1)); - end else - if(WIDTH == 3) begin - cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}), - .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(1'b1)); - end else - if(WIDTH == 4) begin - cyclone10lp_lcell_comb #(.lut_mask(LUT), - .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(A[3])); - end else - wire _TECHMAP_FAIL_ = 1; - endgenerate - -endmodule - - diff --git a/techlibs/intel/cyclone10/cells_sim.v b/techlibs/intel/cyclone10/cells_sim.v deleted file mode 100644 index f5a8aee2b..000000000 --- a/techlibs/intel/cyclone10/cells_sim.v +++ /dev/null @@ -1,137 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -module VCC (output V); - assign V = 1'b1; -endmodule // VCC - -module GND (output G); - assign G = 1'b0; -endmodule // GND - -/* Altera Cyclone 10 LP devices Input Buffer Primitive */ -module cyclone10lp_io_ibuf - (output o, input i, input ibar); - assign ibar = ibar; - assign o = i; -endmodule // cyclone10lp_io_ibuf - -/* Altera Cyclone 10 LP devices Output Buffer Primitive */ -module cyclone10lp_io_obuf - (output o, input i, input oe); - assign o = i; - assign oe = oe; -endmodule // cyclone10lp_io_obuf - -/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */ -module cyclone10lp_lcell_comb - (output combout, cout, - input dataa, datab, datac, datad, cin); - - /* Internal parameters which define the behaviour - of the LUT primitive. - lut_mask define the lut function, can be expressed in 16-digit bin or hex. - sum_lutc_input define the type of LUT (combinational | arithmetic). - dont_touch for retiming || carry options. - lpm_type for WYSIWYG */ - - parameter lut_mask = 16'hFFFF; - parameter dont_touch = "off"; - parameter lpm_type = "cyclone10lp_lcell_comb"; - parameter sum_lutc_input = "datac"; - - reg [1:0] lut_type; - reg cout_rt; - reg combout_rt; - wire dataa_w; - wire datab_w; - wire datac_w; - wire datad_w; - wire cin_w; - - assign dataa_w = dataa; - assign datab_w = datab; - assign datac_w = datac; - assign datad_w = datad; - - function lut_data; - input [15:0] mask; - input dataa, datab, datac, datad; - reg [7:0] s3; - reg [3:0] s2; - reg [1:0] s1; - begin - s3 = datad ? mask[15:8] : mask[7:0]; - s2 = datac ? s3[7:4] : s3[3:0]; - s1 = datab ? s2[3:2] : s2[1:0]; - lut_data = dataa ? s1[1] : s1[0]; - end - - endfunction - - initial begin - if (sum_lutc_input == "datac") lut_type = 0; - else - if (sum_lutc_input == "cin") lut_type = 1; - else begin - $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input); - $finish(); - end - end - - always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin - if (lut_type == 0) begin // logic function - combout_rt = lut_data(lut_mask, dataa_w, datab_w, - datac_w, datad_w); - end - else if (lut_type == 1) begin // arithmetic function - combout_rt = lut_data(lut_mask, dataa_w, datab_w, - cin_w, datad_w); - end - cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0); - end - - assign combout = combout_rt & 1'b1; - assign cout = cout_rt & 1'b1; - -endmodule // cyclone10lp_lcell_comb - -/* Altera D Flip-Flop Primitive */ -module dffeas - (output q, - input d, clk, clrn, prn, ena, - input asdata, aload, sclr, sload); - - // Timing simulation is not covered - parameter power_up="dontcare"; - parameter is_wysiwyg="false"; - - reg q_tmp; - wire reset; - reg [7:0] debug_net; - - assign reset = (prn && sclr && ~clrn && ena); - assign q = q_tmp & 1'b1; - - always @(posedge clk, posedge aload) begin - if(reset) q_tmp <= 0; - else q_tmp <= d; - end - assign q = q_tmp; - -endmodule // dffeas diff --git a/techlibs/intel/cyclone10lp/cells_arith.v b/techlibs/intel/cyclone10lp/cells_arith.v new file mode 100644 index 000000000..5ae8d6cea --- /dev/null +++ b/techlibs/intel/cyclone10lp/cells_arith.v @@ -0,0 +1,65 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// NOTE: This is still WIP. +(* techmap_celltype = "$alu" *) +module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + //output [Y_WIDTH-1:0] CO; + output CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + //wire [Y_WIDTH:0] C = {CO, CI}; + wire [Y_WIDTH+1:0] COx; + wire [Y_WIDTH+1:0] C = {COx, CI}; + + /* Start implementation */ + (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice + if(i==Y_WIDTH-1) begin + (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); + assign CO = COx[Y_WIDTH]; + end + else + cyclone10lp_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); + end: slice + endgenerate + /* End implementation */ + assign X = AA ^ BB; + +endmodule diff --git a/techlibs/intel/cyclone10lp/cells_map.v b/techlibs/intel/cyclone10lp/cells_map.v new file mode 100644 index 000000000..c2f6f403c --- /dev/null +++ b/techlibs/intel/cyclone10lp/cells_map.v @@ -0,0 +1,109 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. + +// Normal mode DFF negedge clk, negedge reset +module \$_DFF_N_ (input D, C, output Q); + parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule +// Normal mode DFF +module \$_DFF_P_ (input D, C, output Q); + parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule + +// Async Active Low Reset DFF +module \$_DFF_PN0_ (input D, C, R, output Q); + parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule +// Async Active High Reset DFF +module \$_DFF_PP0_ (input D, C, R, output Q); + parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; + wire R_i = ~ R; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule + +module \$__DFFE_PP0 (input D, C, E, R, output Q); + parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; + wire E_i = ~ E; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); +endmodule + +// Input buffer map +module \$__inpad (input I, output O); + cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); +endmodule + +// Output buffer map +module \$__outpad (input I, output O); + cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); +endmodule + +// LUT Map +/* 0 -> datac + 1 -> cin */ +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; + generate + if (WIDTH == 1) begin + assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function + end else + if (WIDTH == 2) begin + cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), + .datac(1'b1), + .datad(1'b1)); + end else + if(WIDTH == 3) begin + cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), + .datac(A[2]), + .datad(1'b1)); + end else + if(WIDTH == 4) begin + cyclone10lp_lcell_comb #(.lut_mask(LUT), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), + .datac(A[2]), + .datad(A[3])); + end else + wire _TECHMAP_FAIL_ = 1; + endgenerate + +endmodule + + diff --git a/techlibs/intel/cyclone10lp/cells_sim.v b/techlibs/intel/cyclone10lp/cells_sim.v new file mode 100644 index 000000000..f5a8aee2b --- /dev/null +++ b/techlibs/intel/cyclone10lp/cells_sim.v @@ -0,0 +1,137 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +module VCC (output V); + assign V = 1'b1; +endmodule // VCC + +module GND (output G); + assign G = 1'b0; +endmodule // GND + +/* Altera Cyclone 10 LP devices Input Buffer Primitive */ +module cyclone10lp_io_ibuf + (output o, input i, input ibar); + assign ibar = ibar; + assign o = i; +endmodule // cyclone10lp_io_ibuf + +/* Altera Cyclone 10 LP devices Output Buffer Primitive */ +module cyclone10lp_io_obuf + (output o, input i, input oe); + assign o = i; + assign oe = oe; +endmodule // cyclone10lp_io_obuf + +/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */ +module cyclone10lp_lcell_comb + (output combout, cout, + input dataa, datab, datac, datad, cin); + + /* Internal parameters which define the behaviour + of the LUT primitive. + lut_mask define the lut function, can be expressed in 16-digit bin or hex. + sum_lutc_input define the type of LUT (combinational | arithmetic). + dont_touch for retiming || carry options. + lpm_type for WYSIWYG */ + + parameter lut_mask = 16'hFFFF; + parameter dont_touch = "off"; + parameter lpm_type = "cyclone10lp_lcell_comb"; + parameter sum_lutc_input = "datac"; + + reg [1:0] lut_type; + reg cout_rt; + reg combout_rt; + wire dataa_w; + wire datab_w; + wire datac_w; + wire datad_w; + wire cin_w; + + assign dataa_w = dataa; + assign datab_w = datab; + assign datac_w = datac; + assign datad_w = datad; + + function lut_data; + input [15:0] mask; + input dataa, datab, datac, datad; + reg [7:0] s3; + reg [3:0] s2; + reg [1:0] s1; + begin + s3 = datad ? mask[15:8] : mask[7:0]; + s2 = datac ? s3[7:4] : s3[3:0]; + s1 = datab ? s2[3:2] : s2[1:0]; + lut_data = dataa ? s1[1] : s1[0]; + end + + endfunction + + initial begin + if (sum_lutc_input == "datac") lut_type = 0; + else + if (sum_lutc_input == "cin") lut_type = 1; + else begin + $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input); + $finish(); + end + end + + always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin + if (lut_type == 0) begin // logic function + combout_rt = lut_data(lut_mask, dataa_w, datab_w, + datac_w, datad_w); + end + else if (lut_type == 1) begin // arithmetic function + combout_rt = lut_data(lut_mask, dataa_w, datab_w, + cin_w, datad_w); + end + cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0); + end + + assign combout = combout_rt & 1'b1; + assign cout = cout_rt & 1'b1; + +endmodule // cyclone10lp_lcell_comb + +/* Altera D Flip-Flop Primitive */ +module dffeas + (output q, + input d, clk, clrn, prn, ena, + input asdata, aload, sclr, sload); + + // Timing simulation is not covered + parameter power_up="dontcare"; + parameter is_wysiwyg="false"; + + reg q_tmp; + wire reset; + reg [7:0] debug_net; + + assign reset = (prn && sclr && ~clrn && ena); + assign q = q_tmp & 1'b1; + + always @(posedge clk, posedge aload) begin + if(reset) q_tmp <= 0; + else q_tmp <= d; + end + assign q = q_tmp; + +endmodule // dffeas diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index e5dc1adc7..5e6d2df2c 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,10 +36,10 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); + log(" -family \n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); - log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); + log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); log(" Cyclone V and Arria 10 GX devices are experimental.\n"); log("\n"); log(" -top \n"); @@ -152,7 +152,7 @@ struct SynthIntelPass : public ScriptPass { family_opt != "cyclonev" && family_opt != "cycloneiv" && family_opt != "cycloneive" && - family_opt != "cyclone10") + family_opt != "cyclone10lp") log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); -- cgit v1.2.3 From 85a14895ca31ec8c34bf5c296a5740a798b06693 Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Tue, 10 Dec 2019 13:40:32 +0000 Subject: synth_intel: a10gx -> arria10gx --- techlibs/intel/Makefile.inc | 2 +- techlibs/intel/a10gx/cells_arith.v | 65 ---------------------------------- techlibs/intel/a10gx/cells_map.v | 53 --------------------------- techlibs/intel/a10gx/cells_sim.v | 59 ------------------------------ techlibs/intel/arria10gx/cells_arith.v | 65 ++++++++++++++++++++++++++++++++++ techlibs/intel/arria10gx/cells_map.v | 53 +++++++++++++++++++++++++++ techlibs/intel/arria10gx/cells_sim.v | 59 ++++++++++++++++++++++++++++++ techlibs/intel/synth_intel.cc | 6 ++-- 8 files changed, 181 insertions(+), 181 deletions(-) delete mode 100644 techlibs/intel/a10gx/cells_arith.v delete mode 100644 techlibs/intel/a10gx/cells_map.v delete mode 100644 techlibs/intel/a10gx/cells_sim.v create mode 100644 techlibs/intel/arria10gx/cells_arith.v create mode 100644 techlibs/intel/arria10gx/cells_map.v create mode 100644 techlibs/intel/arria10gx/cells_sim.v (limited to 'techlibs') diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 92a83b5af..d97a9b58f 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k. $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) # Add the cell models and mappings for the VQM backend -families := max10 a10gx cyclonev cyclone10lp cycloneiv cycloneive +families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) diff --git a/techlibs/intel/a10gx/cells_arith.v b/techlibs/intel/a10gx/cells_arith.v deleted file mode 100644 index 89fb4561f..000000000 --- a/techlibs/intel/a10gx/cells_arith.v +++ /dev/null @@ -1,65 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// NOTE: This is still WIP. -(* techmap_celltype = "$alu" *) -module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - input [A_WIDTH-1:0] A; - input [B_WIDTH-1:0] B; - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - //output [Y_WIDTH-1:0] CO; - output CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; - - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - wire [Y_WIDTH-1:0] AA = A_buf; - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - //wire [Y_WIDTH:0] C = {CO, CI}; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; - - /* Start implementation */ - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - - genvar i; - generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); - assign CO = COx[Y_WIDTH]; - end - else - fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); - end: slice - endgenerate - /* End implementation */ - assign X = AA ^ BB; - -endmodule diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/a10gx/cells_map.v deleted file mode 100644 index 1430e8551..000000000 --- a/techlibs/intel/a10gx/cells_map.v +++ /dev/null @@ -1,53 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -// Input buffer map -module \$__inpad (input I, output O); - twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); -endmodule - -// Output buffer map -module \$__outpad (input I, output O); - twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); -endmodule - -// LUT Map -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - input [WIDTH-1:0] A; - output Y; - generate - if (WIDTH == 1) begin - assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end else - if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); - end /*else - if(WIDTH == 3) begin - fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1)); - end else - if(WIDTH == 4) begin - fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3])); - end*/ else - wire _TECHMAP_FAIL_ = 1; - endgenerate -endmodule // - - diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/a10gx/cells_sim.v deleted file mode 100644 index e892b377e..000000000 --- a/techlibs/intel/a10gx/cells_sim.v +++ /dev/null @@ -1,59 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -module VCC (output V); - assign V = 1'b1; -endmodule // VCC - -module GND (output G); - assign G = 1'b0; -endmodule // GND - -/* Altera Arria 10 GX devices Input Buffer Primitive */ -module twentynm_io_ibuf (output o, input i, input ibar); - assign ibar = ibar; - assign o = i; -endmodule // twentynm_io_ibuf - -/* Altera Arria 10 GX devices Output Buffer Primitive */ -module twentynm_io_obuf (output o, input i, input oe); - assign o = i; - assign oe = oe; -endmodule // twentynm_io_obuf - -/* Altera Arria 10 GX LUT Primitive */ -module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, - input datae, dataf, datag, cin, - input sharein); - -parameter lut_mask = 64'hFFFFFFFFFFFFFFFF; -parameter dont_touch = "off"; -parameter lpm_type = "twentynm_lcell_comb"; -parameter shared_arith = "off"; -parameter extended_lut = "off"; - -// TODO: This is still WIP -initial begin - $display("Simulation model is still under investigation\n"); -end - -endmodule // twentynm_lcell_comb - - - diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v new file mode 100644 index 000000000..89fb4561f --- /dev/null +++ b/techlibs/intel/arria10gx/cells_arith.v @@ -0,0 +1,65 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// NOTE: This is still WIP. +(* techmap_celltype = "$alu" *) +module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + //output [Y_WIDTH-1:0] CO; + output CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + //wire [Y_WIDTH:0] C = {CO, CI}; + wire [Y_WIDTH+1:0] COx; + wire [Y_WIDTH+1:0] C = {COx, CI}; + + /* Start implementation */ + (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice + if(i==Y_WIDTH-1) begin + (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); + assign CO = COx[Y_WIDTH]; + end + else + fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); + end: slice + endgenerate + /* End implementation */ + assign X = AA ^ BB; + +endmodule diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v new file mode 100644 index 000000000..1430e8551 --- /dev/null +++ b/techlibs/intel/arria10gx/cells_map.v @@ -0,0 +1,53 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +// Input buffer map +module \$__inpad (input I, output O); + twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); +endmodule + +// Output buffer map +module \$__outpad (input I, output O); + twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); +endmodule + +// LUT Map +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; + generate + if (WIDTH == 1) begin + assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function + end else + if (WIDTH == 2) begin + twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); + end /*else + if(WIDTH == 3) begin + fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1)); + end else + if(WIDTH == 4) begin + fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3])); + end*/ else + wire _TECHMAP_FAIL_ = 1; + endgenerate +endmodule // + + diff --git a/techlibs/intel/arria10gx/cells_sim.v b/techlibs/intel/arria10gx/cells_sim.v new file mode 100644 index 000000000..e892b377e --- /dev/null +++ b/techlibs/intel/arria10gx/cells_sim.v @@ -0,0 +1,59 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +module VCC (output V); + assign V = 1'b1; +endmodule // VCC + +module GND (output G); + assign G = 1'b0; +endmodule // GND + +/* Altera Arria 10 GX devices Input Buffer Primitive */ +module twentynm_io_ibuf (output o, input i, input ibar); + assign ibar = ibar; + assign o = i; +endmodule // twentynm_io_ibuf + +/* Altera Arria 10 GX devices Output Buffer Primitive */ +module twentynm_io_obuf (output o, input i, input oe); + assign o = i; + assign oe = oe; +endmodule // twentynm_io_obuf + +/* Altera Arria 10 GX LUT Primitive */ +module twentynm_lcell_comb (output combout, cout, sumout, + input dataa, datab, datac, datad, + input datae, dataf, datag, cin, + input sharein); + +parameter lut_mask = 64'hFFFFFFFFFFFFFFFF; +parameter dont_touch = "off"; +parameter lpm_type = "twentynm_lcell_comb"; +parameter shared_arith = "off"; +parameter extended_lut = "off"; + +// TODO: This is still WIP +initial begin + $display("Simulation model is still under investigation\n"); +end + +endmodule // twentynm_lcell_comb + + + diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 5e6d2df2c..c8c690e45 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family \n"); + log(" -family \n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); @@ -148,7 +148,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); if (family_opt != "max10" && - family_opt != "a10gx" && + family_opt != "arria10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && family_opt != "cycloneive" && @@ -214,7 +214,7 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_luts")) { - if (family_opt == "a10gx" || family_opt == "cyclonev") + if (family_opt == "arria10gx" || family_opt == "cyclonev") run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -lut 4" + string(retime ? " -dff" : "")); -- cgit v1.2.3 From f022645cd2564ef47a6e8cf80c1452cd25f7ace2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Dec 2019 13:02:07 -0800 Subject: Fix bitwidth mismatch; suppresses iverilog warning --- techlibs/ecp5/cells_ff.vh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh index 501c1b3b2..6b745f391 100644 --- a/techlibs/ecp5/cells_ff.vh +++ b/techlibs/ecp5/cells_ff.vh @@ -1,12 +1,12 @@ // Diamond flip-flops -module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .CE(SP), .DI(D), .Q(Q)); endmodule -module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .DI(D), .Q(Q)); endmodule -module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .DI(D), .Q(Q)); endmodule +module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule +module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule -- cgit v1.2.3 From 937ec1ee78e5470c148d8c39387c7a80711af8a7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 13:50:36 -0600 Subject: Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index ee961fff8..87e659bbc 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -73,7 +73,7 @@ bram $__XILINX_RAMB18_TDP endbram match $__XILINX_RAMB36_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -89,7 +89,7 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp -- cgit v1.2.3 From 3bd623bb05c0be74b024f5635e754e794bd6316c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 14:33:33 -0800 Subject: synth_xilinx: error out if tristate without '-iopad' --- techlibs/xilinx/synth_xilinx.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2c5686a35..6dd769055 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -306,6 +306,10 @@ struct SynthXilinxPass : public ScriptPass run("proc"); if (flatten || help_mode) run("flatten", "(with '-flatten')"); + active_design->scratchpad_unset("tribuf.added_something"); + run("tribuf -logic"); + if (!do_iopad && active_design->scratchpad_get_bool("tribuf.added_something")) + log_error("Tristate buffers are unsupported without the '-iopad' option.\n"); run("tribuf -logic"); run("deminout"); run("opt_expr"); -- cgit v1.2.3 From 3eed8835b5911c4c635e0cade0978987c09c7ab5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 14:56:15 -0800 Subject: abc9_map.v: fix Xilinx LUTRAM --- techlibs/xilinx/abc9_map.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 49000ea25..d04cdb5eb 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -393,8 +393,8 @@ module RAM32X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4) ); - \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO)); - \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO)); + \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO)); + \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); endmodule module RAM64X1D ( @@ -416,8 +416,8 @@ module RAM64X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5) ); - \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO)); - \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO)); + \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO)); + \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); endmodule module RAM128X1D ( @@ -438,8 +438,8 @@ module RAM128X1D ( .A(A), .DPRA(DPRA) ); - \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO)); \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO)); + \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO)); endmodule module SRL16E ( @@ -455,7 +455,7 @@ module SRL16E ( .Q(\$Q ), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) ); - \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q)); + \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); endmodule module SRLC32E ( -- cgit v1.2.3 From 9ab1feeaf11adb6b675ac4034e246cb137d07db9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 14:56:15 -0800 Subject: abc9_map.v: fix Xilinx LUTRAM --- techlibs/xilinx/abc9_map.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 0eac08f3f..6fd73c1e0 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -39,8 +39,8 @@ module RAM32X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4) ); - \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO)); - \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO)); + \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO)); + \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); endmodule module RAM64X1D ( @@ -62,8 +62,8 @@ module RAM64X1D ( .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5) ); - \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO)); - \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO)); + \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO)); + \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); endmodule module RAM128X1D ( @@ -84,8 +84,8 @@ module RAM128X1D ( .A(A), .DPRA(DPRA) ); - \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO)); \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO)); + \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO)); endmodule module SRL16E ( @@ -101,7 +101,7 @@ module SRL16E ( .Q(\$Q ), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) ); - \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q)); + \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); endmodule module SRLC32E ( -- cgit v1.2.3 From 751a18d7e974123352e372c75bb17226e6fabec0 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 17:32:58 -0600 Subject: Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. --- techlibs/xilinx/xc7_xcu_brams.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 87e659bbc..b7c893ff7 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -1,4 +1,3 @@ - bram $__XILINX_RAMB36_SDP init 1 abits 9 @@ -72,6 +71,11 @@ bram $__XILINX_RAMB18_TDP clkpol 2 3 endbram +# The "min bits" value were taken from: +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. +# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf + match $__XILINX_RAMB36_SDP min bits 1024 min efficiency 5 @@ -102,7 +106,3 @@ match $__XILINX_RAMB18_TDP shuffle_enable B make_transp endmatch - -# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), -# v1.14 ed., p 29-30, July, 2019. - -- cgit v1.2.3 From 7a9d1be97d100c265530270810071e2e9e676b3e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 17:44:59 -0800 Subject: Add memory rules for RAM16X1D, RAM32M, RAM64M --- techlibs/xilinx/lutrams.txt | 64 ++++++++++++++++++++++++++ techlibs/xilinx/lutrams_map.v | 104 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 2613c206c..3e260b0d7 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM32X1D init 1 abits 5 @@ -38,6 +51,41 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram + +bram $__XILINX_RAM32M + init 1 + abits 5 + dbits 2 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64M + init 1 + abits 6 + dbits 1 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +match $__XILINX_RAM16X1D + min bits 2 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM32X1D min bits 3 min wports 1 @@ -56,5 +104,21 @@ match $__XILINX_RAM128X1D min bits 9 min wports 1 make_outreg + or_next_if_better +endmatch + + +match $__XILINX_RAM32M + min bits 5 + min rports 3 + min wports 1 + make_outreg + or_next_if_better endmatch +match $__XILINX_RAM64M + min bits 5 + min rports 3 + min wports 1 + make_outreg +endmatch diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index 77041ca86..985e53ff4 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -1,4 +1,36 @@ +module \$__XILINX_RAM16X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [15:0] INIT = 16'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output A1DATA; + + input [3:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM16X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); parameter [31:0] INIT = 32'bx; parameter CLKPOL2 = 1; @@ -95,3 +127,75 @@ module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); ); endmodule + +module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); + parameter [31:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR, A2ADDR, A3ADDR; + output [1:0] A1DATA, A2DATA, A3DATA; + + input [4:0] B1ADDR; + input [1:0] B1DATA; + input B1EN; + + RAM32M #( + .INIT_A(INIT), + .INIT_B(INIT), + .INIT_C(INIT), + .INIT_D(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A2ADDR), + .ADDRC(A3ADDR), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), + + .ADDRD(B1ADDR), + .DIA(B1DATA), + .DIB(B1DATA), + .DIC(B1DATA), + .DID(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [5:0] A1ADDR, A2ADDR, A3ADDR; + output A1DATA, A2DATA, A3DATA; + + input [5:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM64M #( + .INIT_A(INIT), + .INIT_B(INIT), + .INIT_C(INIT), + .INIT_D(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A2ADDR), + .ADDRC(A3ADDR), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), + + .ADDRD(B1ADDR), + .DIA(B1DATA), + .DIB(B1DATA), + .DIC(B1DATA), + .DID(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule -- cgit v1.2.3 From 50e0c835606a94c825079a63fc026c906c9985e0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 18:52:03 -0800 Subject: Fix RAM64M model to have 6 bit address bus --- techlibs/xilinx/cells_sim.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3ed0759db..56eb782c6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1185,10 +1185,10 @@ module RAM64M ( output DOB, output DOC, output DOD, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, input DIA, input DIB, input DIC, -- cgit v1.2.3 From 8925bf4b9639e1604eb3fd9a298d9f1138093a56 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 18:52:28 -0800 Subject: Add RAM32X6SDP and RAM64X3SDP modes --- techlibs/xilinx/lutrams.txt | 40 ++++++++++++++++++++ techlibs/xilinx/lutrams_map.v | 88 +++++++++++++++++++++++++++++++++++++++---- 2 files changed, 120 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 3e260b0d7..be764a63f 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -52,6 +52,32 @@ bram $__XILINX_RAM128X1D endbram +bram $__XILINX_RAM32X6SDP + init 1 + abits 5 + dbits 6 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X3SDP + init 1 + abits 6 + dbits 3 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM32M init 1 abits 5 @@ -108,6 +134,20 @@ match $__XILINX_RAM128X1D endmatch +match $__XILINX_RAM32X6SDP + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X3SDP + min bits 6 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM32M min bits 5 min rports 3 diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index 985e53ff4..d01508de5 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -128,8 +128,80 @@ module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); endmodule +module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [32*6-1:0] INIT = {32*6{1'bx}}; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR; + output [5:0] A1DATA; + + input [4:0] B1ADDR; + input [5:0] B1DATA; + input B1EN; + + RAM32M #( + .INIT_A({INIT[187:186], INIT[181:180], INIT[175:174], INIT[169:168], INIT[163:162], INIT[157:156], INIT[151:150], INIT[145:144], INIT[139:138], INIT[133:132], INIT[127:126], INIT[121:120], INIT[115:114], INIT[109:108], INIT[103:102], INIT[ 97: 96], INIT[ 91: 90], INIT[ 85: 84], INIT[ 79: 78], INIT[ 73: 72], INIT[ 67: 66], INIT[ 61: 60], INIT[ 55: 54], INIT[ 49: 48], INIT[ 43: 42], INIT[ 37: 36], INIT[ 31: 30], INIT[ 25: 24], INIT[ 19: 18], INIT[ 13: 12], INIT[ 7: 6], INIT[ 1: 0]}), + .INIT_B({INIT[189:188], INIT[183:182], INIT[177:176], INIT[171:170], INIT[165:164], INIT[159:158], INIT[153:152], INIT[147:146], INIT[141:140], INIT[135:134], INIT[129:128], INIT[123:122], INIT[117:116], INIT[111:110], INIT[105:104], INIT[ 99: 98], INIT[ 93: 92], INIT[ 87: 86], INIT[ 81: 80], INIT[ 75: 74], INIT[ 69: 68], INIT[ 63: 62], INIT[ 57: 56], INIT[ 51: 50], INIT[ 45: 44], INIT[ 39: 38], INIT[ 33: 32], INIT[ 27: 26], INIT[ 21: 20], INIT[ 15: 14], INIT[ 9: 8], INIT[ 3: 2]}), + .INIT_C({INIT[191:190], INIT[185:184], INIT[179:178], INIT[173:172], INIT[167:166], INIT[161:160], INIT[155:154], INIT[149:148], INIT[143:142], INIT[137:136], INIT[131:130], INIT[125:124], INIT[119:118], INIT[113:112], INIT[107:106], INIT[101:100], INIT[ 95: 94], INIT[ 89: 88], INIT[ 83: 82], INIT[ 77: 76], INIT[ 71: 70], INIT[ 65: 64], INIT[ 59: 58], INIT[ 53: 52], INIT[ 47: 46], INIT[ 41: 40], INIT[ 35: 34], INIT[ 29: 28], INIT[ 23: 22], INIT[ 17: 16], INIT[ 11: 10], INIT[ 5: 4]}), + .INIT_D(64'bx), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A1ADDR), + .ADDRC(A1ADDR), + .DOA(A1DATA[1:0]), + .DOB(A1DATA[3:2]), + .DOC(A1DATA[5:4]), + + .ADDRD(B1ADDR), + .DIA(B1DATA[1:0]), + .DIB(B1DATA[3:2]), + .DIC(B1DATA[5:4]), + .DID(), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [64*3-1:0] INIT = {64*3{1'bx}}; + parameter CLKPOL2 = 1; + input CLK1; + + input [5:0] A1ADDR; + output [2:0] A1DATA; + + input [5:0] B1ADDR; + input [2:0] B1DATA; + input B1EN; + + RAM64M #( + .INIT_A({INIT[189], INIT[186], INIT[183], INIT[180], INIT[177], INIT[174], INIT[171], INIT[168], INIT[165], INIT[162], INIT[159], INIT[156], INIT[153], INIT[150], INIT[147], INIT[144], INIT[141], INIT[138], INIT[135], INIT[132], INIT[129], INIT[126], INIT[123], INIT[120], INIT[117], INIT[114], INIT[111], INIT[108], INIT[105], INIT[102], INIT[ 99], INIT[ 96], INIT[ 93], INIT[ 90], INIT[ 87], INIT[ 84], INIT[ 81], INIT[ 78], INIT[ 75], INIT[ 72], INIT[ 69], INIT[ 66], INIT[ 63], INIT[ 60], INIT[ 57], INIT[ 54], INIT[ 51], INIT[ 48], INIT[ 45], INIT[ 42], INIT[ 39], INIT[ 36], INIT[ 33], INIT[ 30], INIT[ 27], INIT[ 24], INIT[ 21], INIT[ 18], INIT[ 15], INIT[ 12], INIT[ 9], INIT[ 6], INIT[ 3], INIT[ 0]}), + .INIT_B({INIT[190], INIT[187], INIT[184], INIT[181], INIT[178], INIT[175], INIT[172], INIT[169], INIT[166], INIT[163], INIT[160], INIT[157], INIT[154], INIT[151], INIT[148], INIT[145], INIT[142], INIT[139], INIT[136], INIT[133], INIT[130], INIT[127], INIT[124], INIT[121], INIT[118], INIT[115], INIT[112], INIT[109], INIT[106], INIT[103], INIT[100], INIT[ 97], INIT[ 94], INIT[ 91], INIT[ 88], INIT[ 85], INIT[ 82], INIT[ 79], INIT[ 76], INIT[ 73], INIT[ 70], INIT[ 67], INIT[ 64], INIT[ 61], INIT[ 58], INIT[ 55], INIT[ 52], INIT[ 49], INIT[ 46], INIT[ 43], INIT[ 40], INIT[ 37], INIT[ 34], INIT[ 31], INIT[ 28], INIT[ 25], INIT[ 22], INIT[ 19], INIT[ 16], INIT[ 13], INIT[ 10], INIT[ 7], INIT[ 4], INIT[ 1]}), + .INIT_C({INIT[191], INIT[188], INIT[185], INIT[182], INIT[179], INIT[176], INIT[173], INIT[170], INIT[167], INIT[164], INIT[161], INIT[158], INIT[155], INIT[152], INIT[149], INIT[146], INIT[143], INIT[140], INIT[137], INIT[134], INIT[131], INIT[128], INIT[125], INIT[122], INIT[119], INIT[116], INIT[113], INIT[110], INIT[107], INIT[104], INIT[101], INIT[ 98], INIT[ 95], INIT[ 92], INIT[ 89], INIT[ 86], INIT[ 83], INIT[ 80], INIT[ 77], INIT[ 74], INIT[ 71], INIT[ 68], INIT[ 65], INIT[ 62], INIT[ 59], INIT[ 56], INIT[ 53], INIT[ 50], INIT[ 47], INIT[ 44], INIT[ 41], INIT[ 38], INIT[ 35], INIT[ 32], INIT[ 29], INIT[ 26], INIT[ 23], INIT[ 20], INIT[ 17], INIT[ 14], INIT[ 11], INIT[ 8], INIT[ 5], INIT[ 2]}), + .INIT_D(64'bx), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .ADDRA(A1ADDR), + .ADDRB(A1ADDR), + .ADDRC(A1ADDR), + .DOA(A1DATA[0]), + .DOB(A1DATA[1]), + .DOC(A1DATA[2]), + + .ADDRD(B1ADDR), + .DIA(B1DATA[0]), + .DIB(B1DATA[1]), + .DIC(B1DATA[2]), + .DID(), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); - parameter [31:0] INIT = 32'bx; + parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; @@ -150,9 +222,9 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, .ADDRA(A1ADDR), .ADDRB(A2ADDR), .ADDRC(A3ADDR), - .DOA(A1DATA), - .DOB(A2DATA), - .DOC(A3DATA), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), .ADDRD(B1ADDR), .DIA(B1DATA), @@ -165,7 +237,7 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, endmodule module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); - parameter [63:0] INIT = 32'bx; + parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; @@ -186,9 +258,9 @@ module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, .ADDRA(A1ADDR), .ADDRB(A2ADDR), .ADDRC(A3ADDR), - .DOA(A1DATA), - .DOB(A2DATA), - .DOC(A3DATA), + .DOA(A1DATA), + .DOB(A2DATA), + .DOC(A3DATA), .ADDRD(B1ADDR), .DIA(B1DATA), -- cgit v1.2.3 From dd7d2d8db615f7d54d9bbee257fad9fb11bdc9f8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 08:51:05 -0800 Subject: Duplicate tribuf call, credit to @mwkmwkmwk --- techlibs/xilinx/synth_xilinx.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6dd769055..640659ad6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -310,7 +310,6 @@ struct SynthXilinxPass : public ScriptPass run("tribuf -logic"); if (!do_iopad && active_design->scratchpad_get_bool("tribuf.added_something")) log_error("Tristate buffers are unsupported without the '-iopad' option.\n"); - run("tribuf -logic"); run("deminout"); run("opt_expr"); run("opt_clean"); -- cgit v1.2.3 From d6514fc2e13976b15be396f413b046deb6f0c9fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 08:54:19 -0800 Subject: RAM64M8 to also have [5:0] for address --- techlibs/xilinx/cells_sim.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 56eb782c6..f9ce496ff 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1230,14 +1230,14 @@ module RAM64M8 ( output DOF, output DOG, output DOH, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, - input [4:0] ADDRE, - input [4:0] ADDRF, - input [4:0] ADDRG, - input [4:0] ADDRH, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, + input [5:0] ADDRE, + input [5:0] ADDRF, + input [5:0] ADDRG, + input [5:0] ADDRH, input DIA, input DIB, input DIC, -- cgit v1.2.3 From c3262d60752bb20ff5cd54bc4ee6f56e2b772b05 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 08:59:17 -0800 Subject: Disable RAM16X1D match rule; carry-over from LUT4 arches --- techlibs/xilinx/lutrams.txt | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index be764a63f..ae629bce8 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -105,12 +105,15 @@ bram $__XILINX_RAM64M endbram -match $__XILINX_RAM16X1D - min bits 2 - min wports 1 - make_outreg - or_next_if_better -endmatch +# Disabled for now, pending support for LUT4 arches +# since on LUT6 arches this occupies same area as +# a RAM32X1D +#match $__XILINX_RAM16X1D +# min bits 2 +# min wports 1 +# make_outreg +# or_next_if_better +#endmatch match $__XILINX_RAM32X1D min bits 3 -- cgit v1.2.3 From 266993408a2b926ffefcf536feb92b36b11e398e Mon Sep 17 00:00:00 2001 From: Diego H Date: Fri, 13 Dec 2019 15:43:24 -0600 Subject: Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific --- techlibs/xilinx/xc7_xcu_brams.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index b7c893ff7..a52dd9352 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,6 +81,7 @@ match $__XILINX_RAMB36_SDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block or_next_if_better endmatch @@ -89,6 +90,14 @@ match $__XILINX_RAMB18_SDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block + or_next_if_better +endmatch + +match $__XILINX_RAMB18_SDP + shuffle_enable B + make_transp + attribute ram_block=1 ram_style=block or_next_if_better endmatch @@ -97,6 +106,7 @@ match $__XILINX_RAMB36_TDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block or_next_if_better endmatch @@ -105,4 +115,13 @@ match $__XILINX_RAMB18_TDP min efficiency 5 shuffle_enable B make_transp + attribute !ram_style !logic_block + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + min efficiency 5 + shuffle_enable B + make_transp + attribute ram_block=1 ram_style=block endmatch -- cgit v1.2.3 From b35559fc335181d7c8f8046fa17bf05550c21ba7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Sun, 15 Dec 2019 23:33:09 -0600 Subject: Merging attribute rules into a single match block; Adding tests --- techlibs/xilinx/xc7_xcu_brams.txt | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index a52dd9352..2d94ac4a8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,51 +77,45 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block or_next_if_better endmatch match $__XILINX_RAMB18_SDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block - or_next_if_better -endmatch - -match $__XILINX_RAMB18_SDP - shuffle_enable B - make_transp - attribute ram_block=1 ram_style=block or_next_if_better endmatch match $__XILINX_RAMB36_TDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block or_next_if_better endmatch match $__XILINX_RAMB18_TDP + attribute ram_style=block ram_block=1 + attribute !ram_style=distributed + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp - attribute !ram_style !logic_block - or_next_if_better endmatch -match $__XILINX_RAMB18_TDP - min efficiency 5 - shuffle_enable B - make_transp - attribute ram_block=1 ram_style=block -endmatch -- cgit v1.2.3 From f3f59910eb06bf74a2a4b8157797a327dd097451 Mon Sep 17 00:00:00 2001 From: Diego H Date: Sun, 15 Dec 2019 23:51:58 -0600 Subject: Removing fixed attribute value to !ramstyle rules --- techlibs/xilinx/xc7_xcu_brams.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 2d94ac4a8..1374a0a36 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -78,7 +78,7 @@ endbram match $__XILINX_RAMB36_SDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -89,7 +89,7 @@ endmatch match $__XILINX_RAMB18_SDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -100,7 +100,7 @@ endmatch match $__XILINX_RAMB36_TDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -111,7 +111,7 @@ endmatch match $__XILINX_RAMB18_TDP attribute ram_style=block ram_block=1 - attribute !ram_style=distributed + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 -- cgit v1.2.3 From c4d37813cb112d7f3717049d7cf4e6e6b0456fbb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 10:41:13 -0800 Subject: Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q --- techlibs/xilinx/lutrams.txt | 8 ++++---- techlibs/xilinx/lutrams_map.v | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index ae629bce8..29f6b05cc 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -78,7 +78,7 @@ bram $__XILINX_RAM64X3SDP clkpol 0 2 endbram -bram $__XILINX_RAM32M +bram $__XILINX_RAM32X2Q init 1 abits 5 dbits 2 @@ -91,7 +91,7 @@ bram $__XILINX_RAM32M clkpol 0 2 endbram -bram $__XILINX_RAM64M +bram $__XILINX_RAM64X1Q init 1 abits 6 dbits 1 @@ -151,7 +151,7 @@ match $__XILINX_RAM64X3SDP or_next_if_better endmatch -match $__XILINX_RAM32M +match $__XILINX_RAM32X2Q min bits 5 min rports 3 min wports 1 @@ -159,7 +159,7 @@ match $__XILINX_RAM32M or_next_if_better endmatch -match $__XILINX_RAM64M +match $__XILINX_RAM64X1Q min bits 5 min rports 3 min wports 1 diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index d01508de5..884f709ab 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -200,7 +200,7 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); ); endmodule -module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAM32X2Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; @@ -236,7 +236,7 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, ); endmodule -module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); +module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN); parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; input CLK1; -- cgit v1.2.3 From 7545ab3814a01047698f45739a04437045248da3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 11:56:26 -0800 Subject: Populate DID/DOD even if unused --- techlibs/xilinx/lutrams_map.v | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v index d01508de5..47424aa73 100644 --- a/techlibs/xilinx/lutrams_map.v +++ b/techlibs/xilinx/lutrams_map.v @@ -140,6 +140,8 @@ module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [5:0] B1DATA; input B1EN; + wire [1:0] DOD_unused; + RAM32M #( .INIT_A({INIT[187:186], INIT[181:180], INIT[175:174], INIT[169:168], INIT[163:162], INIT[157:156], INIT[151:150], INIT[145:144], INIT[139:138], INIT[133:132], INIT[127:126], INIT[121:120], INIT[115:114], INIT[109:108], INIT[103:102], INIT[ 97: 96], INIT[ 91: 90], INIT[ 85: 84], INIT[ 79: 78], INIT[ 73: 72], INIT[ 67: 66], INIT[ 61: 60], INIT[ 55: 54], INIT[ 49: 48], INIT[ 43: 42], INIT[ 37: 36], INIT[ 31: 30], INIT[ 25: 24], INIT[ 19: 18], INIT[ 13: 12], INIT[ 7: 6], INIT[ 1: 0]}), .INIT_B({INIT[189:188], INIT[183:182], INIT[177:176], INIT[171:170], INIT[165:164], INIT[159:158], INIT[153:152], INIT[147:146], INIT[141:140], INIT[135:134], INIT[129:128], INIT[123:122], INIT[117:116], INIT[111:110], INIT[105:104], INIT[ 99: 98], INIT[ 93: 92], INIT[ 87: 86], INIT[ 81: 80], INIT[ 75: 74], INIT[ 69: 68], INIT[ 63: 62], INIT[ 57: 56], INIT[ 51: 50], INIT[ 45: 44], INIT[ 39: 38], INIT[ 33: 32], INIT[ 27: 26], INIT[ 21: 20], INIT[ 15: 14], INIT[ 9: 8], INIT[ 3: 2]}), @@ -153,12 +155,13 @@ module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOA(A1DATA[1:0]), .DOB(A1DATA[3:2]), .DOC(A1DATA[5:4]), + .DOD(DOD_unused), .ADDRD(B1ADDR), .DIA(B1DATA[1:0]), .DIB(B1DATA[3:2]), .DIC(B1DATA[5:4]), - .DID(), + .DID(2'b00), .WCLK(CLK1), .WE(B1EN) ); @@ -176,6 +179,8 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [2:0] B1DATA; input B1EN; + wire DOD_unused; + RAM64M #( .INIT_A({INIT[189], INIT[186], INIT[183], INIT[180], INIT[177], INIT[174], INIT[171], INIT[168], INIT[165], INIT[162], INIT[159], INIT[156], INIT[153], INIT[150], INIT[147], INIT[144], INIT[141], INIT[138], INIT[135], INIT[132], INIT[129], INIT[126], INIT[123], INIT[120], INIT[117], INIT[114], INIT[111], INIT[108], INIT[105], INIT[102], INIT[ 99], INIT[ 96], INIT[ 93], INIT[ 90], INIT[ 87], INIT[ 84], INIT[ 81], INIT[ 78], INIT[ 75], INIT[ 72], INIT[ 69], INIT[ 66], INIT[ 63], INIT[ 60], INIT[ 57], INIT[ 54], INIT[ 51], INIT[ 48], INIT[ 45], INIT[ 42], INIT[ 39], INIT[ 36], INIT[ 33], INIT[ 30], INIT[ 27], INIT[ 24], INIT[ 21], INIT[ 18], INIT[ 15], INIT[ 12], INIT[ 9], INIT[ 6], INIT[ 3], INIT[ 0]}), .INIT_B({INIT[190], INIT[187], INIT[184], INIT[181], INIT[178], INIT[175], INIT[172], INIT[169], INIT[166], INIT[163], INIT[160], INIT[157], INIT[154], INIT[151], INIT[148], INIT[145], INIT[142], INIT[139], INIT[136], INIT[133], INIT[130], INIT[127], INIT[124], INIT[121], INIT[118], INIT[115], INIT[112], INIT[109], INIT[106], INIT[103], INIT[100], INIT[ 97], INIT[ 94], INIT[ 91], INIT[ 88], INIT[ 85], INIT[ 82], INIT[ 79], INIT[ 76], INIT[ 73], INIT[ 70], INIT[ 67], INIT[ 64], INIT[ 61], INIT[ 58], INIT[ 55], INIT[ 52], INIT[ 49], INIT[ 46], INIT[ 43], INIT[ 40], INIT[ 37], INIT[ 34], INIT[ 31], INIT[ 28], INIT[ 25], INIT[ 22], INIT[ 19], INIT[ 16], INIT[ 13], INIT[ 10], INIT[ 7], INIT[ 4], INIT[ 1]}), @@ -189,12 +194,13 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .DOA(A1DATA[0]), .DOB(A1DATA[1]), .DOC(A1DATA[2]), + .DOD(DOD_unused), .ADDRD(B1ADDR), .DIA(B1DATA[0]), .DIB(B1DATA[1]), .DIC(B1DATA[2]), - .DID(), + .DID(1'b0), .WCLK(CLK1), .WE(B1EN) ); -- cgit v1.2.3 From d910bec8e00b5e9eba2fc62dec1a6b734e429cc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:00:58 -0800 Subject: Update xc7/xcu bram rules --- techlibs/xilinx/xc7_xcu_brams.txt | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 1374a0a36..60425fed9 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,8 +77,7 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 @@ -88,8 +87,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 @@ -99,8 +97,7 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 @@ -110,8 +107,7 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - attribute ram_style=block ram_block=1 - attribute !ram_style + attribute !ram_style ram_style=block ram_block attribute !logic_block min bits 1024 min efficiency 5 -- cgit v1.2.3 From 5a00d5578cea91ce84f3d95e6138c85d1a949b89 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:15 -0800 Subject: Add unconditional match blocks for force RAM --- techlibs/xilinx/xc7_xcu_brams.txt | 40 +++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 60425fed9..c63218ae1 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,7 +77,7 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -86,8 +86,16 @@ match $__XILINX_RAMB36_SDP or_next_if_better endmatch +match $__XILINX_RAMB36_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB18_SDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -96,8 +104,16 @@ match $__XILINX_RAMB18_SDP or_next_if_better endmatch +match $__XILINX_RAMB18_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB36_TDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 @@ -106,12 +122,28 @@ match $__XILINX_RAMB36_TDP or_next_if_better endmatch +match $__XILINX_RAMB36_TDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB18_TDP - attribute !ram_style ram_style=block ram_block + attribute !ram_style attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp endmatch -- cgit v1.2.3 From aff6ad1ce09264fb7fbf43a7456a746a586bea90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Thu, 21 Nov 2019 06:30:06 +0100 Subject: xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. --- techlibs/xilinx/cells_map.v | 27 +++++++++ techlibs/xilinx/synth_xilinx.cc | 15 +++-- techlibs/xilinx/xc6s_ff_map.v | 130 ++++++++++++++++++++++++++++++++++------ techlibs/xilinx/xc7_ff_map.v | 94 ++++++++++++++++++++++++----- 4 files changed, 228 insertions(+), 38 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index de2068bc5..cc180f2b9 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -28,6 +28,33 @@ module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPL (* techmap_celltype = "$_DFF_PN1_" *) module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFE_NN0" *) +module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFE_PN0" *) +module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFE_NN1" *) +module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFE_PN1" *) +module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule + +(* techmap_celltype = "$__DFFS_NN0_" *) +module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$__DFFS_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFS_PN0_" *) +module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$__DFFS_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFS_NN1_" *) +module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$__DFFS_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +(* techmap_celltype = "$__DFFS_PN1_" *) +module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$__DFFS_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule + +(* techmap_celltype = "$__DFFSE_NN0" *) +module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFSE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFSE_PN0" *) +module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFSE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFSE_NN1" *) +module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFSE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule +(* techmap_celltype = "$__DFFSE_PN1" *) +module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFSE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule + module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2c5686a35..a061c8dc0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -444,6 +444,16 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_ffram")) { + // Required for dffsr2dff to work. + run("simplemap t:$dff t:$adff t:$mux"); + // Needs to be done before opt -mux_bool happens. + run("dffsr2dff"); + if (help_mode) + run("dff2dffs [-match-init]", "(-match-init for xc6s only)"); + else if (family == "xc6s") + run("dff2dffs -match-init"); + else + run("dff2dffs"); if (widemux > 0) run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover // performs less efficiently @@ -453,14 +463,11 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("fine")) { - run("dffsr2dff"); - run("dff2dffe"); + run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); if (help_mode) { - run("simplemap t:$mux", " ('-widemux' only)"); run("muxcover , ('-widemux' only)"); } else if (widemux > 0) { - run("simplemap t:$mux"); constexpr int cost_mux2 = 100; std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2); switch (widemux) { diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v index bf35b09e5..c40f446e0 100644 --- a/techlibs/xilinx/xc6s_ff_map.v +++ b/techlibs/xilinx/xc6s_ff_map.v @@ -27,6 +27,8 @@ `ifndef _NO_FFS +// No reset. + module \$_DFF_N_ (input D, C, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -46,6 +48,8 @@ module \$_DFF_P_ (input D, C, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// No reset, enable. + module \$_DFFE_NP_ (input D, C, E, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -65,80 +69,168 @@ module \$_DFFE_PP_ (input D, C, E, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); +// Async reset. + +module \$_DFF_NP0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); else - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NP0_ (input D, C, R, output Q); +module \$_DFF_PP0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); else - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); + +module \$_DFF_NP1_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); + else + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); + else + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Async reset, enable. + +module \$__DFFE_NP0 (input D, C, E, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); else - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); else - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); +module \$__DFFE_NP1 (input D, C, E, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); else - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); +module \$__DFFE_PP1 (input D, C, E, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); else - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset. + +module \$__DFFS_NP0_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); +module \$__DFFS_PP0_ (input D, C, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFS_NP1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); + $error("Spartan 6 doesn't support FFs with set initialized to 0"); else - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); +module \$__DFFS_PP1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); + $error("Spartan 6 doesn't support FFs with set initialized to 0"); else - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); endgenerate wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Sync reset, enable. + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + $error("Spartan 6 doesn't support FFs with reset initialized to 1"); + else + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFSE_NP1 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with set initialized to 0"); + else + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); + parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) + $error("Spartan 6 doesn't support FFs with set initialized to 0"); + else + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches (no reset). + module \$_DLATCH_N_ (input E, D, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) @@ -158,5 +250,7 @@ module \$_DLATCH_P_ (input E, D, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Latches with reset (TODO). + `endif diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v index 32ca9f560..2bd874457 100644 --- a/techlibs/xilinx/xc7_ff_map.v +++ b/techlibs/xilinx/xc7_ff_map.v @@ -37,6 +37,8 @@ `ifndef _NO_FFS +// No reset. + module \$_DFF_N_ (input D, C, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); @@ -48,6 +50,8 @@ module \$_DFF_P_ (input D, C, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// No reset, enable. + module \$_DFFE_NP_ (input D, C, E, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); @@ -59,47 +63,103 @@ module \$_DFFE_PP_ (input D, C, E, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); +// Async reset. + +module \$_DFF_NP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NP0_ (input D, C, R, output Q); +module \$_DFF_PP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); + +module \$_DFF_NP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); +module \$_DFF_PP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); +// Async reset, enable. + +module \$__DFFE_NP0 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); + +module \$__DFFE_NP1 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); +module \$__DFFE_PP1 (input D, C, E, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset. + +module \$__DFFS_NP0_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFS_NP1_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset, enable. + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$__DFFSE_NP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches (no reset). module \$_DLATCH_N_ (input E, D, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -112,5 +172,7 @@ module \$_DLATCH_P_ (input E, D, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule +// Latches with reset (TODO). + `endif -- cgit v1.2.3 From a2352504031ee69efd0aac214fc947737303eb5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 18 Dec 2019 13:42:26 +0100 Subject: xilinx: Add xilinx_dffopt pass (#1557) --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells_sim.v | 35 ++++ techlibs/xilinx/cells_xtra.py | 2 +- techlibs/xilinx/cells_xtra.v | 21 --- techlibs/xilinx/synth_xilinx.cc | 1 + techlibs/xilinx/xilinx_dffopt.cc | 351 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 389 insertions(+), 22 deletions(-) create mode 100644 techlibs/xilinx/xilinx_dffopt.cc (limited to 'techlibs') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 3ebc72fe8..3f2fbcc85 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/xilinx/synth_xilinx.o +OBJS += techlibs/xilinx/xilinx_dffopt.o GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_32.vh diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index f9ce496ff..cf7923777 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -329,6 +329,41 @@ module FDSE ( endcase endgenerate endmodule +module FDRSE ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + (* invertible_pin = "IS_CE_INVERTED" *) + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_R_INVERTED" *) + input R, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + wire c = C ^ IS_C_INVERTED; + wire ce = CE ^ IS_CE_INVERTED; + wire d = D ^ IS_D_INVERTED; + wire r = R ^ IS_R_INVERTED; + wire s = S ^ IS_S_INVERTED; + always @(posedge c) + if (r) + Q <= 0; + else if (s) + Q <= 1; + else if (ce) + Q <= d; +endmodule + module FDCE ( (* abc9_arrival=303 *) output reg Q, diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index e4c580b9d..6d5adf1aa 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -66,7 +66,7 @@ CELLS = [ # CLB -- registers/latches. # Virtex 1/2/4/5, Spartan 3. Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), - Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), # Virtex 6, Spartan 6, Series 7, Ultrascale. # Cell('FDCE'), diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8ac596459..66b7c583f 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -17,27 +17,6 @@ module FDCPE (...); input PRE; endmodule -module FDRSE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - (* invertible_pin = "IS_R_INVERTED" *) - input R; - (* invertible_pin = "IS_S_INVERTED" *) - input S; -endmodule - module LDCPE (...); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a061c8dc0..971089b28 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -570,6 +570,7 @@ struct SynthXilinxPass : public ScriptPass else techmap_args += " -map " + ff_map_file; run("techmap " + techmap_args); + run("xilinx_dffopt"); run("clean"); } diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc new file mode 100644 index 000000000..1256a08cb --- /dev/null +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -0,0 +1,351 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +typedef std::pair> LutData; + +// Compute a LUT implementing (select ^ select_inv) ? alt_data : data. Returns true if successful. +bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) { + // First, gather input signals. + result.second = data.second; + int idx_alt = -1; + if (alt_data.wire) { + // Check if we already have it. + for (int i = 0; i < GetSize(result.second); i++) + if (result.second[i] == alt_data) + idx_alt = i; + // If not, add it. + if (idx_alt == -1) { + idx_alt = GetSize(result.second); + result.second.push_back(alt_data); + } + } + std::vector idx_sel; + for (auto bit : select.second) { + int idx = -1; + for (int i = 0; i < GetSize(result.second); i++) + if (result.second[i] == bit) + idx = i; + if (idx == -1) { + idx = GetSize(result.second); + result.second.push_back(bit); + } + idx_sel.push_back(idx); + } + + // If LUT would be too large, bail. + if (GetSize(result.second) > max_lut_size) + return false; + + // Okay, we're doing it — compute the LUT mask. + result.first = Const(0, 1 << GetSize(result.second)); + for (int i = 0; i < GetSize(result.first); i++) { + int sel_lut_idx = 0; + for (int j = 0; j < GetSize(select.second); j++) + if (i & 1 << idx_sel[j]) + sel_lut_idx |= 1 << j; + bool select_val = (select.first.bits[sel_lut_idx] == State::S1); + bool new_bit; + if (select_val ^ select_inv) { + // Use alt_data. + if (alt_data.wire) + new_bit = (i & 1 << idx_alt) != 0; + else + new_bit = alt_data.data == State::S1; + } else { + // Use original LUT. + int lut_idx = i & ((1 << GetSize(data.second)) - 1); + new_bit = data.first.bits[lut_idx] == State::S1; + } + result.first.bits[i] = new_bit ? State::S1 : State::S0; + } + return true; +} + +struct XilinxDffOptPass : public Pass { + XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" xilinx_dffopt [options] [selection]\n"); + log("\n"); + log("Converts hardware clock enable and set/reset signals on FFs to emulation\n"); + log("using LUTs, if doing so would improve area. Operates on post-techmap Xilinx\n"); + log("cells (LUT*, FD*).\n"); + log("\n"); + log(" -lut4\n"); + log(" Assume a LUT4-based device (instead of a LUT6-based device).\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n"); + + size_t argidx; + int max_lut_size = 6; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-lut4") { + max_lut_size = 4; + continue; + } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + log("Optimizing FFs in %s.\n", log_id(module)); + + SigMap sigmap(module); + dict> bit_to_lut; + dict bit_uses; + + // Gather LUTs. + for (auto cell : module->selected_cells()) + { + for (auto port : cell->connections()) + for (auto bit : port.second) + bit_uses[sigmap(bit)]++; + if (cell->get_bool_attribute(ID::keep)) + continue; + if (cell->type == ID(INV)) { + SigBit sigout = sigmap(cell->getPort(ID(O))); + SigBit sigin = sigmap(cell->getPort(ID(I))); + bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); + } else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) { + SigBit sigout = sigmap(cell->getPort(ID(O))); + const Const &init = cell->getParam(ID(INIT)); + std::vector sigin; + sigin.push_back(sigmap(cell->getPort(ID(I0)))); + if (cell->type == ID(LUT1)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I1)))); + if (cell->type == ID(LUT2)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I2)))); + if (cell->type == ID(LUT3)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I3)))); + if (cell->type == ID(LUT4)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I4)))); + if (cell->type == ID(LUT5)) + goto lut_sigin_done; + sigin.push_back(sigmap(cell->getPort(ID(I5)))); +lut_sigin_done: + bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell); + } + } + for (auto wire : module->wires()) + if (wire->port_output || wire->port_input) + for (int i = 0; i < GetSize(wire); i++) + bit_uses[sigmap(SigBit(wire, i))]++; + + // Iterate through FFs. + for (auto cell : module->selected_cells()) + { + bool has_s = false, has_r = false; + if (cell->type.in(ID(FDCE), ID(FDPE), ID(FDCPE), ID(FDCE_1), ID(FDPE_1), ID(FDCPE_1))) { + // Async reset. + } else if (cell->type.in(ID(FDRE), ID(FDRE_1))) { + has_r = true; + } else if (cell->type.in(ID(FDSE), ID(FDSE_1))) { + has_s = true; + } else if (cell->type.in(ID(FDRSE), ID(FDRSE_1))) { + has_r = true; + has_s = true; + } else { + // Not a FF. + continue; + } + if (cell->get_bool_attribute(ID::keep)) + continue; + + // Don't bother if D has more than one use. + SigBit sig_D = sigmap(cell->getPort(ID(D))); + if (bit_uses[sig_D] > 2) + continue; + + // Find the D LUT. + auto it_D = bit_to_lut.find(sig_D); + if (it_D == bit_to_lut.end()) + continue; + LutData lut_d = it_D->second.first; + Cell *cell_d = it_D->second.second; + if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) { + // Flip all bits in the LUT. + for (int i = 0; i < GetSize(lut_d.first); i++) + lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1; + } + + LutData lut_d_post_ce; + LutData lut_d_post_s; + LutData lut_d_post_r; + bool worthy_post_ce = false; + bool worthy_post_s = false; + bool worthy_post_r = false; + + // First, unmap CE. + SigBit sig_Q = sigmap(cell->getPort(ID(Q))); + SigBit sig_CE = sigmap(cell->getPort(ID(CE))); + LutData lut_ce = LutData(Const(2, 2), {sig_CE}); + auto it_CE = bit_to_lut.find(sig_CE); + if (it_CE != bit_to_lut.end()) + lut_ce = it_CE->second.first; + if (sig_CE.wire) { + // Merge CE LUT and D LUT into one. If it cannot be done, nothing to do about this FF. + if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size)) + continue; + + // If this gets rid of a CE LUT, it's worth it. If not, it still may be worth it, if we can remove set/reset as well. + if (it_CE != bit_to_lut.end()) + worthy_post_ce = true; + } else if (sig_CE.data != State::S1) { + // Strange. Should not happen in a reasonable flow, so bail. + continue; + } else { + lut_d_post_ce = lut_d; + } + + // Second, unmap S, if any. + lut_d_post_s = lut_d_post_ce; + if (has_s) { + SigBit sig_S = sigmap(cell->getPort(ID(S))); + LutData lut_s = LutData(Const(2, 2), {sig_S}); + bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool(); + auto it_S = bit_to_lut.find(sig_S); + if (it_S != bit_to_lut.end()) + lut_s = it_S->second.first; + if (sig_S.wire) { + // Merge S LUT and D LUT into one. If it cannot be done, try to at least merge CE. + if (!merge_lut(lut_d_post_s, lut_d_post_ce, lut_s, inv_s, SigBit(State::S1), max_lut_size)) + goto unmap; + // If this gets rid of an S LUT, it's worth it. + if (it_S != bit_to_lut.end()) + worthy_post_s = true; + } else if (sig_S.data != (inv_s ? State::S1 : State::S0)) { + // Strange. Should not happen in a reasonable flow, so bail. + continue; + } + } + + // Third, unmap R, if any. + lut_d_post_r = lut_d_post_s; + if (has_r) { + SigBit sig_R = sigmap(cell->getPort(ID(R))); + LutData lut_r = LutData(Const(2, 2), {sig_R}); + bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool(); + auto it_R = bit_to_lut.find(sig_R); + if (it_R != bit_to_lut.end()) + lut_r = it_R->second.first; + if (sig_R.wire) { + // Merge R LUT and D LUT into one. If it cannot be done, try to at least merge CE/S. + if (!merge_lut(lut_d_post_r, lut_d_post_s, lut_r, inv_r, SigBit(State::S0), max_lut_size)) + goto unmap; + // If this gets rid of an S LUT, it's worth it. + if (it_R != bit_to_lut.end()) + worthy_post_r = true; + } else if (sig_R.data != (inv_r ? State::S1 : State::S0)) { + // Strange. Should not happen in a reasonable flow, so bail. + continue; + } + } + +unmap: + LutData final_lut; + if (worthy_post_r) { + final_lut = lut_d_post_r; + log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + } else if (worthy_post_s) { + final_lut = lut_d_post_s; + log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + } else if (worthy_post_ce) { + final_lut = lut_d_post_ce; + log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + } else { + // Nothing to do here. + continue; + } + + // Okay, we're doing it. Unmap ports. + if (worthy_post_r) { + cell->unsetParam(ID(IS_R_INVERTED)); + cell->setPort(ID(R), Const(0, 1)); + } + if (has_s && (worthy_post_r || worthy_post_s)) { + cell->unsetParam(ID(IS_S_INVERTED)); + cell->setPort(ID(S), Const(0, 1)); + } + cell->setPort(ID(CE), Const(1, 1)); + cell->unsetParam(ID(IS_D_INVERTED)); + + // Create the new LUT. + Cell *lut_cell = 0; + switch (GetSize(final_lut.second)) { + case 1: + lut_cell = module->addCell(NEW_ID, ID(LUT1)); + break; + case 2: + lut_cell = module->addCell(NEW_ID, ID(LUT2)); + break; + case 3: + lut_cell = module->addCell(NEW_ID, ID(LUT3)); + break; + case 4: + lut_cell = module->addCell(NEW_ID, ID(LUT4)); + break; + case 5: + lut_cell = module->addCell(NEW_ID, ID(LUT5)); + break; + case 6: + lut_cell = module->addCell(NEW_ID, ID(LUT6)); + break; + default: + log_assert(!"unknown lut size"); + } + lut_cell->attributes = cell_d->attributes; + Wire *lut_out = module->addWire(NEW_ID); + lut_cell->setParam(ID(INIT), final_lut.first); + cell->setPort(ID(D), lut_out); + lut_cell->setPort(ID(O), lut_out); + lut_cell->setPort(ID(I0), final_lut.second[0]); + if (GetSize(final_lut.second) >= 2) + lut_cell->setPort(ID(I1), final_lut.second[1]); + if (GetSize(final_lut.second) >= 3) + lut_cell->setPort(ID(I2), final_lut.second[2]); + if (GetSize(final_lut.second) >= 4) + lut_cell->setPort(ID(I3), final_lut.second[3]); + if (GetSize(final_lut.second) >= 5) + lut_cell->setPort(ID(I4), final_lut.second[4]); + if (GetSize(final_lut.second) >= 6) + lut_cell->setPort(ID(I5), final_lut.second[5]); + } + } + } +} XilinxDffOptPass; + +PRIVATE_NAMESPACE_END + -- cgit v1.2.3 From 561ae1c5c4e694656fb4ce9198e62f0efbe4c705 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Thu, 19 Dec 2019 08:49:21 +0100 Subject: xilinx_dffopt: Keep order of LUT inputs. See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549 --- techlibs/xilinx/xilinx_dffopt.cc | 46 ++++++++++++++++++++++++++-------------- 1 file changed, 30 insertions(+), 16 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index 1256a08cb..13a0b9b83 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -27,20 +27,13 @@ typedef std::pair> LutData; // Compute a LUT implementing (select ^ select_inv) ? alt_data : data. Returns true if successful. bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) { - // First, gather input signals. + // First, gather input signals -- insert new signals at the beginning + // of the vector, so they don't disturb the likely-critical D LUT input + // timings. result.second = data.second; - int idx_alt = -1; - if (alt_data.wire) { - // Check if we already have it. - for (int i = 0; i < GetSize(result.second); i++) - if (result.second[i] == alt_data) - idx_alt = i; - // If not, add it. - if (idx_alt == -1) { - idx_alt = GetSize(result.second); - result.second.push_back(alt_data); - } - } + // D lut inputs initially start at 0. + int idx_data = 0; + // Now add the control input LUT inputs. std::vector idx_sel; for (auto bit : select.second) { int idx = -1; @@ -48,11 +41,32 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool if (result.second[i] == bit) idx = i; if (idx == -1) { - idx = GetSize(result.second); - result.second.push_back(bit); + idx = 0; + // Insert new signal at the beginning and bump all indices. + result.second.insert(result.second.begin(), bit); + idx_data++; + for (int &sidx : idx_sel) + sidx++; } idx_sel.push_back(idx); } + // Insert the Q signal, if any, to the slowest input -- it will have + // no problem meeting timing. + int idx_alt = -1; + if (alt_data.wire) { + // Check if we already have it. + for (int i = 0; i < GetSize(result.second); i++) + if (result.second[i] == alt_data) + idx_alt = i; + // If not, add it. + if (idx_alt == -1) { + idx_alt = 0; + result.second.insert(result.second.begin(), alt_data); + idx_data++; + for (int &sidx : idx_sel) + sidx++; + } + } // If LUT would be too large, bail. if (GetSize(result.second) > max_lut_size) @@ -75,7 +89,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool new_bit = alt_data.data == State::S1; } else { // Use original LUT. - int lut_idx = i & ((1 << GetSize(data.second)) - 1); + int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1); new_bit = data.first.bits[lut_idx] == State::S1; } result.first.bits[i] = new_bit ? State::S1 : State::S0; -- cgit v1.2.3 From 8b2c9f4518aa27662a29de5d282df44f1bba6dc8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 27 Nov 2019 18:13:00 +0100 Subject: xilinx: Add simulation models for remaining CLB primitives. --- techlibs/xilinx/cells_sim.v | 201 +++++++++++++++++++++++++++++++++++++++++- techlibs/xilinx/cells_xtra.py | 26 +++--- techlibs/xilinx/cells_xtra.v | 139 ----------------------------- 3 files changed, 210 insertions(+), 156 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index cf7923777..47ba794bf 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -227,6 +227,14 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule +module MUXF5(output O, input I0, I1, S); + assign O = S ? I1 : I0; +endmodule + +module MUXF6(output O, input I0, I1, S); + assign O = S ? I1 : I0; +endmodule + (* abc9_box_id = 1, lib_whitebox *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; @@ -237,6 +245,10 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +module MUXF9(output O, input I0, I1, S); + assign O = S ? I1 : I0; +endmodule + module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule @@ -258,6 +270,26 @@ module CARRY4( assign CO[3] = S[3] ? CO[2] : DI[3]; endmodule +module CARRY8( + output [7:0] CO, + output [7:0] O, + input CI, + input CI_TOP, + input [7:0] DI, S +); + parameter CARRY_TYPE = "SINGLE_CY8"; + wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]); + assign O = S ^ {CO[6:4], CI4, CO[2:0], CI}; + assign CO[0] = S[0] ? CI : DI[0]; + assign CO[1] = S[1] ? CO[0] : DI[1]; + assign CO[2] = S[2] ? CO[1] : DI[2]; + assign CO[3] = S[3] ? CO[2] : DI[3]; + assign CO[4] = S[4] ? CI4 : DI[4]; + assign CO[5] = S[5] ? CO[4] : DI[5]; + assign CO[6] = S[6] ? CO[5] : DI[6]; + assign CO[7] = S[7] ? CO[6] : DI[7]; +endmodule + `ifdef _EXPLICIT_CARRY module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S); @@ -281,6 +313,16 @@ endmodule `endif +module ORCY (output O, input CI, I); + assign O = CI | I; +endmodule + +module MULT_AND (output LO, input I0, I1); + assign LO = I0 & I1; +endmodule + +// Flip-flops and latches. + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 module FDRE ( @@ -414,6 +456,51 @@ module FDPE ( endcase endgenerate endmodule +module FDCPE ( + output wire Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + wire c = C ^ IS_C_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + // Hacky model to avoid simulation-synthesis mismatches. + reg qc, qp, qs; + initial qc = INIT; + initial qp = INIT; + initial qs = 0; + always @(posedge c, posedge clr) begin + if (clr) + qc <= 0; + else if (CE) + qc <= D; + end + always @(posedge c, posedge pre) begin + if (pre) + qp <= 1; + else if (CE) + qp <= D; + end + always @* begin + if (clr) + qs <= 0; + else if (pre) + qs <= 1; + end + assign Q = qs ? qp : qc; +endmodule + module FDRE_1 ( (* abc9_arrival=303 *) output reg Q, @@ -480,8 +567,8 @@ module LDCE ( wire clr = CLR ^ IS_CLR_INVERTED; wire g = G ^ IS_G_INVERTED; always @* - if (clr) Q = 1'b0; - else if (GE && g) Q = D; + if (clr) Q <= 1'b0; + else if (GE && g) Q <= D; endmodule module LDPE ( @@ -502,8 +589,59 @@ module LDPE ( wire g = G ^ IS_G_INVERTED; wire pre = PRE ^ IS_PRE_INVERTED; always @* - if (pre) Q = 1'b1; - else if (GE && g) Q = D; + if (pre) Q <= 1'b1; + else if (GE && g) Q <= D; +endmodule + +module LDCPE ( + output reg Q, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + (* invertible_pin = "IS_GE_INVERTED" *) + input GE, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter [0:0] IS_GE_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + initial Q = INIT; + wire d = D ^ IS_D_INVERTED; + wire g = G ^ IS_G_INVERTED; + wire ge = GE ^ IS_GE_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + always @* + if (clr) Q <= 1'b0; + else if (pre) Q <= 1'b1; + else if (ge && g) Q <= d; +endmodule + +module AND2B1L ( + output O, + input DI, + (* invertible_pin = "IS_SRI_INVERTED" *) + input SRI +); + parameter [0:0] IS_SRI_INVERTED = 1'b0; + assign O = DI & ~(SRI ^ IS_SRI_INVERTED); +endmodule + +module OR2L ( + output O, + input DI, + (* invertible_pin = "IS_SRI_INVERTED" *) + input SRI +); + parameter [0:0] IS_SRI_INVERTED = 1'b0; + assign O = DI | (SRI ^ IS_SRI_INVERTED); endmodule // LUTRAM. @@ -1369,6 +1507,20 @@ endmodule // Shift registers. +module SRL16 ( + output Q, + input A0, A1, A2, A3, + (* clkbuf_sink *) + input CLK, + input D +); + parameter [15:0] INIT = 16'h0000; + + reg [15:0] r = INIT; + assign Q = r[{A3,A2,A1,A0}]; + always @(posedge CLK) r <= { r[14:0], D }; +endmodule + module SRL16E ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 (* abc9_arrival=1472 *) @@ -1393,6 +1545,22 @@ module SRL16E ( endgenerate endmodule +module SRLC16 ( + output Q, + output Q15, + input A0, A1, A2, A3, + (* clkbuf_sink *) + input CLK, + input D +); + parameter [15:0] INIT = 16'h0000; + + reg [15:0] r = INIT; + assign Q15 = r[15]; + assign Q = r[{A3,A2,A1,A0}]; + always @(posedge CLK) r <= { r[14:0], D }; +endmodule + module SRLC16E ( output Q, output Q15, @@ -1445,6 +1613,31 @@ module SRLC32E ( endgenerate endmodule +module CFGLUT5 ( + output CDO, + output O5, + output O6, + input I4, + input I3, + input I2, + input I1, + input I0, + input CDI, + input CE, + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + wire clk = CLK ^ IS_CLK_INVERTED; + reg [31:0] r = INIT; + assign CDO = r[31]; + assign O5 = r[{1'b0, I3, I2, I1, I0}]; + assign O6 = r[{I4, I3, I2, I1, I0}]; + always @(posedge clk) if (CE) r <= {r[30:0], CDI}; +endmodule + // DSP // Virtex 2, Virtex 2 Pro, Spartan 3. diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 6d5adf1aa..d5c58c5d7 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -65,9 +65,9 @@ CELLS = [ # CLB -- registers/latches. # Virtex 1/2/4/5, Spartan 3. - Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), - Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), + # Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), # Virtex 6, Spartan 6, Series 7, Ultrascale. # Cell('FDCE'), # Cell('FDPE'), @@ -75,8 +75,8 @@ CELLS = [ # Cell('FDSE'), # Cell('LDCE'), # Cell('LDPE'), - Cell('AND2B1L'), - Cell('OR2L'), + # Cell('AND2B1L'), + # Cell('OR2L'), # CLB -- other. # Cell('LUT1'), @@ -86,23 +86,23 @@ CELLS = [ # Cell('LUT5'), # Cell('LUT6'), # Cell('LUT6_2'), - Cell('MUXF5'), - Cell('MUXF6'), + # Cell('MUXF5'), + # Cell('MUXF6'), # Cell('MUXF7'), # Cell('MUXF8'), - Cell('MUXF9'), + # Cell('MUXF9'), # Cell('CARRY4'), - Cell('CARRY8'), + # Cell('CARRY8'), # Cell('MUXCY'), # Cell('XORCY'), - Cell('ORCY'), - Cell('MULT_AND'), - Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('ORCY'), + # Cell('MULT_AND'), + # Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}), # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}), # Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}), # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), # Block RAM. # Virtex. diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 66b7c583f..c3e5c72f9 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -1,144 +1,5 @@ // Created by cells_xtra.py from Xilinx models -module FDCPE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - input D; - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE; -endmodule - -module LDCPE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_GE_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - output Q; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - (* invertible_pin = "IS_GE_INVERTED" *) - input GE; - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE; -endmodule - -module AND2B1L (...); - parameter [0:0] IS_SRI_INVERTED = 1'b0; - output O; - input DI; - (* invertible_pin = "IS_SRI_INVERTED" *) - input SRI; -endmodule - -module OR2L (...); - parameter [0:0] IS_SRI_INVERTED = 1'b0; - output O; - input DI; - (* invertible_pin = "IS_SRI_INVERTED" *) - input SRI; -endmodule - -module MUXF5 (...); - output O; - input I0; - input I1; - input S; -endmodule - -module MUXF6 (...); - output O; - input I0; - input I1; - input S; -endmodule - -module MUXF9 (...); - output O; - input I0; - input I1; - input S; -endmodule - -module CARRY8 (...); - parameter CARRY_TYPE = "SINGLE_CY8"; - output [7:0] CO; - output [7:0] O; - input CI; - input CI_TOP; - input [7:0] DI; - input [7:0] S; -endmodule - -module ORCY (...); - output O; - input CI; - input I; -endmodule - -module MULT_AND (...); - output LO; - input I0; - input I1; -endmodule - -module SRL16 (...); - parameter [15:0] INIT = 16'h0000; - output Q; - input A0; - input A1; - input A2; - input A3; - (* clkbuf_sink *) - input CLK; - input D; -endmodule - -module SRLC16 (...); - parameter [15:0] INIT = 16'h0000; - output Q; - output Q15; - input A0; - input A1; - input A2; - input A3; - (* clkbuf_sink *) - input CLK; - input D; -endmodule - -module CFGLUT5 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output CDO; - output O5; - output O6; - input I4; - input I3; - input I2; - input I1; - input I0; - input CDI; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; -endmodule - module RAMB16_S1 (...); parameter [0:0] INIT = 1'h0; parameter [0:0] SRVAL = 1'h0; -- cgit v1.2.3 From 979bf36fb00ec61ec7e27f074079e0464be03be7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Dec 2019 11:23:41 -0800 Subject: Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t --- techlibs/xilinx/abc9_map.v | 32 ++++++++++++++++++-------------- techlibs/xilinx/abc9_model.v | 14 +++++++++++--- techlibs/xilinx/abc9_unmap.v | 3 ++- techlibs/xilinx/abc9_xc7.box | 26 ++++++++++++++++---------- techlibs/xilinx/cells_sim.v | 16 ++++++++-------- 5 files changed, 55 insertions(+), 36 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index d04cdb5eb..b36d93c5d 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -161,8 +161,10 @@ module FDCE (output Q, input C, CE, D, CLR); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC1 below ); + // Since this is an async flop, async behaviour is dealt with here + \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -177,13 +179,12 @@ module FDCE (output Q, input C, CE, D, CLR); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC0 below ); + // Since this is an async flop, async behaviour is dealt with here + \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - // Since this is an async flop, async behaviour is also dealt with - // using the $_ABC9_ASYNC box by abc9_map.v - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; @@ -203,8 +204,9 @@ module FDCE_1 (output Q, input C, CE, D, CLR); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC1 below ); + \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); end else begin assign Q = QQ; @@ -216,11 +218,11 @@ module FDCE_1 (output Q, input C, CE, D, CLR); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC0 below ); + \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; @@ -247,8 +249,9 @@ module FDPE (output Q, input C, CE, D, PRE); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC0 below ); + \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -263,11 +266,11 @@ module FDPE (output Q, input C, CE, D, PRE); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC1 below ); + \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; @@ -287,8 +290,9 @@ module FDPE_1 (output Q, input C, CE, D, PRE); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC0 below ); + \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); end else begin assign Q = QQ; @@ -300,11 +304,11 @@ module FDPE_1 (output Q, input C, CE, D, PRE); // control is not directly // supported by abc9 but its // behaviour is captured by - // $__ABC9_ASYNC below + // $__ABC9_ASYNC1 below ); + \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); end endgenerate \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); - \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index cc0e5ec41..c793396a4 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -33,11 +33,19 @@ endmodule module \$__ABC9_FF_ (input D, output Q); endmodule +// Box to emulate async behaviour of FDC* (* abc_box_id = 1000 *) -module \$__ABC9_ASYNC (input A, S, output Y); +module \$__ABC9_ASYNC0 (input A, S, output Y); + assign Y = S ? 1'b0 : A; endmodule -// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} +// Box to emulate async behaviour of FDP* +(* abc_box_id = 1001 *) +module \$__ABC9_ASYNC1 (input A, S, output Y); + assign Y = S ? 1'b0 : A; +endmodule + +// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} // Necessary since RAMD* and SRL* have both combinatorial (i.e. // same-cycle read operation) and sequential (write operation // is only committed on the next clock edge). @@ -46,7 +54,7 @@ endmodule (* abc9_box_id=2000 *) module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); endmodule -// Box to emulate comb/seq behaviour of RAMD128 +// Box to emulate comb/seq behaviour of RAM128 (* abc9_box_id=2001 *) module \$__ABC9_LUT7 (input A, input [6:0] S, output Y); endmodule diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index 21fe78d08..46526007d 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -20,7 +20,8 @@ // ============================================================================ -module \$__ABC9_ASYNC (input A, S, output Y); +(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *) +module \$__ABC9_ASYNC01 (input A, S, output Y); assign Y = A; endmodule diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 4e632c0fa..a2d119284 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -41,10 +41,16 @@ CARRY4 4 1 10 8 592 540 520 356 - 512 548 292 - 228 580 526 507 398 385 508 528 378 380 114 -# Box to emulate async behaviour of FD[CP]* +# Box to emulate async behaviour of FDC* # Inputs: A S # Outputs: Y -$__ABC9_ASYNC 1000 0 2 1 +$__ABC9_ASYNC0 1000 1 2 1 +0 764 + +# Box to emulate async behaviour of FDP* +# Inputs: A S +# Outputs: Y +$__ABC9_ASYNC1 1001 1 2 1 0 764 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to @@ -54,42 +60,42 @@ $__ABC9_ASYNC 1000 0 2 1 # Inputs: C CE D R \$currQ # Outputs: Q -FDRE 1001 1 5 1 +FDRE 1100 1 5 1 0 151 0 446 0 # Inputs: C CE D R \$currQ # Outputs: Q -FDRE_1 1002 1 5 1 +FDRE_1 1101 1 5 1 0 151 0 446 0 # Inputs: C CE CLR D \$currQ # Outputs: Q -FDCE 1003 1 5 1 +FDCE 1102 1 5 1 0 151 806 0 0 # Inputs: C CE CLR D \$currQ # Outputs: Q -FDCE_1 1004 1 5 1 +FDCE_1 1103 1 5 1 0 151 806 0 0 # Inputs: C CE D PRE \$currQ # Outputs: Q -FDPE 1005 1 5 1 +FDPE 1104 1 5 1 0 151 0 806 0 # Inputs: C CE D PRE \$currQ # Outputs: Q -FDPE_1 1006 1 5 1 +FDPE_1 1105 1 5 1 0 151 0 806 0 # Inputs: C CE D S \$currQ # Outputs: Q -FDSE 1007 1 5 1 +FDSE 1106 1 5 1 0 151 0 446 0 # Inputs: C CE D S \$currQ # Outputs: Q -FDSE_1 1008 1 5 1 +FDSE_1 1107 1 5 1 0 151 0 446 0 # SLICEM/A6LUT diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 7941a94cd..d7dff8975 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -283,7 +283,7 @@ endmodule // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250 -(* abc9_box_id=1001, lib_whitebox, abc9_flop *) +(* abc9_box_id=1100, lib_whitebox, abc9_flop *) module FDRE ( (* abc9_arrival=303 *) output reg Q, @@ -307,7 +307,7 @@ module FDRE ( endcase endgenerate endmodule -(* abc9_box_id=1002, lib_whitebox, abc9_flop *) +(* abc9_box_id=1101, lib_whitebox, abc9_flop *) module FDRE_1 ( (* abc9_arrival=303 *) output reg Q, @@ -355,7 +355,7 @@ module FDRSE ( Q <= d; endmodule -(* abc9_box_id=1003, lib_whitebox, abc9_flop *) +(* abc9_box_id=1102, lib_whitebox, abc9_flop *) module FDCE ( (* abc9_arrival=303 *) output reg Q, @@ -381,7 +381,7 @@ module FDCE ( endcase endgenerate endmodule -(* abc9_box_id=1004, lib_whitebox, abc9_flop *) +(* abc9_box_id=1103, lib_whitebox, abc9_flop *) module FDCE_1 ( (* abc9_arrival=303 *) output reg Q, @@ -394,7 +394,7 @@ module FDCE_1 ( always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule -(* abc9_box_id=1005, lib_whitebox, abc9_flop *) +(* abc9_box_id=1104, lib_whitebox, abc9_flop *) module FDPE ( (* abc9_arrival=303 *) output reg Q, @@ -420,7 +420,7 @@ module FDPE ( endcase endgenerate endmodule -(* abc9_box_id=1006, lib_whitebox, abc9_flop *) +(* abc9_box_id=1105, lib_whitebox, abc9_flop *) module FDPE_1 ( (* abc9_arrival=303 *) output reg Q, @@ -433,7 +433,7 @@ module FDPE_1 ( always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc9_box_id=1007, lib_whitebox, abc9_flop *) +(* abc9_box_id=1106, lib_whitebox, abc9_flop *) module FDSE ( (* abc9_arrival=303 *) output reg Q, @@ -457,7 +457,7 @@ module FDSE ( endcase endgenerate endmodule -(* abc9_box_id=1008, lib_whitebox, abc9_flop *) +(* abc9_box_id=1107, lib_whitebox, abc9_flop *) module FDSE_1 ( (* abc9_arrival=303 *) output reg Q, -- cgit v1.2.3 From 45f0f1486bbe30cdbf22c94b165879568af1a37a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Dec 2019 11:24:39 -0800 Subject: Add RAM{32,64}M to abc9_map.v --- techlibs/xilinx/abc9_map.v | 78 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index b36d93c5d..d2d7d9114 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -446,6 +446,84 @@ module RAM128X1D ( \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO)); endmodule +module RAM32M ( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + (* techmap_autopurge *) input [4:0] ADDRA, + (* techmap_autopurge *) input [4:0] ADDRB, + (* techmap_autopurge *) input [4:0] ADDRC, + (* techmap_autopurge *) input [4:0] ADDRD, + (* techmap_autopurge *) input [1:0] DIA, + (* techmap_autopurge *) input [1:0] DIB, + (* techmap_autopurge *) input [1:0] DIC, + (* techmap_autopurge *) input [1:0] DID, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [1:0] \$DOA , \$DOB , \$DOC , \$DOD ; + RAM32M #( + .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), + .IS_WCLK_INVERTED(IS_WCLK_INVERTED) + ) _TECHMAP_REPLACE_ ( + .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ), + .WCLK(WCLK), .WE(WE), + .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), + .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) + ); + \$__ABC9_LUT6 doa0 (.A(\$DOA [0]), .S({1'b1, ADDRA}), .Y(DOA[0])); + \$__ABC9_LUT6 doa1 (.A(\$DOA [1]), .S({1'b1, ADDRA}), .Y(DOA[1])); + \$__ABC9_LUT6 dob0 (.A(\$DOB [0]), .S({1'b1, ADDRB}), .Y(DOB[0])); + \$__ABC9_LUT6 dob1 (.A(\$DOB [1]), .S({1'b1, ADDRB}), .Y(DOB[1])); + \$__ABC9_LUT6 doc0 (.A(\$DOC [0]), .S({1'b1, ADDRC}), .Y(DOC[0])); + \$__ABC9_LUT6 doc1 (.A(\$DOC [1]), .S({1'b1, ADDRC}), .Y(DOC[1])); + \$__ABC9_LUT6 dod0 (.A(\$DOD [0]), .S({1'b1, ADDRD}), .Y(DOD[0])); + \$__ABC9_LUT6 dod1 (.A(\$DOD [1]), .S({1'b1, ADDRD}), .Y(DOD[1])); +endmodule + +module RAM64M ( + output DOA, + output DOB, + output DOC, + output DOD, + (* techmap_autopurge *) input [5:0] ADDRA, + (* techmap_autopurge *) input [5:0] ADDRB, + (* techmap_autopurge *) input [5:0] ADDRC, + (* techmap_autopurge *) input [5:0] ADDRD, + (* techmap_autopurge *) input DIA, + (* techmap_autopurge *) input DIB, + (* techmap_autopurge *) input DIC, + (* techmap_autopurge *) input DID, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire \$DOA , \$DOB , \$DOC , \$DOD ; + RAM64M #( + .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), + .IS_WCLK_INVERTED(IS_WCLK_INVERTED) + ) _TECHMAP_REPLACE_ ( + .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ), + .WCLK(WCLK), .WE(WE), + .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), + .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) + ); + \$__ABC9_LUT6 doa (.A(\$DOA ), .S(ADDRA), .Y(DOA)); + \$__ABC9_LUT6 dob (.A(\$DOB ), .S(ADDRB), .Y(DOB)); + \$__ABC9_LUT6 doc (.A(\$DOC ), .S(ADDRC), .Y(DOC)); + \$__ABC9_LUT6 dod (.A(\$DOD ), .S(ADDRD), .Y(DOD)); +endmodule + module SRL16E ( output Q, (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D -- cgit v1.2.3 From 10e82e103f7b95d5a50d2ac85bc8e07e4461e388 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Dec 2019 12:05:45 -0800 Subject: Revert "Optimise write_xaiger" --- techlibs/ecp5/synth_ecp5.cc | 5 ----- techlibs/ice40/synth_ice40.cc | 5 ----- techlibs/xilinx/synth_xilinx.cc | 5 ----- 3 files changed, 15 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 16ff9c57a..b71bb2395 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -321,11 +321,6 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 5073ba917..ed7a16c08 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,11 +350,6 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ff530b819..971089b28 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -540,11 +540,6 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); -- cgit v1.2.3 From 7928eb113c5a310924f4bb8ab26d0dafe902d6ec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Dec 2019 11:24:39 -0800 Subject: Add RAM{32,64}M to abc9_map.v --- techlibs/xilinx/abc9_map.v | 78 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 6fd73c1e0..7b9427b2f 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -88,6 +88,84 @@ module RAM128X1D ( \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO)); endmodule +module RAM32M ( + output [1:0] DOA, + output [1:0] DOB, + output [1:0] DOC, + output [1:0] DOD, + (* techmap_autopurge *) input [4:0] ADDRA, + (* techmap_autopurge *) input [4:0] ADDRB, + (* techmap_autopurge *) input [4:0] ADDRC, + (* techmap_autopurge *) input [4:0] ADDRD, + (* techmap_autopurge *) input [1:0] DIA, + (* techmap_autopurge *) input [1:0] DIB, + (* techmap_autopurge *) input [1:0] DIC, + (* techmap_autopurge *) input [1:0] DID, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire [1:0] \$DOA , \$DOB , \$DOC , \$DOD ; + RAM32M #( + .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), + .IS_WCLK_INVERTED(IS_WCLK_INVERTED) + ) _TECHMAP_REPLACE_ ( + .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ), + .WCLK(WCLK), .WE(WE), + .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), + .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) + ); + \$__ABC9_LUT6 doa0 (.A(\$DOA [0]), .S({1'b1, ADDRA}), .Y(DOA[0])); + \$__ABC9_LUT6 doa1 (.A(\$DOA [1]), .S({1'b1, ADDRA}), .Y(DOA[1])); + \$__ABC9_LUT6 dob0 (.A(\$DOB [0]), .S({1'b1, ADDRB}), .Y(DOB[0])); + \$__ABC9_LUT6 dob1 (.A(\$DOB [1]), .S({1'b1, ADDRB}), .Y(DOB[1])); + \$__ABC9_LUT6 doc0 (.A(\$DOC [0]), .S({1'b1, ADDRC}), .Y(DOC[0])); + \$__ABC9_LUT6 doc1 (.A(\$DOC [1]), .S({1'b1, ADDRC}), .Y(DOC[1])); + \$__ABC9_LUT6 dod0 (.A(\$DOD [0]), .S({1'b1, ADDRD}), .Y(DOD[0])); + \$__ABC9_LUT6 dod1 (.A(\$DOD [1]), .S({1'b1, ADDRD}), .Y(DOD[1])); +endmodule + +module RAM64M ( + output DOA, + output DOB, + output DOC, + output DOD, + (* techmap_autopurge *) input [5:0] ADDRA, + (* techmap_autopurge *) input [5:0] ADDRB, + (* techmap_autopurge *) input [5:0] ADDRC, + (* techmap_autopurge *) input [5:0] ADDRD, + (* techmap_autopurge *) input DIA, + (* techmap_autopurge *) input DIB, + (* techmap_autopurge *) input DIC, + (* techmap_autopurge *) input DID, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + wire \$DOA , \$DOB , \$DOC , \$DOD ; + RAM64M #( + .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), + .IS_WCLK_INVERTED(IS_WCLK_INVERTED) + ) _TECHMAP_REPLACE_ ( + .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ), + .WCLK(WCLK), .WE(WE), + .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), + .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) + ); + \$__ABC9_LUT6 doa (.A(\$DOA ), .S(ADDRA), .Y(DOA)); + \$__ABC9_LUT6 dob (.A(\$DOB ), .S(ADDRB), .Y(DOB)); + \$__ABC9_LUT6 doc (.A(\$DOC ), .S(ADDRC), .Y(DOC)); + \$__ABC9_LUT6 dod (.A(\$DOD ), .S(ADDRD), .Y(DOD)); +endmodule + module SRL16E ( output Q, (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D -- cgit v1.2.3 From 5986a4df40a9c19171624c772b39e4c003e9c6ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Dec 2019 14:06:59 -0800 Subject: Add abc9_arrival times for RAM{32,64}M --- techlibs/xilinx/cells_sim.v | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 47ba794bf..804c2d70f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1244,18 +1244,11 @@ endmodule // Multi port. module RAM32M ( - output [1:0] DOA, - output [1:0] DOB, - output [1:0] DOC, - output [1:0] DOD, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, - input [1:0] DIA, - input [1:0] DIB, - input [1:0] DIC, - input [1:0] DID, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc9_arrival=1153 *) + output [1:0] DOA, DOB, DOC, DOD, + input [4:0] ADDRA, ADDRB, ADDRC, ADDRD, + input [1:0] DIA, DIB, DIC, DID, (* clkbuf_sink *) (* invertible_pin = "IS_WCLK_INVERTED" *) input WCLK, @@ -1354,18 +1347,11 @@ module RAM32M16 ( endmodule module RAM64M ( - output DOA, - output DOB, - output DOC, - output DOD, - input [5:0] ADDRA, - input [5:0] ADDRB, - input [5:0] ADDRC, - input [5:0] ADDRD, - input DIA, - input DIB, - input DIC, - input DID, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc9_arrival=1153 *) + output DOA, DOB, DOC, DOD, + input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, + input DIA, DIB, DIC, DID, (* clkbuf_sink *) (* invertible_pin = "IS_WCLK_INVERTED" *) input WCLK, -- cgit v1.2.3 From 2fcf683af427aa86ff57bcbed8b027e97fd03f96 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Dec 2019 11:56:41 +0100 Subject: Make iopad option default for all xilinx flows --- techlibs/xilinx/synth_xilinx.cc | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 971089b28..006679eb1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -ise\n"); - log(" generate an output netlist suitable for ISE (enables -iopad)\n"); + log(" generate an output netlist suitable for ISE\n"); log("\n"); log(" -nobram\n"); log(" do not use block RAM cells in output netlist\n"); @@ -84,11 +84,8 @@ struct SynthXilinxPass : public ScriptPass log(" -nodsp\n"); log(" do not use DSP48E1s to implement multipliers and associated logic\n"); log("\n"); - log(" -iopad\n"); - log(" enable I/O buffer insertion (selected automatically by -ise)\n"); - log("\n"); log(" -noiopad\n"); - log(" disable I/O buffer insertion (only useful with -ise)\n"); + log(" disable I/O buffer insertion\n"); log("\n"); log(" -noclkbuf\n"); log(" disable automatic clock buffer insertion\n"); @@ -122,7 +119,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9; + bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9; bool flatten_before_abc; int widemux; @@ -136,7 +133,6 @@ struct SynthXilinxPass : public ScriptPass retime = false; vpr = false; ise = false; - iopad = false; noiopad = false; noclkbuf = false; nocarry = false; @@ -212,10 +208,6 @@ struct SynthXilinxPass : public ScriptPass ise = true; continue; } - if (args[argidx] == "-iopad") { - iopad = true; - continue; - } if (args[argidx] == "-noiopad") { noiopad = true; continue; @@ -282,7 +274,6 @@ struct SynthXilinxPass : public ScriptPass void script() YS_OVERRIDE { - bool do_iopad = iopad || (ise && !noiopad); std::string ff_map_file; if (help_mode) ff_map_file = "+/xilinx/{family}_ff_map.v"; @@ -514,8 +505,8 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_cells")) { // Needs to be done before logic optimization, so that inverters (OE vs T) are handled. - if (help_mode || do_iopad) - run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); + if (help_mode || !noiopad) + run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if not '-noiopad')"); std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v"; if (widemux > 0) techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); -- cgit v1.2.3 From 1937091f622a37d8050e5cc1e7c486707fd90b2f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Dec 2019 13:21:45 +0100 Subject: iopad no op for compatibility with old scripts --- techlibs/xilinx/synth_xilinx.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 006679eb1..c66e1d750 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -208,6 +208,9 @@ struct SynthXilinxPass : public ScriptPass ise = true; continue; } + if (args[argidx] == "-iopad") { + continue; + } if (args[argidx] == "-noiopad") { noiopad = true; continue; -- cgit v1.2.3 From 436fea9e6990c66369d7c30b571920ae115efb44 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Dec 2019 20:23:23 +0100 Subject: Addressed review comments --- techlibs/xilinx/synth_xilinx.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c66e1d750..90ab688e5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -85,7 +85,8 @@ struct SynthXilinxPass : public ScriptPass log(" do not use DSP48E1s to implement multipliers and associated logic\n"); log("\n"); log(" -noiopad\n"); - log(" disable I/O buffer insertion\n"); + log(" disable I/O buffer insertion (useful for hierarchical or \n"); + log(" out-of-context flows)\n"); log("\n"); log(" -noclkbuf\n"); log(" disable automatic clock buffer insertion\n"); @@ -210,7 +211,7 @@ struct SynthXilinxPass : public ScriptPass } if (args[argidx] == "-iopad") { continue; - } + } if (args[argidx] == "-noiopad") { noiopad = true; continue; -- cgit v1.2.3 From 666c6128a90de588ab26c876a257ea48edfded30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 22 Dec 2019 20:43:39 +0100 Subject: xilinx_dsp: Initial DSP48A/DSP48A1 support. --- techlibs/xilinx/synth_xilinx.cc | 5 ++++- techlibs/xilinx/xc3sda_dsp_map.v | 2 +- techlibs/xilinx/xc6s_dsp_map.v | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 971089b28..a19046911 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -387,7 +387,10 @@ struct SynthXilinxPass : public ScriptPass run("opt_expr -fine"); run("wreduce"); run("select -clear"); - run("xilinx_dsp"); + if (help_mode) + run("xilinx_dsp -family "); + else + run("xilinx_dsp -family " + family); run("chtype -set $mul t:$__soft_mul"); } } diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v index 87348a173..258f90395 100644 --- a/techlibs/xilinx/xc3sda_dsp_map.v +++ b/techlibs/xilinx/xc3sda_dsp_map.v @@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D(18'b0), .P(P_48), - .OPMODE(8'b0000010) + .OPMODE(8'b0000001) ); assign Y = P_48; endmodule diff --git a/techlibs/xilinx/xc6s_dsp_map.v b/techlibs/xilinx/xc6s_dsp_map.v index e8705723b..bdce60c14 100644 --- a/techlibs/xilinx/xc6s_dsp_map.v +++ b/techlibs/xilinx/xc6s_dsp_map.v @@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D(18'b0), .P(P_48), - .OPMODE(8'b0000010) + .OPMODE(8'b0000001) ); assign Y = P_48; endmodule -- cgit v1.2.3 From dadaf7ed788370c94a463e5e479bed4d540cdf4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 22 Dec 2019 14:30:04 +0000 Subject: xilinx: Test our DSP48A/DSP48A1 simulation models. --- techlibs/xilinx/cells_sim.v | 6 +- techlibs/xilinx/tests/.gitignore | 4 + techlibs/xilinx/tests/test_dsp48a1_model.sh | 17 ++ techlibs/xilinx/tests/test_dsp48a1_model.v | 331 ++++++++++++++++++++++++++++ techlibs/xilinx/tests/test_dsp_model.sh | 11 +- 5 files changed, 362 insertions(+), 7 deletions(-) create mode 100644 techlibs/xilinx/tests/test_dsp48a1_model.sh create mode 100644 techlibs/xilinx/tests/test_dsp48a1_model.v (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 804c2d70f..3bcbfc9aa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2099,7 +2099,7 @@ always @* begin 2'b00: XMUX <= 0; 2'b01: XMUX <= M; 2'b10: XMUX <= P; - 2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT}; + 2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT}; default: XMUX <= 48'hxxxxxxxxxxxx; endcase end @@ -2117,8 +2117,8 @@ end // The post-adder. wire signed [48:0] X_EXT; wire signed [48:0] Z_EXT; -assign X_EXT = XMUX; -assign Z_EXT = ZMUX; +assign X_EXT = {1'b0, XMUX}; +assign Z_EXT = {1'b0, ZMUX}; assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); // Cascade outputs. diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore index ef3699bd2..848f88d53 100644 --- a/techlibs/xilinx/tests/.gitignore +++ b/techlibs/xilinx/tests/.gitignore @@ -8,4 +8,8 @@ dsp_work*/ test_dsp_model_ref.v test_dsp_model_uut.v test_dsp_model +test_dsp48a_model_ref.v +test_dsp48a1_model_ref.v +test_dsp48a1_model_uut.v +test_dsp48a1_model *.vcd diff --git a/techlibs/xilinx/tests/test_dsp48a1_model.sh b/techlibs/xilinx/tests/test_dsp48a1_model.sh new file mode 100644 index 000000000..a14a78e72 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48a1_model.sh @@ -0,0 +1,17 @@ +#!/bin/bash +set -ex +if [ -z $ISE_DIR ]; then + ISE_DIR=/opt/Xilinx/ISE/14.7 +fi +sed 's/DSP48A1/MARKER1/; s/DSP48A/DSP48A_UUT/; s/MARKER1/DSP48A1_UUT/; /module DSP48A_UUT/,/endmodule/ p; /module DSP48A1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48a1_model_uut.v +if [ ! -f "test_dsp48a1_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v test_dsp48a1_model_ref.v +fi +if [ ! -f "test_dsp48a_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A.v test_dsp48a_model_ref.v +fi +for tb in mult_allreg mult_noreg mult_inreg +do + iverilog -s $tb -s glbl -o test_dsp48a1_model test_dsp48a1_model.v test_dsp48a1_model_uut.v test_dsp48a1_model_ref.v test_dsp48a_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v + vvp -N ./test_dsp48a1_model +done diff --git a/techlibs/xilinx/tests/test_dsp48a1_model.v b/techlibs/xilinx/tests/test_dsp48a1_model.v new file mode 100644 index 000000000..66346b47b --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48a1_model.v @@ -0,0 +1,331 @@ +`timescale 1ns / 1ps + +module testbench; + parameter integer A0REG = 1; + parameter integer A1REG = 1; + parameter integer B0REG = 1; + parameter integer B1REG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer PREG = 1; + parameter integer CARRYINREG = 1; + parameter integer CARRYOUTREG = 1; + parameter integer OPMODEREG = 1; + parameter CARRYINSEL = "OPMODE5"; + parameter RSTTYPE = "SYNC"; + + reg CLK; + reg CEA, CEB, CEC, CED, CEM, CEP, CECARRYIN, CEOPMODE; + reg RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE; + reg [17:0] A; + reg [17:0] B; + reg [47:0] C; + reg [17:0] D; + reg [47:0] PCIN; + reg [7:0] OPMODE; + reg CARRYIN; + + output CARRYOUTF, REF_CARRYOUTF; + output CARRYOUT, REF_CARRYOUT, REF_OLD_CARRYOUT; + output [35:0] M, REF_M; + output [47:0] P, REF_P, REF_OLD_P; + output [17:0] BCOUT, REF_BCOUT, REF_OLD_BCOUT; + output [47:0] PCOUT, REF_PCOUT, REF_OLD_PCOUT; + + integer errcount = 0; + + reg ERROR_FLAG = 0; + + task clkcycle; + begin + #5; + CLK = ~CLK; + #10; + CLK = ~CLK; + #2; + ERROR_FLAG = 0; + if (REF_BCOUT !== BCOUT || REF_OLD_BCOUT != BCOUT) begin + $display("ERROR at %1t: REF_BCOUT=%b REF_OLD_BCOUT=%b UUT_BCOUT=%b DIFF=%b", $time, REF_BCOUT, REF_OLD_BCOUT, BCOUT, REF_BCOUT ^ BCOUT); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_M !== M) begin + $display("ERROR at %1t: REF_M=%b UUT_M=%b DIFF=%b", $time, REF_M, M, REF_M ^ M); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_P !== P || REF_OLD_P != P) begin + $display("ERROR at %1t: REF_P=%b REF_OLD_P=%b UUT_P=%b DIFF=%b", $time, REF_P, REF_OLD_P, P, REF_P ^ P); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_PCOUT !== PCOUT || REF_OLD_PCOUT != PCOUT) begin + $display("ERROR at %1t: REF_PCOUT=%b REF_OLD_PCOUT=%b UUT_PCOUT=%b DIFF=%b", $time, REF_PCOUT, REF_OLD_PCOUT, PCOUT, REF_PCOUT ^ PCOUT); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_CARRYOUT !== CARRYOUT || (REF_OLD_CARRYOUT != CARRYOUT && !CARRYOUTREG)) begin + $display("ERROR at %1t: REF_CARRYOUT=%b REF_OLD_CARRYOUT=%b UUT_CARRYOUT=%b DIFF=%b", $time, REF_CARRYOUT, REF_OLD_CARRYOUT, CARRYOUT, REF_CARRYOUT ^ CARRYOUT); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_CARRYOUTF !== CARRYOUTF) begin + $display("ERROR at %1t: REF_CARRYOUTF=%b UUT_CARRYOUTF=%b", $time, REF_CARRYOUTF, CARRYOUTF); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + #3; + end + endtask + + reg config_valid = 0; + task drc; + begin + config_valid = 1; + + if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; + if (OPMODE[3:2] == 2'b10 && PREG != 1) config_valid = 0; + end + endtask + + initial begin + $dumpfile("test_dsp48a1_model.vcd"); + $dumpvars(0, testbench); + + #2; + CLK = 1'b0; + {CEA, CEB, CEC, CED, CEM, CEP, CECARRYIN, CEOPMODE} = 8'b11111111; + {A, B, C, D, PCIN, OPMODE, CARRYIN} = 0; + {RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE} = 8'b11111111; + repeat (10) begin + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + end + {RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE} = 0; + + repeat (10000) begin + clkcycle; + config_valid = 0; + while (!config_valid) begin + A = $urandom; + B = $urandom; + C = {$urandom, $urandom}; + D = $urandom; + PCIN = {$urandom, $urandom}; + + {CEA, CEB, CEC, CED, CEM, CEP, CECARRYIN, CEOPMODE} = $urandom | $urandom | $urandom; + {RSTA, RSTB, RSTC, RSTD, RSTM, RSTP, RSTCARRYIN, RSTOPMODE} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + {CARRYIN, OPMODE} = $urandom; + + drc; + end + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + DSP48A #( + .A0REG (A0REG), + .A1REG (A1REG), + .B0REG (B0REG), + .B1REG (B1REG), + .CREG (CREG), + .DREG (DREG), + .MREG (MREG), + .PREG (PREG), + .CARRYINREG (CARRYINREG), + .OPMODEREG (OPMODEREG), + .CARRYINSEL (CARRYINSEL), + .RSTTYPE (RSTTYPE) + ) ref_old ( + .A (A), + .B (B), + .C (C), + .D (D), + .PCIN (PCIN), + .CARRYIN (CARRYIN), + .OPMODE (OPMODE), + .BCOUT (REF_OLD_BCOUT), + .CARRYOUT (REF_OLD_CARRYOUT), + .P (REF_OLD_P), + .PCOUT (REF_OLD_PCOUT), + .CEA (CEA), + .CEB (CEB), + .CEC (CEC), + .CED (CED), + .CEM (CEM), + .CEP (CEP), + .CECARRYIN (CECARRYIN), + .CEOPMODE (CEOPMODE), + .CLK (CLK), + .RSTA (RSTA), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTD (RSTD), + .RSTM (RSTM), + .RSTP (RSTP), + .RSTCARRYIN (RSTCARRYIN), + .RSTOPMODE (RSTOPMODE) + ); + + DSP48A1 #( + .A0REG (A0REG), + .A1REG (A1REG), + .B0REG (B0REG), + .B1REG (B1REG), + .CREG (CREG), + .DREG (DREG), + .MREG (MREG), + .PREG (PREG), + .CARRYINREG (CARRYINREG), + .CARRYOUTREG (CARRYOUTREG), + .OPMODEREG (OPMODEREG), + .CARRYINSEL (CARRYINSEL), + .RSTTYPE (RSTTYPE) + ) ref ( + .A (A), + .B (B), + .C (C), + .D (D), + .PCIN (PCIN), + .CARRYIN (CARRYIN), + .OPMODE (OPMODE), + .BCOUT (REF_BCOUT), + .CARRYOUTF (REF_CARRYOUTF), + .CARRYOUT (REF_CARRYOUT), + .P (REF_P), + .M (REF_M), + .PCOUT (REF_PCOUT), + .CEA (CEA), + .CEB (CEB), + .CEC (CEC), + .CED (CED), + .CEM (CEM), + .CEP (CEP), + .CECARRYIN (CECARRYIN), + .CEOPMODE (CEOPMODE), + .CLK (CLK), + .RSTA (RSTA), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTD (RSTD), + .RSTM (RSTM), + .RSTP (RSTP), + .RSTCARRYIN (RSTCARRYIN), + .RSTOPMODE (RSTOPMODE) + ); + + DSP48A1_UUT #( + .A0REG (A0REG), + .A1REG (A1REG), + .B0REG (B0REG), + .B1REG (B1REG), + .CREG (CREG), + .DREG (DREG), + .MREG (MREG), + .PREG (PREG), + .CARRYINREG (CARRYINREG), + .CARRYOUTREG (CARRYOUTREG), + .OPMODEREG (OPMODEREG), + .CARRYINSEL (CARRYINSEL), + .RSTTYPE (RSTTYPE) + ) uut ( + .A (A), + .B (B), + .C (C), + .D (D), + .PCIN (PCIN), + .CARRYIN (CARRYIN), + .OPMODE (OPMODE), + .BCOUT (BCOUT), + .CARRYOUTF (CARRYOUTF), + .CARRYOUT (CARRYOUT), + .P (P), + .M (M), + .PCOUT (PCOUT), + .CEA (CEA), + .CEB (CEB), + .CEC (CEC), + .CED (CED), + .CEM (CEM), + .CEP (CEP), + .CECARRYIN (CECARRYIN), + .CEOPMODE (CEOPMODE), + .CLK (CLK), + .RSTA (RSTA), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTD (RSTD), + .RSTM (RSTM), + .RSTP (RSTP), + .RSTCARRYIN (RSTCARRYIN), + .RSTOPMODE (RSTOPMODE) + ); +endmodule + +module mult_noreg; + testbench #( + .A0REG (0), + .A1REG (0), + .B0REG (0), + .B1REG (0), + .CREG (0), + .DREG (0), + .MREG (0), + .PREG (0), + .CARRYINREG (0), + .CARRYOUTREG (0), + .OPMODEREG (0), + .CARRYINSEL ("CARRYIN"), + .RSTTYPE ("SYNC") + ) testbench (); +endmodule + +module mult_allreg; + testbench #( + .A0REG (1), + .A1REG (1), + .B0REG (1), + .B1REG (1), + .CREG (1), + .DREG (1), + .MREG (1), + .PREG (1), + .CARRYINREG (1), + .CARRYOUTREG (1), + .OPMODEREG (1), + .CARRYINSEL ("OPMODE5"), + .RSTTYPE ("SYNC") + ) testbench (); +endmodule + +module mult_inreg; + testbench #( + .A0REG (1), + .A1REG (1), + .B0REG (1), + .B1REG (1), + .CREG (1), + .DREG (1), + .MREG (0), + .PREG (0), + .CARRYINREG (1), + .CARRYOUTREG (0), + .OPMODEREG (0), + .CARRYINSEL ("CARRYIN"), + .RSTTYPE ("SYNC") + ) testbench (); +endmodule diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index ae925c402..d005cd40c 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -1,14 +1,17 @@ #!/bin/bash set -ex +if [ -z $VIVADO_DIR ]; then + VIVADO_DIR=/opt/Xilinx/Vivado/2019.1 +fi sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v if [ ! -f "test_dsp_model_ref.v" ]; then - cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v + cp $VIVADO_DIR/data/verilog/src/unisims/DSP48E1.v test_dsp_model_ref.v fi for tb in macc_overflow_underflow \ - simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ - mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ + mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc do - iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v + iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v $VIVADO_DIR/data/verilog/src/glbl.v vvp -N ./test_dsp_model done -- cgit v1.2.3 From 71906fab51c60d22ee5b145df0429287ab9d2d65 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Dec 2019 16:57:08 -0800 Subject: Nitpick cleanup for ecp5 --- techlibs/ecp5/cells_sim.v | 12 ++---------- techlibs/ecp5/synth_ecp5.cc | 2 +- 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f467218cc..0d3ec4e5b 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -1,5 +1,6 @@ // --------------------------------------- +(* lib_whitebox *) module LUT4(input A, B, C, D, output Z); parameter [15:0] INIT = 16'h0000; wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; @@ -31,13 +32,8 @@ module CCU2C( // First half wire LUT4_0, LUT2_0; -`ifdef _ABC - assign LUT4_0 = INIT0[{D0, C0, B0, A0}]; - assign LUT2_0 = INIT0[{2'b00, B0, A0}]; -`else LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); -`endif wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; assign S0 = LUT4_0 ^ gated_cin_0; @@ -46,13 +42,8 @@ module CCU2C( // Second half wire LUT4_1, LUT2_1; -`ifdef _ABC - assign LUT4_1 = INIT1[{D1, C1, B1, A1}]; - assign LUT2_1 = INIT1[{2'b00, B1, A1}]; -`else LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); -`endif wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; assign S1 = LUT4_1 ^ gated_cin_1; @@ -209,6 +200,7 @@ endmodule // --------------------------------------- +(* lib_whitebox *) module LUT2(input A, B, output Z); parameter [3:0] INIT = 4'h0; wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index b71bb2395..a0ea6d1f9 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v"); + run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } -- cgit v1.2.3 From aa6d06c1b5b0083096ad547b0ad2600fcdc854f4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 12:09:53 -0800 Subject: Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. --- techlibs/achronix/synth_achronix.cc | 4 ++-- techlibs/anlogic/synth_anlogic.cc | 2 +- techlibs/coolrunner2/synth_coolrunner2.cc | 2 +- techlibs/easic/synth_easic.cc | 2 +- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/gowin/synth_gowin.cc | 2 +- techlibs/greenpak4/synth_greenpak4.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel/synth_intel.cc | 2 +- techlibs/sf2/synth_sf2.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 11 files changed, 13 insertions(+), 13 deletions(-) (limited to 'techlibs') diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 626860d9c..3dbf20911 100755 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff", "(only if -retime)"); + run("abc -markgroups -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) { - run("abc -lut 4" + string(retime ? " -dff" : "")); + run("abc -lut 4" + string(retime ? " -dff -D 1" : "")); run("clean"); } diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index b87fc8566..310c9c76c 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index 014c68622..d73241fa8 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass if (check_label("map_pla")) { - run("abc -sop -I 40 -P 56"); + run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : "")); run("clean"); } diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index dd9e3dab7..7bacc7890 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass run("techmap"); run("opt -fast"); if (retime || help_mode) { - run("abc -dff", " (only if -retime)"); + run("abc -dff -D 1", " (only if -retime)"); run("opt_clean", "(only if -retime)"); } } diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index a0ea6d1f9..24e300fa8 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -290,7 +290,7 @@ struct SynthEcp5Pass : public ScriptPass else run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 6cf058f29..5acc096a3 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -209,7 +209,7 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); run("techmap -map +/techmap.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); run("splitnets"); } diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index eeb001b46..3222be2e3 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib"); run("opt -fast"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index ed7a16c08..fe1228165 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); } if (retime || help_mode) - run(abc + " -dff", "(only if -retime)"); + run(abc + " -dff -D 1", "(only if -retime)"); run("ice40_opt"); } diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c8c690e45..f033f3acc 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -210,7 +210,7 @@ struct SynthIntelPass : public ScriptPass { run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) - run("abc -markgroups -dff", "(only if -retime)"); + run("abc -markgroups -dff -D 1", "(only if -retime)"); } if (check_label("map_luts")) { diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 0924df7a6..3c5a58b4c 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/sf2/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a19046911..afe4d483b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -555,9 +555,9 @@ struct SynthXilinxPass : public ScriptPass } else { if (nowidelut) - run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : "")); else - run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : "")); } run("clean"); -- cgit v1.2.3 From c9e3b26412d6e5c5405f131b7526dec632fbb315 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 12:05:52 -0800 Subject: Disable synth_gowin -abc9 as it offers no advantages yet --- techlibs/gowin/synth_gowin.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 5acc096a3..8431473f0 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -62,16 +62,16 @@ struct SynthGowinPass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log(" -nowidelut\n"); log(" do not use muxes to implement LUTs larger than LUT4s\n"); log("\n"); log(" -noiopads\n"); log(" do not emit IOB at top level ports\n"); - log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + //log("\n"); + //log(" -abc9\n"); + //log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -144,10 +144,10 @@ struct SynthGowinPass : public ScriptPass nowidelut = true; continue; } - if (args[argidx] == "-abc9") { - abc9 = true; - continue; - } + //if (args[argidx] == "-abc9") { + // abc9 = true; + // continue; + //} if (args[argidx] == "-noiopads") { noiopads = true; continue; @@ -227,13 +227,13 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_luts")) { - if (nowidelut && abc9) { + /*if (nowidelut && abc9) { run("abc9 -lut 4"); - } else if (nowidelut && !abc9) { + } else*/ if (nowidelut && !abc9) { run("abc -lut 4"); - } else if (!nowidelut && abc9) { + } else /*if (!nowidelut && abc9) { run("abc9 -lut 4:8"); - } else if (!nowidelut && !abc9) { + } else*/ if (!nowidelut && !abc9) { run("abc -lut 4:8"); } run("clean"); -- cgit v1.2.3 From 79448f9be035c88589b4e9c0de6b2bdc5acbd4df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 12:11:45 -0800 Subject: Update doc that "-retime" calls abc with "-dff -D 1" --- techlibs/achronix/synth_achronix.cc | 2 +- techlibs/anlogic/synth_anlogic.cc | 2 +- techlibs/coolrunner2/synth_coolrunner2.cc | 2 +- techlibs/easic/synth_easic.cc | 2 +- techlibs/ecp5/synth_ecp5.cc | 2 +- techlibs/efinix/synth_efinix.cc | 4 ++-- techlibs/greenpak4/synth_greenpak4.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel/synth_intel.cc | 2 +- techlibs/sf2/synth_sf2.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 3dbf20911..1dc6bdb2f 100755 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -52,7 +52,7 @@ struct SynthAchronixPass : public ScriptPass { log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 310c9c76c..57b8a2b26 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -58,7 +58,7 @@ struct SynthAnlogicPass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index d73241fa8..388e2b792 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -55,7 +55,7 @@ struct SynthCoolrunner2Pass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index 7bacc7890..b4a3a1ac9 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -56,7 +56,7 @@ struct SynthEasicPass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 24e300fa8..1ecb9cac3 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -62,7 +62,7 @@ struct SynthEcp5Pass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log(" -noccu2\n"); log(" do not use CCU2 cells in output netlist\n"); diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 26a8d4eda..6fe0182ac 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -58,7 +58,7 @@ struct SynthEfinixPass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -164,7 +164,7 @@ struct SynthEfinixPass : public ScriptPass run("opt -undriven -fine"); run("techmap -map +/techmap.v -map +/efinix/arith_map.v"); if (retime || help_mode) - run("abc -dff", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 3222be2e3..e1fbe6b69 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -59,7 +59,7 @@ struct SynthGreenPAK4Pass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index fe1228165..463c2063a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -65,7 +65,7 @@ struct SynthIce40Pass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log(" -nocarry\n"); log(" do not use SB_CARRY cells in output netlist\n"); diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index f033f3acc..a3d346407 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -71,7 +71,7 @@ struct SynthIntelPass : public ScriptPass { log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 3c5a58b4c..543dfdb9e 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -67,7 +67,7 @@ struct SynthSf2Pass : public ScriptPass log(" insert direct PAD->global_net buffers\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index afe4d483b..215a48f95 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,7 +110,7 @@ struct SynthXilinxPass : public ScriptPass log(" flatten design before synthesis\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); -- cgit v1.2.3 From d7ada6649766cfa32b077a744e066476278afd02 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 14:13:16 -0800 Subject: Add "synth_xilinx -dff" option, cleanup abc9 --- techlibs/xilinx/abc9_map.v | 84 +++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/synth_xilinx.cc | 16 +++++++- 2 files changed, 98 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index d2d7d9114..1e17d4766 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -83,6 +83,7 @@ module FDRE (output Q, input C, CE, D, R); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -113,9 +114,21 @@ module FDRE (output Q, input C, CE, D, R); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDRE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_R_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .R(R) + ); +`endif endmodule module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -140,6 +153,14 @@ module FDRE_1 (output Q, input C, CE, D, R); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDRE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .R(R) + ); +`endif endmodule module FDCE (output Q, input C, CE, D, CLR); @@ -147,6 +168,7 @@ module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -190,9 +212,21 @@ module FDCE (output Q, input C, CE, D, CLR); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDCE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_CLR_INVERTED(IS_CLR_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) + ); +`endif endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -228,6 +262,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDCE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) + ); +`endif endmodule module FDPE (output Q, input C, CE, D, PRE); @@ -235,6 +277,7 @@ module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -276,9 +319,21 @@ module FDPE (output Q, input C, CE, D, PRE); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDPE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_PRE_INVERTED(IS_PRE_INVERTED), + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) + ); +`endif endmodule module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; +`ifdef DFF_MODE wire QQ, $nextQ, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -314,6 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; +`else + (* abc9_keep *) + FDPE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) + ); +`endif endmodule module FDSE (output Q, input C, CE, D, S); @@ -321,6 +384,7 @@ module FDSE (output Q, input C, CE, D, S); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -350,9 +414,21 @@ module FDSE (output Q, input C, CE, D, S); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDSE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .S(S) + ); +`endif endmodule module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; +`ifdef DFF_MODE wire QQ, $nextQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -376,6 +452,14 @@ module FDSE_1 (output Q, input C, CE, D, S); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDSE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .S(S) + ); +`endif endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ac6fedc58..e7069f286 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -109,6 +109,9 @@ struct SynthXilinxPass : public ScriptPass log(" -flatten\n"); log(" flatten design before synthesis\n"); log("\n"); + log(" -dff\n"); + log(" run 'abc9' with -dff option\n"); + log("\n"); log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); @@ -122,7 +125,8 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9; + bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; + bool abc9, dff_mode; bool flatten_before_abc; int widemux; @@ -148,6 +152,7 @@ struct SynthXilinxPass : public ScriptPass nodsp = false; uram = false; abc9 = false; + dff_mode = false; flatten_before_abc = false; widemux = 0; } @@ -256,6 +261,10 @@ struct SynthXilinxPass : public ScriptPass uram = true; continue; } + if (args[argidx] == "-dff") { + dff_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -540,7 +549,10 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); - run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); + std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1"; + if (dff_mode) + techmap_args += " -D DFF_MODE"; + run("techmap " + techmap_args); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); -- cgit v1.2.3 From a038294a87b44a8eadfb62453f1fd76eec5a04ef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 14:19:29 -0800 Subject: Tidy up abc9_map.v --- techlibs/xilinx/abc9_map.v | 206 ++++++++++++++++++++++----------------------- 1 file changed, 103 insertions(+), 103 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 1e17d4766..2cabe57d7 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -49,10 +49,10 @@ // || Comb box || // || || // || /\/\/\/\ || -// D -->>-----< > || +------+ -// R -->>-----< Comb. > || |$__ABC| -// CE -->>-----< logic >--->>-- $nextQ --| _FF_ |--+-->> Q -// $abc9_currQ +-->>-----< > || +------+ | +// D -->>-----< > || +// R -->>-----< Comb. > || +----------+ +// CE -->>-----< logic >--->>-- $Q --|$__ABC_FF_|--+-->> Q +// $abc9_currQ +-->>-----< > || +----------+ | // | || \/\/\/\/ || | // | || || | // | ++==================++ | @@ -84,7 +84,7 @@ module FDRE (output Q, input C, CE, D, R); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; `ifdef DFF_MODE - wire QQ, $nextQ; + wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDSE #( @@ -93,7 +93,7 @@ module FDRE (output Q, input C, CE, D, R); .IS_D_INVERTED(IS_D_INVERTED), .IS_S_INVERTED(IS_R_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R) + .D(~D), .Q($Q), .C(C), .CE(CE), .S(R) ); end else begin @@ -104,11 +104,11 @@ module FDRE (output Q, input C, CE, D, R); .IS_D_INVERTED(IS_D_INVERTED), .IS_R_INVERTED(IS_R_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) + .D(D), .Q($Q), .C(C), .CE(CE), .R(R) ); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; @@ -129,13 +129,13 @@ endmodule module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; `ifdef DFF_MODE - wire QQ, $nextQ; + wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDSE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R) + .D(~D), .Q($Q), .C(C), .CE(CE), .S(R) ); end else begin @@ -143,11 +143,11 @@ module FDRE_1 (output Q, input C, CE, D, R); FDRE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) + .D(D), .Q($Q), .C(C), .CE(CE), .R(R) ); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; @@ -169,7 +169,7 @@ module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; `ifdef DFF_MODE - wire QQ, $nextQ, $abc9_currQ; + wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDPE #( @@ -178,7 +178,7 @@ module FDCE (output Q, input C, CE, D, CLR); .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR) + .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR) // ^^^ Note that async // control is not directly // supported by abc9 but its @@ -186,7 +186,7 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC1 below ); // Since this is an async flop, async behaviour is dealt with here - \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -196,7 +196,7 @@ module FDCE (output Q, input C, CE, D, CLR); .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_CLR_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR) // ^^^ Note that async // control is not directly // supported by abc9 but its @@ -204,9 +204,9 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC0 below ); // Since this is an async flop, async behaviour is dealt with here - \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; @@ -227,36 +227,36 @@ endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; `ifdef DFF_MODE - wire QQ, $nextQ, $abc9_currQ; + wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDPE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR) + .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR) // ^^^ Note that async // control is not directly // supported by abc9 but its // behaviour is captured by // $__ABC9_ASYNC1 below ); - \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); end else begin assign Q = QQ; FDCE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) + .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR) // ^^^ Note that async // control is not directly // supported by abc9 but its // behaviour is captured by // $__ABC9_ASYNC0 below ); - \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; @@ -278,7 +278,7 @@ module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; `ifdef DFF_MODE - wire QQ, $nextQ, $abc9_currQ; + wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDCE #( @@ -287,14 +287,14 @@ module FDPE (output Q, input C, CE, D, PRE); .IS_D_INVERTED(IS_D_INVERTED), .IS_CLR_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE) + .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE) // ^^^ Note that async // control is not directly // supported by abc9 but its // behaviour is captured by // $__ABC9_ASYNC0 below ); - \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -304,16 +304,16 @@ module FDPE (output Q, input C, CE, D, PRE); .IS_D_INVERTED(IS_D_INVERTED), .IS_PRE_INVERTED(IS_PRE_INVERTED), ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE) // ^^^ Note that async // control is not directly // supported by abc9 but its // behaviour is captured by // $__ABC9_ASYNC1 below ); - \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; @@ -334,36 +334,36 @@ endmodule module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; `ifdef DFF_MODE - wire QQ, $nextQ, $abc9_currQ; + wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDCE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE) + .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE) // ^^^ Note that async // control is not directly // supported by abc9 but its // behaviour is captured by // $__ABC9_ASYNC0 below ); - \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); end else begin assign Q = QQ; FDPE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) + .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE) // ^^^ Note that async // control is not directly // supported by abc9 but its // behaviour is captured by // $__ABC9_ASYNC1 below ); - \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; @@ -385,7 +385,7 @@ module FDSE (output Q, input C, CE, D, S); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; `ifdef DFF_MODE - wire QQ, $nextQ; + wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDRE #( @@ -394,7 +394,7 @@ module FDSE (output Q, input C, CE, D, S); .IS_D_INVERTED(IS_D_INVERTED), .IS_R_INVERTED(IS_S_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S) + .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) ); end else begin @@ -405,10 +405,10 @@ module FDSE (output Q, input C, CE, D, S); .IS_D_INVERTED(IS_D_INVERTED), .IS_S_INVERTED(IS_S_INVERTED) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) + .D(D), .Q($Q), .C(C), .CE(CE), .S(S) ); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; @@ -429,13 +429,13 @@ endmodule module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; `ifdef DFF_MODE - wire QQ, $nextQ; + wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDRE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S) + .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) ); end else begin @@ -443,10 +443,10 @@ module FDSE_1 (output Q, input C, CE, D, S); FDSE_1 #( .INIT(1'b0) ) _TECHMAP_REPLACE_ ( - .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) + .D(D), .Q($Q), .C(C), .CE(CE), .S(S) ); end endgenerate - \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ)); + $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); // Special signals wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; @@ -472,17 +472,17 @@ module RAM32X1D ( ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; - wire \$DPO , \$SPO ; + wire $DPO, $SPO; RAM32X1D #( .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .DPO(\$DPO ), .SPO(\$SPO ), + .DPO($DPO), .SPO($SPO), .D(D), .WCLK(WCLK), .WE(WE), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4) ); - \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO)); - \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); + $__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO)); + $__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); endmodule module RAM64X1D ( @@ -495,17 +495,17 @@ module RAM64X1D ( ); parameter INIT = 64'h0; parameter IS_WCLK_INVERTED = 1'b0; - wire \$DPO , \$SPO ; + wire $DPO, $SPO; RAM64X1D #( .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .DPO(\$DPO ), .SPO(\$SPO ), + .DPO($DPO), .SPO($SPO), .D(D), .WCLK(WCLK), .WE(WE), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5) ); - \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO)); - \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); + $__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO)); + $__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO)); endmodule module RAM128X1D ( @@ -517,17 +517,17 @@ module RAM128X1D ( ); parameter INIT = 128'h0; parameter IS_WCLK_INVERTED = 1'b0; - wire \$DPO , \$SPO ; + wire $DPO, $SPO; RAM128X1D #( .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .DPO(\$DPO ), .SPO(\$SPO ), + .DPO($DPO), .SPO($SPO), .D(D), .WCLK(WCLK), .WE(WE), .A(A), .DPRA(DPRA) ); - \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO)); - \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO)); + $__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO)); + $__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO)); endmodule module RAM32M ( @@ -551,24 +551,24 @@ module RAM32M ( parameter [63:0] INIT_C = 64'h0000000000000000; parameter [63:0] INIT_D = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire [1:0] \$DOA , \$DOB , \$DOC , \$DOD ; + wire [1:0] $DOA, $DOB, $DOC, $DOD; RAM32M #( .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ), + .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD), .WCLK(WCLK), .WE(WE), .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) ); - \$__ABC9_LUT6 doa0 (.A(\$DOA [0]), .S({1'b1, ADDRA}), .Y(DOA[0])); - \$__ABC9_LUT6 doa1 (.A(\$DOA [1]), .S({1'b1, ADDRA}), .Y(DOA[1])); - \$__ABC9_LUT6 dob0 (.A(\$DOB [0]), .S({1'b1, ADDRB}), .Y(DOB[0])); - \$__ABC9_LUT6 dob1 (.A(\$DOB [1]), .S({1'b1, ADDRB}), .Y(DOB[1])); - \$__ABC9_LUT6 doc0 (.A(\$DOC [0]), .S({1'b1, ADDRC}), .Y(DOC[0])); - \$__ABC9_LUT6 doc1 (.A(\$DOC [1]), .S({1'b1, ADDRC}), .Y(DOC[1])); - \$__ABC9_LUT6 dod0 (.A(\$DOD [0]), .S({1'b1, ADDRD}), .Y(DOD[0])); - \$__ABC9_LUT6 dod1 (.A(\$DOD [1]), .S({1'b1, ADDRD}), .Y(DOD[1])); + $__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0])); + $__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1])); + $__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0])); + $__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1])); + $__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0])); + $__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1])); + $__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0])); + $__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1])); endmodule module RAM64M ( @@ -592,20 +592,20 @@ module RAM64M ( parameter [63:0] INIT_C = 64'h0000000000000000; parameter [63:0] INIT_D = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; - wire \$DOA , \$DOB , \$DOC , \$DOD ; + wire $DOA, $DOB, $DOC, $DOD; RAM64M #( .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D), .IS_WCLK_INVERTED(IS_WCLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ), + .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD), .WCLK(WCLK), .WE(WE), .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD), .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID) ); - \$__ABC9_LUT6 doa (.A(\$DOA ), .S(ADDRA), .Y(DOA)); - \$__ABC9_LUT6 dob (.A(\$DOB ), .S(ADDRB), .Y(DOB)); - \$__ABC9_LUT6 doc (.A(\$DOC ), .S(ADDRC), .Y(DOC)); - \$__ABC9_LUT6 dod (.A(\$DOD ), .S(ADDRD), .Y(DOD)); + $__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA)); + $__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB)); + $__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC)); + $__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD)); endmodule module SRL16E ( @@ -614,14 +614,14 @@ module SRL16E ( ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; - wire \$Q ; + wire $Q; SRL16E #( .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .Q(\$Q ), + .Q($Q), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D) ); - \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); + $__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q)); endmodule module SRLC32E ( @@ -632,14 +632,14 @@ module SRLC32E ( ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; - wire \$Q ; + wire $Q; SRLC32E #( .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED) ) _TECHMAP_REPLACE_ ( - .Q(\$Q ), .Q31(Q31), + .Q($Q), .Q31(Q31), .A(A), .CE(CE), .CLK(CLK), .D(D) ); - \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q)); + $__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q)); endmodule module DSP48E1 ( @@ -828,15 +828,15 @@ __CELL__ #( if (AREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); + $__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); + $__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); + $__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; else if (techmap_guard) @@ -847,27 +847,27 @@ __CELL__ #( assign pAD = 1'bx; if (PREG == 0) begin if (MREG == 1) - \$__ABC9_REG rM (.Q(pM)); + $__ABC9_REG rM (.Q(pM)); else assign pM = 1'bx; assign pP = 1'bx; end else begin assign pM = 1'bx; - \$__ABC9_REG rP (.Q(pP)); + $__ABC9_REG rP (.Q(pP)); end if (MREG == 0 && PREG == 0) assign mP = oP, mPCOUT = oPCOUT; else assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC9_DSP48E1_MULT_P_MUX muxP ( + $__ABC9_DSP48E1_MULT_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); - \$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( + $__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC9_DSP48E1_MULT ) + `DSP48E1_INST($__ABC9_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin // Disconnect the A-input if MREG is enabled, since @@ -875,26 +875,26 @@ __CELL__ #( if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); + $__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); + $__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); + $__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0 && ADREG == 0) assign iD = D, pD = 1'bx; else - \$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); + $__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); if (PREG == 0) begin if (MREG == 1) begin assign pAD = 1'bx; - \$__ABC9_REG rM (.Q(pM)); + $__ABC9_REG rM (.Q(pM)); end else begin if (ADREG == 1) - \$__ABC9_REG rAD (.Q(pAD)); + $__ABC9_REG rAD (.Q(pAD)); else assign pAD = 1'bx; assign pM = 1'bx; @@ -902,21 +902,21 @@ __CELL__ #( assign pP = 1'bx; end else begin assign pAD = 1'bx, pM = 1'bx; - \$__ABC9_REG rP (.Q(pP)); + $__ABC9_REG rP (.Q(pP)); end if (MREG == 0 && PREG == 0) assign mP = oP, mPCOUT = oPCOUT; else assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP ( + $__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); - \$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( + $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT ) + `DSP48E1_INST($__ABC9_DSP48E1_MULT_DPORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin // Disconnect the A-input if MREG is enabled, since @@ -924,15 +924,15 @@ __CELL__ #( if (AREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); + $__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); + $__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); + $__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); assign pD = 1'bx; @@ -943,7 +943,7 @@ __CELL__ #( $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); assign pM = 1'bx; if (PREG == 1) - \$__ABC9_REG rP (.Q(pP)); + $__ABC9_REG rP (.Q(pP)); else assign pP = 1'bx; @@ -951,14 +951,14 @@ __CELL__ #( assign mP = oP, mPCOUT = oPCOUT; else assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC9_DSP48E1_P_MUX muxP ( + $__ABC9_DSP48E1_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); - \$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT ( + $__ABC9_DSP48E1_PCOUT_MUX muxPCOUT ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC9_DSP48E1 ) + `DSP48E1_INST($__ABC9_DSP48E1 ) end else $error("Invalid DSP48E1 configuration"); -- cgit v1.2.3 From eb4e767053f4731c9f4b82c4dd53504e5fe50802 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Dec 2019 12:03:19 -0800 Subject: Do not offset FD* box timings due to -46ps Tsu --- techlibs/xilinx/abc9_xc7.box | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index a2d119284..16606d14e 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -53,50 +53,59 @@ $__ABC9_ASYNC0 1000 1 2 1 $__ABC9_ASYNC1 1001 1 2 1 0 764 -# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to -# reflect the -46ps Tsu -# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 -# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 + +# NB: Inputs/Outputs must be ordered alphabetically +# (with exception for \$currQ) # Inputs: C CE D R \$currQ # Outputs: Q FDRE 1100 1 5 1 -0 151 0 446 0 +#0 109 -46 404 0 +0 109 0 404 0 # Clamp -46ps Tsu # Inputs: C CE D R \$currQ # Outputs: Q FDRE_1 1101 1 5 1 -0 151 0 446 0 +#0 109 0 -46 404 +0 109 0 0 404 # Clamp -46ps Tsu # Inputs: C CE CLR D \$currQ # Outputs: Q FDCE 1102 1 5 1 -0 151 806 0 0 +#0 109 764 -46 0 +0 109 764 0 0 # Clamp -46ps Tsu # Inputs: C CE CLR D \$currQ # Outputs: Q FDCE_1 1103 1 5 1 -0 151 806 0 0 +#0 109 764 -46 0 +0 109 764 0 0 # Clamp -46ps Tsu # Inputs: C CE D PRE \$currQ # Outputs: Q FDPE 1104 1 5 1 -0 151 0 806 0 +#0 109 -46 764 0 +0 109 0 764 0 # Clamp -46ps Tsu # Inputs: C CE D PRE \$currQ # Outputs: Q FDPE_1 1105 1 5 1 -0 151 0 806 0 +#0 109 -46 764 0 +0 109 0 764 0 # Clamp -46ps Tsu # Inputs: C CE D S \$currQ # Outputs: Q FDSE 1106 1 5 1 -0 151 0 446 0 +#0 109 -46 446 0 +0 109 0 446 0 # Clamp -46ps Tsu # Inputs: C CE D S \$currQ # Outputs: Q FDSE_1 1107 1 5 1 -0 151 0 446 0 +#0 109 -46 446 0 +0 109 0 446 0 # Clamp -46ps Tsu # SLICEM/A6LUT # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} -- cgit v1.2.3 From 543bd2de6c00f98577263439ebdada7bcda249ab Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Dec 2019 12:15:33 -0800 Subject: Update timings for Xilinx S7 cells --- techlibs/xilinx/cells_sim.v | 50 +++++++++++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 15 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3bcbfc9aa..72e684af5 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1112,8 +1112,8 @@ module RAM16X1D_1 ( endmodule module RAM32X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc9_arrival=1153 *) + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857 + (* abc9_arrival=1188 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -1135,8 +1135,8 @@ module RAM32X1D ( endmodule module RAM32X1D_1 ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc9_arrival=1153 *) + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857 + (* abc9_arrival=1188 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -1158,7 +1158,7 @@ module RAM32X1D_1 ( endmodule module RAM64X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 (* abc9_arrival=1153 *) output DPO, SPO, input D, @@ -1181,7 +1181,7 @@ module RAM64X1D ( endmodule module RAM64X1D_1 ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 (* abc9_arrival=1153 *) output DPO, SPO, input D, @@ -1204,8 +1204,9 @@ module RAM64X1D_1 ( endmodule module RAM128X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc9_arrival=1153 *) + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 + // plus 204ps to cross MUXF7 + (* abc9_arrival=1357 *) output DPO, SPO, input D, (* clkbuf_sink *) @@ -1244,9 +1245,18 @@ endmodule // Multi port. module RAM32M ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc9_arrival=1153 *) - output [1:0] DOA, DOB, DOC, DOD, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857 + (* abc9_arrival=1188 *) + output [1:0] DOA, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925 + (* abc9_arrival=1187 *) + output [1:0] DOB, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993 + (* abc9_arrival=1180 *) + output [1:0] DOC, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061 + (* abc9_arrival=1190 *) + output [1:0] DOD, input [4:0] ADDRA, ADDRB, ADDRC, ADDRD, input [1:0] DIA, DIB, DIC, DID, (* clkbuf_sink *) @@ -1347,9 +1357,18 @@ module RAM32M16 ( endmodule module RAM64M ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889 (* abc9_arrival=1153 *) - output DOA, DOB, DOC, DOD, + output DOA, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc9_arrival=1161 *) + output DOB, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025 + (* abc9_arrival=1158 *) + output DOC, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093 + (* abc9_arrival=1163 *) + output DOD, input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, input DIA, DIB, DIC, DID, (* clkbuf_sink *) @@ -1508,7 +1527,7 @@ module SRL16 ( endmodule module SRL16E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 (* abc9_arrival=1472 *) output Q, input A0, A1, A2, A3, CE, @@ -1572,9 +1591,10 @@ module SRLC16E ( endmodule module SRLC32E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905 (* abc9_arrival=1472 *) output Q, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904 (* abc9_arrival=1114 *) output Q31, input [4:0] A, -- cgit v1.2.3 From 379dcda1398ea7a1325f82340148359ffe2bf548 Mon Sep 17 00:00:00 2001 From: Niklas Nisbeth Date: Tue, 31 Dec 2019 02:38:10 +0100 Subject: ice40: Demote conflicting FF init values to a warning --- techlibs/ice40/ice40_ffinit.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index 3089d8932..c098736e9 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -78,10 +78,12 @@ struct Ice40FfinitPass : public Pass { continue; if (initbits.count(bit)) { - if (initbits.at(bit) != val) - log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n", + if (initbits.at(bit) != val) { + log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n", log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val), log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit))); + initbits.at(bit) = State::Sx; + } continue; } @@ -114,6 +116,10 @@ struct Ice40FfinitPass : public Pass { continue; State val = initbits.at(bit_q); + + if (val == State::Sx) + continue; + handled_initbits.insert(bit_q); log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type), -- cgit v1.2.3 From 789211d9b3a6892c72d22a09bf2299075337f9f9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 11:13:50 -0800 Subject: Fix incorrect $__ABC9_ASYNC[01] box --- techlibs/xilinx/abc9_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 2cabe57d7..a3f9e311e 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -186,7 +186,7 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC1 below ); // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -204,7 +204,7 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC0 below ); // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end endgenerate $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); -- cgit v1.2.3 From b4663a987bc1bac3aa4cccab99dc191825902205 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 11:14:11 -0800 Subject: Fix attributes on $__ABC9_ASYNC[01] whitebox --- techlibs/xilinx/abc9_model.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index c793396a4..11250123d 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -34,13 +34,13 @@ module \$__ABC9_FF_ (input D, output Q); endmodule // Box to emulate async behaviour of FDC* -(* abc_box_id = 1000 *) +(* abc9_box_id = 1000, lib_whitebox *) module \$__ABC9_ASYNC0 (input A, S, output Y); assign Y = S ? 1'b0 : A; endmodule // Box to emulate async behaviour of FDP* -(* abc_box_id = 1001 *) +(* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); assign Y = S ? 1'b0 : A; endmodule -- cgit v1.2.3 From 4cdba00e25d892b90c0ee48716c17dec60e472db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 15:24:02 -0800 Subject: FDCE ports to be alphabetical --- techlibs/xilinx/cells_sim.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4d20e1d2c..982ccad72 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -405,10 +405,10 @@ module FDCE ( (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) - input D, (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR + input CLR, + (* invertible_pin = "IS_D_INVERTED" *) + input D ); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; -- cgit v1.2.3 From 6b825c719b5bf6f63d3397cfadf8293b5d14dde6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 15:25:46 -0800 Subject: Update abc9_xc7.box comments --- techlibs/xilinx/abc9_xc7.box | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 16606d14e..67523124a 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -1,8 +1,9 @@ # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) # Average across F7[AB]MUX # Inputs: I0 I1 S0 @@ -15,7 +16,7 @@ MUXF7 1 1 3 1 MUXF8 2 1 3 1 104 94 273 -# Box containing MUXF7.[AB] + MUXF8, +# Box containing MUXF7.[AB] + MUXF8 # Necessary to make these an atomic unit so that # ABC cannot optimise just one of the MUXF7 away # and expect to save on its delay @@ -27,8 +28,8 @@ $__MUXF78 3 1 6 1 # CARRY4 + CARRY4_[ABCD]X # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 -# (NB: carry chain input/output must be last -# input/output and the entire bus has been +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been # moved there overriding the otherwise # alphabetical ordering) CARRY4 4 1 10 8 @@ -53,55 +54,54 @@ $__ABC9_ASYNC0 1000 1 2 1 $__ABC9_ASYNC1 1001 1 2 1 0 764 -# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 -# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 +# Flop boxes: +# * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 +# * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality -# NB: Inputs/Outputs must be ordered alphabetically -# (with exception for \$currQ) - -# Inputs: C CE D R \$currQ +# Inputs: C CE D R $abc9_currQ # Outputs: Q FDRE 1100 1 5 1 #0 109 -46 404 0 0 109 0 404 0 # Clamp -46ps Tsu -# Inputs: C CE D R \$currQ +# Inputs: C CE D R $abc9_currQ # Outputs: Q FDRE_1 1101 1 5 1 #0 109 0 -46 404 0 109 0 0 404 # Clamp -46ps Tsu -# Inputs: C CE CLR D \$currQ +# Inputs: C CE CLR D $abc9_currQ # Outputs: Q FDCE 1102 1 5 1 #0 109 764 -46 0 0 109 764 0 0 # Clamp -46ps Tsu -# Inputs: C CE CLR D \$currQ +# Inputs: C CE CLR D $abc9_currQ # Outputs: Q FDCE_1 1103 1 5 1 #0 109 764 -46 0 0 109 764 0 0 # Clamp -46ps Tsu -# Inputs: C CE D PRE \$currQ +# Inputs: C CE D PRE $abc9_currQ # Outputs: Q FDPE 1104 1 5 1 #0 109 -46 764 0 0 109 0 764 0 # Clamp -46ps Tsu -# Inputs: C CE D PRE \$currQ +# Inputs: C CE D PRE $abc9_currQ # Outputs: Q FDPE_1 1105 1 5 1 #0 109 -46 764 0 0 109 0 764 0 # Clamp -46ps Tsu -# Inputs: C CE D S \$currQ +# Inputs: C CE D S $abc9_currQ # Outputs: Q FDSE 1106 1 5 1 #0 109 -46 446 0 0 109 0 446 0 # Clamp -46ps Tsu -# Inputs: C CE D S \$currQ +# Inputs: C CE D S $abc9_currQ # Outputs: Q FDSE_1 1107 1 5 1 #0 109 -46 446 0 -- cgit v1.2.3 From b2046a2114add3d24c0affd9d885b7ee320dba27 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:29:29 -0800 Subject: Cleanup ecp5 boxes --- techlibs/ecp5/abc9_5g.box | 41 +++++++++++++++++------------------------ techlibs/ecp5/abc9_map.v | 19 +++++++++++-------- techlibs/ecp5/abc9_model.v | 2 +- techlibs/ecp5/abc9_unmap.v | 4 ++-- 4 files changed, 31 insertions(+), 35 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box index 2bc945a54..5c7f52ab1 100644 --- a/techlibs/ecp5/abc9_5g.box +++ b/techlibs/ecp5/abc9_5g.box @@ -1,43 +1,36 @@ -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) # Box 1 : CCU2C (2xCARRY + 2xLUT4) -# Outputs: S0, S1, COUT -# (NB: carry chain input/output must be last -# input/output and bus has been moved -# there overriding the otherwise +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been +# moved there overriding the otherwise # alphabetical ordering) # name ID w/b ins outs CCU2C 1 1 9 3 - -#A0 A1 B0 B1 C0 C1 D0 D1 CIN -379 - 379 - 275 - 141 - 257 -630 379 630 379 526 275 392 141 273 -516 516 516 516 412 412 278 278 43 +#A0 B0 C0 D0 A1 B1 C1 D1 CIN +379 379 275 141 - - - - 257 # S0 +630 630 526 392 379 379 275 141 273 # S1 +516 516 412 278 516 516 412 278 43 # COUT # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) -# Outputs: DO0, DO1, DO2, DO3 # name ID w/b ins outs $__ABC9_DPR16X4_COMB 2 0 8 4 - -#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 -0 0 0 0 141 379 275 379 -0 0 0 0 141 379 275 379 -0 0 0 0 141 379 275 379 -0 0 0 0 141 379 275 379 +#$D0 $D1 $D2 $D3 RAD0 RAD1 RAD2 RAD3 +0 0 0 0 141 379 275 379 # DO0 +0 0 0 0 141 379 275 379 # DO1 +0 0 0 0 141 379 275 379 # DO2 +0 0 0 0 141 379 275 379 # DO3 # Box 3 : PFUMX (MUX2) -# Outputs: Z # name ID w/b ins outs PFUMX 3 1 3 1 - #ALUT BLUT C0 -98 98 151 +98 98 151 # Z # Box 4 : L6MUX21 (MUX2) -# Outputs: Z # name ID w/b ins outs L6MUX21 4 1 3 1 - #D0 D1 SD -140 141 148 +140 141 148 # Z diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v index d8d70f9f6..113a35b91 100644 --- a/techlibs/ecp5/abc9_map.v +++ b/techlibs/ecp5/abc9_map.v @@ -1,24 +1,27 @@ // --------------------------------------- +// Attach a (combinatorial) black-box onto the output +// of this LUTRAM primitive to capture its +// asynchronous read behaviour module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, - input WCK, - input [3:0] RAD, + (* techmap_autopurge *) input [3:0] DI, + (* techmap_autopurge *) input [3:0] WAD, + (* techmap_autopurge *) input WRE, + (* techmap_autopurge *) input WCK, + (* techmap_autopurge *) input [3:0] RAD, output [3:0] DO ); parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter [63:0] INITVAL = 64'h0000000000000000; - wire [3:0] \$DO ; + wire [3:0] $DO; TRELLIS_DPR16X4 #( .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) ) _TECHMAP_REPLACE_ ( .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), - .RAD(RAD), .DO(\$DO ) + .RAD(RAD), .DO($DO) ); - \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); + $__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO)); endmodule diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v index 1dc8b5617..81e5cd070 100644 --- a/techlibs/ecp5/abc9_model.v +++ b/techlibs/ecp5/abc9_model.v @@ -1,5 +1,5 @@ // --------------------------------------- (* abc9_box_id=2 *) -module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); +module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO); endmodule diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v index 9ae143c46..cbdffdaf1 100644 --- a/techlibs/ecp5/abc9_unmap.v +++ b/techlibs/ecp5/abc9_unmap.v @@ -1,5 +1,5 @@ // --------------------------------------- -module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); - assign Y = A; +module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO); + assign DO = $DO; endmodule -- cgit v1.2.3 From 2358320f5168edd691882bba0f759d82308291d6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:29:37 -0800 Subject: Cleanup ice40 boxes --- techlibs/ice40/abc9_hx.box | 24 ++++++++++++++---------- techlibs/ice40/abc9_lp.box | 24 ++++++++++++++---------- techlibs/ice40/abc9_u.box | 25 +++++++++++++++---------- 3 files changed, 43 insertions(+), 30 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box index 3ea70bc91..31e743669 100644 --- a/techlibs/ice40/abc9_hx.box +++ b/techlibs/ice40/abc9_hx.box @@ -1,13 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) -# Inputs: A B I0 I3 CI -# Outputs: O CO -# (NB: carry chain input/output must be last -# input/output and have been moved there -# overriding the alphabetical ordering) -$__ICE40_CARRY_WRAPPER 1 1 5 2 -400 379 449 316 316 -259 231 - - 126 +# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve +# SB_LUT4+SB_CARRY) +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been +# moved there overriding the otherwise +# alphabetical ordering) +# name ID w/b ins outs +$__ICE40_CARRY_WRAPPER 1 1 5 2 +#A B I0 I3 CI +400 379 449 316 316 # O +259 231 - - 126 # CO diff --git a/techlibs/ice40/abc9_lp.box b/techlibs/ice40/abc9_lp.box index 473e92fe9..71986a67b 100644 --- a/techlibs/ice40/abc9_lp.box +++ b/techlibs/ice40/abc9_lp.box @@ -1,13 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) -# Inputs: A B I0 I3 CI -# Outputs: O CO -# (NB: carry chain input/output must be last -# input/output and have been moved there -# overriding the alphabetical ordering) -$__ICE40_CARRY_WRAPPER 1 1 5 2 -589 558 661 465 465 -675 609 - - 186 +# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve +# SB_LUT4+SB_CARRY) +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been +# moved there overriding the otherwise +# alphabetical ordering) +# name ID w/b ins outs +$__ICE40_CARRY_WRAPPER 1 1 5 2 +#A B I0 I3 CI +589 558 661 465 465 # O +675 609 - - 186 # CO diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box index f00e247b8..48a51463e 100644 --- a/techlibs/ice40/abc9_u.box +++ b/techlibs/ice40/abc9_u.box @@ -1,13 +1,18 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) +# NB: Box inputs/outputs must each be in the same order +# as their corresponding module definition +# (with exceptions detailed below) -# Inputs: A B I0 I3 CI -# Outputs: O CO -# (NB: carry chain input/output must be last -# input/output and have been moved there -# overriding the alphabetical ordering) -$__ICE40_CARRY_WRAPPER 1 1 5 2 -1231 1205 1285 874 874 -675 609 - - 278 +# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve +# SB_LUT4+SB_CARRY) +# Outputs: O, CO +# (Exception: carry chain input/output must be the +# last input and output and the entire bus has been +# moved there overriding the otherwise +# alphabetical ordering) +# name ID w/b ins outs +$__ICE40_CARRY_WRAPPER 1 1 5 2 +#A B I0 I3 CI +1231 1205 1285 874 874 # O +675 609 - - 278 # CO -- cgit v1.2.3 From 35c659be74396db7824bc98428137dc9a5ac1d16 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:29:44 -0800 Subject: Cleanup xilinx boxes --- techlibs/xilinx/abc9_map.v | 3 + techlibs/xilinx/abc9_xc7.box | 813 ++++++++++++++++++++++--------------------- 2 files changed, 425 insertions(+), 391 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index a3f9e311e..4ab8e1564 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -462,6 +462,9 @@ module FDSE_1 (output Q, input C, CE, D, S); `endif endmodule +// Attach a (combinatorial) black-box onto the output +// of thes LUTRAM primitives to capture their +// asynchronous read behaviour module RAM32X1D ( output DPO, SPO, (* techmap_autopurge *) input D, diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 67523124a..302487041 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -5,126 +5,138 @@ # as their corresponding module definition # (with exceptions detailed below) -# Average across F7[AB]MUX -# Inputs: I0 I1 S0 -# Outputs: O -MUXF7 1 1 3 1 -204 208 286 +# Box 1 : MUXF7 +# Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453 +# name ID w/b ins outs +MUXF7 1 1 3 1 +#I0 I1 S0 +204 208 286 # O -# Inputs: I0 I1 S0 -# Outputs: O -MUXF8 2 1 3 1 -104 94 273 +# Box 2 : MUXF8 +# Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464 +# name ID w/b ins outs +MUXF8 2 1 3 1 +#I0 I1 S0 +104 94 273 # O -# Box containing MUXF7.[AB] + MUXF8 -# Necessary to make these an atomic unit so that -# ABC cannot optimise just one of the MUXF7 away -# and expect to save on its delay -# Inputs: I0 I1 I2 I3 S0 S1 -# Outputs: O -$__MUXF78 3 1 6 1 -294 297 311 317 390 273 +# Box 3 : $__MUXF78 +# (private cell used to preserve 2xMUXF7 + 1xMUXF8 +# an atomic unit so that ABC cannot optimise just +# one of the MUXF7 away and expect to save on its +# delay, since MUXF8 is only reachable through an +# MUXF7) +# name ID w/b ins outs +$__MUXF78 3 1 6 1 +#I0 I1 I2 I3 S0 S1 +294 297 311 317 390 273 # O -# CARRY4 + CARRY4_[ABCD]X -# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI -# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 +# Box 4 : CARRY4 + CARRY4_[ABCD]X # (Exception: carry chain input/output must be the # last input and output and the entire bus has been # moved there overriding the otherwise # alphabetical ordering) -CARRY4 4 1 10 8 -482 - - - - 223 - - - 222 -598 407 - - - 400 205 - - 334 -584 556 537 - - 523 558 226 - 239 -642 615 596 438 - 582 618 330 227 313 -536 379 - - - 340 - - - 271 -494 465 445 - - 433 469 - - 157 -592 540 520 356 - 512 548 292 - 228 -580 526 507 398 385 508 528 378 380 114 +# Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46 +# name ID w/b ins outs +CARRY4 4 1 10 8 +#CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI +482 - - - - 223 - - - 222 # O0 +598 407 - - - 400 205 - - 334 # O1 +584 556 537 - - 523 558 226 - 239 # O2 +642 615 596 438 - 582 618 330 227 313 # O3 +536 379 - - - 340 - - - 271 # CO0 +494 465 445 - - 433 469 - - 157 # CO1 +592 540 520 356 - 512 548 292 - 228 # CO2 +580 526 507 398 385 508 528 378 380 114 # CO3 -# Box to emulate async behaviour of FDC* -# Inputs: A S -# Outputs: Y -$__ABC9_ASYNC0 1000 1 2 1 -0 764 +# Box 1000 : $__ABC9_ASYNC0 +# (private cell to emulate async behaviour of FDC*) +# name ID w/b ins outs +$__ABC9_ASYNC0 1000 1 2 1 +#A S +0 764 # Y -# Box to emulate async behaviour of FDP* -# Inputs: A S -# Outputs: Y +# Box 1001 : $__ABC9_ASYNC1 +# (private cell to emulate async behaviour of FDP*) +# name ID w/b ins outs $__ABC9_ASYNC1 1001 1 2 1 -0 764 +#A S +0 764 # Y # Flop boxes: # * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 # * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality -# Inputs: C CE D R $abc9_currQ -# Outputs: Q -FDRE 1100 1 5 1 +# Box 1100 : FDRE +# name ID w/b ins outs +FDRE 1100 1 5 1 +#C CE D R $abc9_currQ #0 109 -46 404 0 -0 109 0 404 0 # Clamp -46ps Tsu +0 109 0 404 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE D R $abc9_currQ -# Outputs: Q -FDRE_1 1101 1 5 1 -#0 109 0 -46 404 -0 109 0 0 404 # Clamp -46ps Tsu +# Box 1101 : FDRE_1 +# name ID w/b ins outs +FDRE_1 1101 1 5 1 +#C CE D R $abc9_currQ +#0 109 -46 404 0 +0 109 0 404 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE CLR D $abc9_currQ -# Outputs: Q -FDCE 1102 1 5 1 +# Box 1102 : FDCE +# name ID w/b ins outs +FDCE 1102 1 5 1 +#C CE CLR D $abc9_currQ #0 109 764 -46 0 -0 109 764 0 0 # Clamp -46ps Tsu +0 109 764 0 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE CLR D $abc9_currQ -# Outputs: Q -FDCE_1 1103 1 5 1 +# Box 1103 : FDCE_1 +# name ID w/b ins outs +FDCE_1 1103 1 5 1 +#C CE CLR D $abc9_currQ #0 109 764 -46 0 -0 109 764 0 0 # Clamp -46ps Tsu +0 109 764 0 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE D PRE $abc9_currQ -# Outputs: Q -FDPE 1104 1 5 1 +# Box 1104 : FDPE +# name ID w/b ins outs +FDPE 1104 1 5 1 +#C CE D PRE $abc9_currQ #0 109 -46 764 0 -0 109 0 764 0 # Clamp -46ps Tsu +0 109 -46 764 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE D PRE $abc9_currQ -# Outputs: Q -FDPE_1 1105 1 5 1 +# Box 1105 : FDPE_1 +# name ID w/b ins outs +FDPE_1 1105 1 5 1 +#C CE D PRE $abc9_currQ #0 109 -46 764 0 -0 109 0 764 0 # Clamp -46ps Tsu +0 109 -46 764 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE D S $abc9_currQ -# Outputs: Q -FDSE 1106 1 5 1 -#0 109 -46 446 0 -0 109 0 446 0 # Clamp -46ps Tsu +# Box 1106 : FDSE +# name ID w/b ins outs +FDSE 1106 1 5 1 +#C CE D R $abc9_currQ +#0 109 -46 404 0 +0 109 0 404 0 # Q (-46ps Tsu clamped to 0) -# Inputs: C CE D S $abc9_currQ -# Outputs: Q -FDSE_1 1107 1 5 1 -#0 109 -46 446 0 -0 109 0 446 0 # Clamp -46ps Tsu +# Box 1107 : FDSE_1 +# name ID w/b ins outs +FDSE_1 1107 1 5 1 +#C CE D R $abc9_currQ +#0 109 -46 404 0 +0 109 0 404 0 # Q (-46ps Tsu clamped to 0) +# Box 2000 : $__ABC9_LUT6 +# (private cell to emulate async behaviour of LUTRAMs) # SLICEM/A6LUT -# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} -# Necessary since RAMD* and SRL* have both combinatorial (i.e. -# same-cycle read operation) and sequential (write operation -# is only committed on the next clock edge). -# To model the combinatorial path, such cells have to be split -# into comb and seq parts, with this box modelling only the former. -# Inputs: A S0 S1 S2 S3 S4 S5 -# Outputs: Y -$__ABC9_LUT6 2000 0 7 1 -0 642 631 472 407 238 127 +# name ID w/b ins outs +$__ABC9_LUT6 2000 0 7 1 +#A S0 S1 S2 S3 S4 S5 +0 642 631 472 407 238 127 # Y -# SLICEM/A6LUT + F7BMUX -# Box to emulate comb/seq behaviour of RAMD128 -# Inputs: A S0 S1 S2 S3 S4 S5 S6 -# Outputs: Y +# Box 2001 : $__ABC9_LUT6 +# (private cell to emulate async behaviour of LUITRAMs) +# name ID w/b ins outs $__ABC9_LUT7 2001 0 8 1 -0 1047 1036 877 812 643 532 478 +#A S0 S1 S2 S3 S4 S5 S6 +0 1047 1036 877 812 643 532 478 # Y # Boxes used to represent the comb/seq behaviour of DSP48E1 # With abc9_map.v responsible for disconnecting inputs to @@ -136,308 +148,323 @@ $__ABC9_LUT7 2001 0 8 1 # the mux at zero time, the combinatorial delay through # these muxes thus represents the clock-to-q delay at # P/PCOUT. -$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 48 -# A AD B C D I M P Pq -2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 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3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 - - 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 - @@ -965,7 +994,9 @@ $__ABC9_DSP48E1_MULT_DPORT 3001 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -$__ABC9_DSP48E1 3002 0 263 154 +# Box 3002 : $__ABC9_DSP48E1 +# name ID w/b ins outs +$__ABC9_DSP48E1 3002 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 - -- cgit v1.2.3 From f7793a29564881245239e81326e0c7afeb15f6e9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:42:11 -0800 Subject: Missing character --- techlibs/ecp5/abc9_5g.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box index 5c7f52ab1..f153a665e 100644 --- a/techlibs/ecp5/abc9_5g.box +++ b/techlibs/ecp5/abc9_5g.box @@ -17,7 +17,7 @@ CCU2C 1 1 9 3 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # name ID w/b ins outs $__ABC9_DPR16X4_COMB 2 0 8 4 -#$D0 $D1 $D2 $D3 RAD0 RAD1 RAD2 RAD3 +#$DO0 $DO1 $DO2 $DO3 RAD0 RAD1 RAD2 RAD3 0 0 0 0 141 379 275 379 # DO0 0 0 0 0 141 379 275 379 # DO1 0 0 0 0 141 379 275 379 # DO2 -- cgit v1.2.3 From 44d9fb0e7cee7d8986ed037429e3c9fdd1b29ba1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:47:38 -0800 Subject: Re-arrange FD order --- techlibs/xilinx/abc9_map.v | 166 +++++++++++++++++++++---------------------- techlibs/xilinx/abc9_xc7.box | 44 ++++++------ techlibs/xilinx/cells_sim.v | 154 +++++++++++++++++++-------------------- 3 files changed, 182 insertions(+), 182 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 4ab8e1564..6d93e508f 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -163,6 +163,89 @@ module FDRE_1 (output Q, input C, CE, D, R); `endif endmodule +module FDSE (output Q, input C, CE, D, S); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; +`ifdef DFF_MODE + wire QQ, $Q; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDRE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_R_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) + ); + end + else begin + assign Q = QQ; + FDSE #( + .INIT(1'b0), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($Q), .C(C), .CE(CE), .S(S) + ); + end endgenerate + $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); + + // Special signals + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDSE #( + .INIT(INIT), + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_S_INVERTED(IS_S_INVERTED) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .S(S) + ); +`endif +endmodule +module FDSE_1 (output Q, input C, CE, D, S); + parameter [0:0] INIT = 1'b1; +`ifdef DFF_MODE + wire QQ, $Q; + generate if (INIT == 1'b1) begin + assign Q = ~QQ; + FDRE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) + ); + end + else begin + assign Q = QQ; + FDSE_1 #( + .INIT(1'b0) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q($Q), .C(C), .CE(CE), .S(S) + ); + end endgenerate + $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); + + // Special signals + wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; +`else + (* abc9_keep *) + FDSE_1 #( + .INIT(INIT) + ) _TECHMAP_REPLACE_ ( + .D(D), .Q(Q), .C(C), .CE(CE), .S(S) + ); +`endif +endmodule + module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -379,89 +462,6 @@ module FDPE_1 (output Q, input C, CE, D, PRE); `endif endmodule -module FDSE (output Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; -`ifdef DFF_MODE - wire QQ, $Q; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDRE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) - ); - end - else begin - assign Q = QQ; - FDSE #( - .INIT(1'b0), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_S_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .S(S) - ); - end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); - - // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -`else - (* abc9_keep *) - FDSE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_S_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .S(S) - ); -`endif -endmodule -module FDSE_1 (output Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b1; -`ifdef DFF_MODE - wire QQ, $Q; - generate if (INIT == 1'b1) begin - assign Q = ~QQ; - FDRE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(~D), .Q($Q), .C(C), .CE(CE), .R(S) - ); - end - else begin - assign Q = QQ; - FDSE_1 #( - .INIT(1'b0) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q($Q), .C(C), .CE(CE), .S(S) - ); - end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); - - // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -`else - (* abc9_keep *) - FDSE_1 #( - .INIT(INIT) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .S(S) - ); -`endif -endmodule - // Attach a (combinatorial) black-box onto the output // of thes LUTRAM primitives to capture their // asynchronous read behaviour diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 302487041..43c39544e 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -81,48 +81,48 @@ FDRE_1 1101 1 5 1 #0 109 -46 404 0 0 109 0 404 0 # Q (-46ps Tsu clamped to 0) -# Box 1102 : FDCE +# Box 1102 : FDSE # name ID w/b ins outs -FDCE 1102 1 5 1 +FDSE 1102 1 5 1 +#C CE D R $abc9_currQ +#0 109 -46 404 0 +0 109 0 404 0 # Q (-46ps Tsu clamped to 0) + +# Box 1103 : FDSE_1 +# name ID w/b ins outs +FDSE_1 1103 1 5 1 +#C CE D R $abc9_currQ +#0 109 -46 404 0 +0 109 0 404 0 # Q (-46ps Tsu clamped to 0) + +# Box 1104 : FDCE +# name ID w/b ins outs +FDCE 1104 1 5 1 #C CE CLR D $abc9_currQ #0 109 764 -46 0 0 109 764 0 0 # Q (-46ps Tsu clamped to 0) -# Box 1103 : FDCE_1 +# Box 1105 : FDCE_1 # name ID w/b ins outs -FDCE_1 1103 1 5 1 +FDCE_1 1105 1 5 1 #C CE CLR D $abc9_currQ #0 109 764 -46 0 0 109 764 0 0 # Q (-46ps Tsu clamped to 0) -# Box 1104 : FDPE +# Box 1106 : FDPE # name ID w/b ins outs -FDPE 1104 1 5 1 +FDPE 1106 1 5 1 #C CE D PRE $abc9_currQ #0 109 -46 764 0 0 109 -46 764 0 # Q (-46ps Tsu clamped to 0) -# Box 1105 : FDPE_1 +# Box 1107 : FDPE_1 # name ID w/b ins outs -FDPE_1 1105 1 5 1 +FDPE_1 1107 1 5 1 #C CE D PRE $abc9_currQ #0 109 -46 764 0 0 109 -46 764 0 # Q (-46ps Tsu clamped to 0) -# Box 1106 : FDSE -# name ID w/b ins outs -FDSE 1106 1 5 1 -#C CE D R $abc9_currQ -#0 109 -46 404 0 -0 109 0 404 0 # Q (-46ps Tsu clamped to 0) - -# Box 1107 : FDSE_1 -# name ID w/b ins outs -FDSE_1 1107 1 5 1 -#C CE D R $abc9_currQ -#0 109 -46 404 0 -0 109 0 404 0 # Q (-46ps Tsu clamped to 0) - # Box 2000 : $__ABC9_LUT6 # (private cell to emulate async behaviour of LUTRAMs) # SLICEM/A6LUT diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 982ccad72..c22bcdc27 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -362,6 +362,43 @@ module FDRE_1 ( always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; endmodule +(* abc9_box_id=1102, lib_whitebox, abc9_flop *) +module FDSE ( + (* abc9_arrival=303 *) + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + generate case (|IS_C_INVERTED) + 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate +endmodule + +(* abc9_box_id=1103, lib_whitebox, abc9_flop *) +module FDSE_1 ( + (* abc9_arrival=303 *) + output reg Q, + (* clkbuf_sink *) + input C, + input CE, D, S +); + parameter [0:0] INIT = 1'b1; + initial Q <= INIT; + always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; +endmodule + module FDRSE ( output reg Q, (* clkbuf_sink *) @@ -397,7 +434,7 @@ module FDRSE ( Q <= d; endmodule -(* abc9_box_id=1102, lib_whitebox, abc9_flop *) +(* abc9_box_id=1104, lib_whitebox, abc9_flop *) module FDCE ( (* abc9_arrival=303 *) output reg Q, @@ -423,7 +460,7 @@ module FDCE ( endcase endgenerate endmodule -(* abc9_box_id=1103, lib_whitebox, abc9_flop *) +(* abc9_box_id=1105, lib_whitebox, abc9_flop *) module FDCE_1 ( (* abc9_arrival=303 *) output reg Q, @@ -436,52 +473,7 @@ module FDCE_1 ( always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule -module FDCPE ( - output wire Q, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C, - input CE, - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR, - input D, - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire c = C ^ IS_C_INVERTED; - wire clr = CLR ^ IS_CLR_INVERTED; - wire pre = PRE ^ IS_PRE_INVERTED; - // Hacky model to avoid simulation-synthesis mismatches. - reg qc, qp, qs; - initial qc = INIT; - initial qp = INIT; - initial qs = 0; - always @(posedge c, posedge clr) begin - if (clr) - qc <= 0; - else if (CE) - qc <= D; - end - always @(posedge c, posedge pre) begin - if (pre) - qp <= 1; - else if (CE) - qp <= D; - end - always @* begin - if (clr) - qs <= 0; - else if (pre) - qs <= 1; - end - assign Q = qs ? qp : qc; -endmodule - -(* abc9_box_id=1104, lib_whitebox, abc9_flop *) +(* abc9_box_id=1106, lib_whitebox, abc9_flop *) module FDPE ( (* abc9_arrival=303 *) output reg Q, @@ -507,7 +499,7 @@ module FDPE ( endcase endgenerate endmodule -(* abc9_box_id=1105, lib_whitebox, abc9_flop *) +(* abc9_box_id=1107, lib_whitebox, abc9_flop *) module FDPE_1 ( (* abc9_arrival=303 *) output reg Q, @@ -520,41 +512,49 @@ module FDPE_1 ( always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc9_box_id=1106, lib_whitebox, abc9_flop *) -module FDSE ( - (* abc9_arrival=303 *) - output reg Q, +module FDCPE ( + output wire Q, (* clkbuf_sink *) (* invertible_pin = "IS_C_INVERTED" *) input C, input CE, - (* invertible_pin = "IS_D_INVERTED" *) + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, input D, - (* invertible_pin = "IS_S_INVERTED" *) - input S + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE ); - parameter [0:0] INIT = 1'b1; + parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - initial Q <= INIT; - generate case (|IS_C_INVERTED) - 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase endgenerate -endmodule - -(* abc9_box_id=1107, lib_whitebox, abc9_flop *) -module FDSE_1 ( - (* abc9_arrival=303 *) - output reg Q, - (* clkbuf_sink *) - input C, - input CE, D, S -); - parameter [0:0] INIT = 1'b1; - initial Q <= INIT; - always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + wire c = C ^ IS_C_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + // Hacky model to avoid simulation-synthesis mismatches. + reg qc, qp, qs; + initial qc = INIT; + initial qp = INIT; + initial qs = 0; + always @(posedge c, posedge clr) begin + if (clr) + qc <= 0; + else if (CE) + qc <= D; + end + always @(posedge c, posedge pre) begin + if (pre) + qp <= 1; + else if (CE) + qp <= D; + end + always @* begin + if (clr) + qs <= 0; + else if (pre) + qs <= 1; + end + assign Q = qs ? qp : qc; endmodule module LDCE ( -- cgit v1.2.3 From 550310e2647c7aac1e49b79d9ff912436103062f Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 12:30:00 +0000 Subject: Harmonize BRAM/LUTRAM descriptions across all of Yosys. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates --- techlibs/anlogic/Makefile.inc | 6 ++--- techlibs/anlogic/dram_init_16x4.vh | 16 ----------- techlibs/anlogic/drams.txt | 16 ----------- techlibs/anlogic/drams_map.v | 22 --------------- techlibs/anlogic/lutram_init_16x4.vh | 16 +++++++++++ techlibs/anlogic/lutrams.txt | 16 +++++++++++ techlibs/anlogic/lutrams_map.v | 22 +++++++++++++++ techlibs/anlogic/synth_anlogic.cc | 24 ++++++++++++----- techlibs/ecp5/Makefile.inc | 4 +-- techlibs/ecp5/bram.txt | 52 ------------------------------------ techlibs/ecp5/brams.txt | 52 ++++++++++++++++++++++++++++++++++++ techlibs/ecp5/lutram.txt | 17 ------------ techlibs/ecp5/lutrams.txt | 17 ++++++++++++ techlibs/ecp5/synth_ecp5.cc | 4 +-- techlibs/efinix/Makefile.inc | 2 +- techlibs/efinix/bram.txt | 32 ---------------------- techlibs/efinix/brams.txt | 32 ++++++++++++++++++++++ techlibs/efinix/synth_efinix.cc | 22 +++++++++++---- techlibs/gowin/Makefile.inc | 6 ++--- techlibs/gowin/bram.txt | 31 --------------------- techlibs/gowin/brams.txt | 31 +++++++++++++++++++++ techlibs/gowin/dram.txt | 17 ------------ techlibs/gowin/drams_map.v | 31 --------------------- techlibs/gowin/lutrams.txt | 17 ++++++++++++ techlibs/gowin/lutrams_map.v | 31 +++++++++++++++++++++ techlibs/gowin/synth_gowin.cc | 27 ++++++++++--------- techlibs/intel/synth_intel.cc | 10 +++---- 27 files changed, 300 insertions(+), 273 deletions(-) delete mode 100644 techlibs/anlogic/dram_init_16x4.vh delete mode 100644 techlibs/anlogic/drams.txt delete mode 100644 techlibs/anlogic/drams_map.v create mode 100644 techlibs/anlogic/lutram_init_16x4.vh create mode 100644 techlibs/anlogic/lutrams.txt create mode 100644 techlibs/anlogic/lutrams_map.v delete mode 100644 techlibs/ecp5/bram.txt create mode 100644 techlibs/ecp5/brams.txt delete mode 100644 techlibs/ecp5/lutram.txt create mode 100644 techlibs/ecp5/lutrams.txt delete mode 100644 techlibs/efinix/bram.txt create mode 100644 techlibs/efinix/brams.txt delete mode 100644 techlibs/gowin/bram.txt create mode 100644 techlibs/gowin/brams.txt delete mode 100644 techlibs/gowin/dram.txt delete mode 100644 techlibs/gowin/drams_map.v create mode 100644 techlibs/gowin/lutrams.txt create mode 100644 techlibs/gowin/lutrams_map.v (limited to 'techlibs') diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 9426b5ca5..2d8d65e2e 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh)) diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/dram_init_16x4.vh deleted file mode 100644 index 32fb1578c..000000000 --- a/techlibs/anlogic/dram_init_16x4.vh +++ /dev/null @@ -1,16 +0,0 @@ -.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0], - INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0], - INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0], - INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}), -.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1], - INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1], - INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1], - INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}), -.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2], - INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2], - INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2], - INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}), -.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3], - INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3], - INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3], - INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]}) diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt deleted file mode 100644 index 4e903c0a2..000000000 --- a/techlibs/anlogic/drams.txt +++ /dev/null @@ -1,16 +0,0 @@ -bram $__ANLOGIC_DRAM16X4 - init 1 - abits 4 - dbits 4 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 1 -endbram - -match $__ANLOGIC_DRAM16X4 - make_outreg -endmatch diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v deleted file mode 100644 index 084e2a25f..000000000 --- a/techlibs/anlogic/drams_map.v +++ /dev/null @@ -1,22 +0,0 @@ -module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [63:0]INIT = 64'bx; - input CLK1; - - input [3:0] A1ADDR; - output [3:0] A1DATA; - - input [3:0] B1ADDR; - input [3:0] B1DATA; - input B1EN; - - EG_LOGIC_DRAM16X4 #( - `include "dram_init_16x4.vh" - ) _TECHMAP_REPLACE_ ( - .di(B1DATA), - .waddr(B1ADDR), - .wclk(CLK1), - .we(B1EN), - .raddr(A1ADDR), - .do(A1DATA) - ); -endmodule diff --git a/techlibs/anlogic/lutram_init_16x4.vh b/techlibs/anlogic/lutram_init_16x4.vh new file mode 100644 index 000000000..32fb1578c --- /dev/null +++ b/techlibs/anlogic/lutram_init_16x4.vh @@ -0,0 +1,16 @@ +.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0], + INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0], + INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0], + INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}), +.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1], + INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1], + INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1], + INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}), +.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2], + INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2], + INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2], + INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}), +.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3], + INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3], + INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3], + INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]}) diff --git a/techlibs/anlogic/lutrams.txt b/techlibs/anlogic/lutrams.txt new file mode 100644 index 000000000..4e903c0a2 --- /dev/null +++ b/techlibs/anlogic/lutrams.txt @@ -0,0 +1,16 @@ +bram $__ANLOGIC_DRAM16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 1 +endbram + +match $__ANLOGIC_DRAM16X4 + make_outreg +endmatch diff --git a/techlibs/anlogic/lutrams_map.v b/techlibs/anlogic/lutrams_map.v new file mode 100644 index 000000000..5a464cafc --- /dev/null +++ b/techlibs/anlogic/lutrams_map.v @@ -0,0 +1,22 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 #( + `include "lutram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index b87fc8566..3a1992588 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -60,6 +60,9 @@ struct SynthAnlogicPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -nolutram\n"); + log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -67,7 +70,7 @@ struct SynthAnlogicPass : public ScriptPass } string top_opt, edif_file, json_file; - bool flatten, retime; + bool flatten, retime, nolutram; void clear_flags() YS_OVERRIDE { @@ -76,6 +79,7 @@ struct SynthAnlogicPass : public ScriptPass json_file = ""; flatten = true; retime = false; + nolutram = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -110,6 +114,10 @@ struct SynthAnlogicPass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-nolutram") { + nolutram = true; + continue; + } if (args[argidx] == "-retime") { retime = true; continue; @@ -150,18 +158,22 @@ struct SynthAnlogicPass : public ScriptPass run("synth -run coarse"); } - if (check_label("dram")) + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/anlogic/drams.txt"); - run("techmap -map +/anlogic/drams_map.v"); + run("memory_bram -rules +/anlogic/lutrams.txt"); + run("techmap -map +/anlogic/lutrams_map.v"); run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); @@ -187,7 +199,7 @@ struct SynthAnlogicPass : public ScriptPass run("techmap -map +/anlogic/cells_map.v"); run("clean"); } - + if (check_label("map_anlogic")) { run("anlogic_fixcarry"); diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 46463f510..2c33f23b9 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -8,9 +8,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt deleted file mode 100644 index 777ccaa2e..000000000 --- a/techlibs/ecp5/bram.txt +++ /dev/null @@ -1,52 +0,0 @@ -bram $__ECP5_PDPW16KD - init 1 - - abits 9 - dbits 36 - - groups 2 - ports 1 1 - wrmode 1 0 - enable 4 1 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -bram $__ECP5_DP16KD - init 1 - - abits 10 @a10d18 - dbits 18 @a10d18 - abits 11 @a11d9 - dbits 9 @a11d9 - abits 12 @a12d4 - dbits 4 @a12d4 - abits 13 @a13d2 - dbits 2 @a13d2 - abits 14 @a14d1 - dbits 1 @a14d1 - - groups 2 - ports 1 1 - wrmode 1 0 - enable 2 1 @a10d18 - enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 - transp 0 2 - clocks 2 3 - clkpol 2 3 -endbram - -match $__ECP5_PDPW16KD - min bits 2048 - min efficiency 5 - shuffle_enable A - make_transp - or_next_if_better -endmatch - -match $__ECP5_DP16KD - min bits 2048 - min efficiency 5 - shuffle_enable A -endmatch diff --git a/techlibs/ecp5/brams.txt b/techlibs/ecp5/brams.txt new file mode 100644 index 000000000..777ccaa2e --- /dev/null +++ b/techlibs/ecp5/brams.txt @@ -0,0 +1,52 @@ +bram $__ECP5_PDPW16KD + init 1 + + abits 9 + dbits 36 + + groups 2 + ports 1 1 + wrmode 1 0 + enable 4 1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__ECP5_DP16KD + init 1 + + abits 10 @a10d18 + dbits 18 @a10d18 + abits 11 @a11d9 + dbits 9 @a11d9 + abits 12 @a12d4 + dbits 4 @a12d4 + abits 13 @a13d2 + dbits 2 @a13d2 + abits 14 @a14d1 + dbits 1 @a14d1 + + groups 2 + ports 1 1 + wrmode 1 0 + enable 2 1 @a10d18 + enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 + transp 0 2 + clocks 2 3 + clkpol 2 3 +endbram + +match $__ECP5_PDPW16KD + min bits 2048 + min efficiency 5 + shuffle_enable A + make_transp + or_next_if_better +endmatch + +match $__ECP5_DP16KD + min bits 2048 + min efficiency 5 + shuffle_enable A +endmatch diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutram.txt deleted file mode 100644 index b94357429..000000000 --- a/techlibs/ecp5/lutram.txt +++ /dev/null @@ -1,17 +0,0 @@ -bram $__TRELLIS_DPR16X4 - init 1 - abits 4 - dbits 4 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -match $__TRELLIS_DPR16X4 - make_outreg - min wports 1 -endmatch diff --git a/techlibs/ecp5/lutrams.txt b/techlibs/ecp5/lutrams.txt new file mode 100644 index 000000000..b94357429 --- /dev/null +++ b/techlibs/ecp5/lutrams.txt @@ -0,0 +1,17 @@ +bram $__TRELLIS_DPR16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__TRELLIS_DPR16X4 + make_outreg + min wports 1 +endmatch diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index a0ea6d1f9..3985da57a 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -266,13 +266,13 @@ struct SynthEcp5Pass : public ScriptPass if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/ecp5/bram.txt"); + run("memory_bram -rules +/ecp5/brams.txt"); run("techmap -map +/ecp5/brams_map.v"); } if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/ecp5/lutram.txt"); + run("memory_bram -rules +/ecp5/lutrams.txt"); run("techmap -map +/ecp5/lutrams_map.v"); } diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 5013f7fc1..69665982c 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v)) -$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt)) diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/bram.txt deleted file mode 100644 index 0b3fd9308..000000000 --- a/techlibs/efinix/bram.txt +++ /dev/null @@ -1,32 +0,0 @@ -bram $__EFINIX_5K - init 1 - - abits 8 @a8d16 - dbits 16 @a8d16 - abits 9 @a9d8 - dbits 8 @a9d8 - abits 10 @a10d4 - dbits 4 @a10d4 - abits 11 @a11d2 - dbits 2 @a11d2 - abits 12 @a12d1 - dbits 1 @a12d1 - abits 8 @a8d20 - dbits 20 @a8d20 - abits 9 @a9d10 - dbits 10 @a9d10 - - groups 2 - ports 1 1 - wrmode 1 0 - enable 1 1 - transp 0 2 - clocks 2 3 - clkpol 2 3 -endbram - -match $__EFINIX_5K - min bits 256 - min efficiency 5 - shuffle_enable B -endmatch diff --git a/techlibs/efinix/brams.txt b/techlibs/efinix/brams.txt new file mode 100644 index 000000000..0b3fd9308 --- /dev/null +++ b/techlibs/efinix/brams.txt @@ -0,0 +1,32 @@ +bram $__EFINIX_5K + init 1 + + abits 8 @a8d16 + dbits 16 @a8d16 + abits 9 @a9d8 + dbits 8 @a9d8 + abits 10 @a10d4 + dbits 4 @a10d4 + abits 11 @a11d2 + dbits 2 @a11d2 + abits 12 @a12d1 + dbits 1 @a12d1 + abits 8 @a8d20 + dbits 20 @a8d20 + abits 9 @a9d10 + dbits 10 @a9d10 + + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 2 + clocks 2 3 + clkpol 2 3 +endbram + +match $__EFINIX_5K + min bits 256 + min efficiency 5 + shuffle_enable B +endmatch diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 26a8d4eda..3e5274385 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -60,6 +60,9 @@ struct SynthEfinixPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -nobram\n"); + log(" do not use EFX_RAM_5K cells in output netlist\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -67,7 +70,7 @@ struct SynthEfinixPass : public ScriptPass } string top_opt, edif_file, json_file; - bool flatten, retime; + bool flatten, retime, nobram; void clear_flags() YS_OVERRIDE { @@ -76,6 +79,7 @@ struct SynthEfinixPass : public ScriptPass json_file = ""; flatten = true; retime = false; + nobram = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -114,6 +118,10 @@ struct SynthEfinixPass : public ScriptPass retime = true; continue; } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } break; } extra_args(args, argidx, design); @@ -150,18 +158,22 @@ struct SynthEfinixPass : public ScriptPass run("synth -run coarse"); } - if (check_label("map_bram", "(skip if -nobram)")) + if (!nobram || check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/efinix/bram.txt"); + run("memory_bram -rules +/efinix/brams.txt"); run("techmap -map +/efinix/brams_map.v"); run("setundef -zero -params t:EFX_RAM_5K"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/efinix/arith_map.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); @@ -194,7 +206,7 @@ struct SynthEfinixPass : public ScriptPass run("efinix_fixcarry"); run("clean"); } - + if (check_label("check")) { run("hierarchy -check"); diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index d2853704b..fe5d9d6e6 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -7,9 +7,9 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v)) -$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt)) -$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v)) -$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt)) diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/bram.txt deleted file mode 100644 index e406f9c51..000000000 --- a/techlibs/gowin/bram.txt +++ /dev/null @@ -1,31 +0,0 @@ -bram $__GW1NR_SDP - init 1 - abits 9 @a9d36 - dbits 32 @a9d36 - abits 10 @a10d18 - dbits 16 @a10d18 - abits 11 @a11d9 - dbits 8 @a11d9 - abits 12 @a12d4 - dbits 4 @a12d4 - abits 13 @a13d2 - dbits 2 @a13d2 - abits 14 @a14d1 - dbits 1 @a14d1 - groups 2 - ports 1 1 - wrmode 1 0 - enable 4 1 @a9d36 - enable 2 1 @a10d18 - enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -match $__GW1NR_SDP - min bits 2048 - min efficiency 5 - shuffle_enable A - make_transp -endmatch diff --git a/techlibs/gowin/brams.txt b/techlibs/gowin/brams.txt new file mode 100644 index 000000000..e406f9c51 --- /dev/null +++ b/techlibs/gowin/brams.txt @@ -0,0 +1,31 @@ +bram $__GW1NR_SDP + init 1 + abits 9 @a9d36 + dbits 32 @a9d36 + abits 10 @a10d18 + dbits 16 @a10d18 + abits 11 @a11d9 + dbits 8 @a11d9 + abits 12 @a12d4 + dbits 4 @a12d4 + abits 13 @a13d2 + dbits 2 @a13d2 + abits 14 @a14d1 + dbits 1 @a14d1 + groups 2 + ports 1 1 + wrmode 1 0 + enable 4 1 @a9d36 + enable 2 1 @a10d18 + enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__GW1NR_SDP + min bits 2048 + min efficiency 5 + shuffle_enable A + make_transp +endmatch diff --git a/techlibs/gowin/dram.txt b/techlibs/gowin/dram.txt deleted file mode 100644 index 9db530251..000000000 --- a/techlibs/gowin/dram.txt +++ /dev/null @@ -1,17 +0,0 @@ -bram $__GW1NR_RAM16S4 - init 1 - abits 4 - dbits 4 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 1 - clocks 0 1 - clkpol 0 1 -endbram - -match $__GW1NR_RAM16S4 - make_outreg - min wports 1 -endmatch diff --git a/techlibs/gowin/drams_map.v b/techlibs/gowin/drams_map.v deleted file mode 100644 index a50ab365a..000000000 --- a/techlibs/gowin/drams_map.v +++ /dev/null @@ -1,31 +0,0 @@ -module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); - parameter CFG_ABITS = 4; - parameter CFG_DBITS = 4; - - parameter [63:0] INIT = 64'bx; - input CLK1; - - input [CFG_ABITS-1:0] A1ADDR; - output [CFG_DBITS-1:0] A1DATA; - input A1EN; - - input [CFG_ABITS-1:0] B1ADDR; - input [CFG_DBITS-1:0] B1DATA; - input B1EN; - - `include "brams_init3.vh" - - RAM16S4 - #(.INIT_0(INIT_0), - .INIT_1(INIT_1), - .INIT_2(INIT_2), - .INIT_3(INIT_3)) - _TECHMAP_REPLACE_ - (.AD(B1ADDR), - .DI(B1DATA), - .DO(A1DATA), - .CLK(CLK1), - .WRE(B1EN)); - - -endmodule diff --git a/techlibs/gowin/lutrams.txt b/techlibs/gowin/lutrams.txt new file mode 100644 index 000000000..9db530251 --- /dev/null +++ b/techlibs/gowin/lutrams.txt @@ -0,0 +1,17 @@ +bram $__GW1NR_RAM16S4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 1 + clocks 0 1 + clkpol 0 1 +endbram + +match $__GW1NR_RAM16S4 + make_outreg + min wports 1 +endmatch diff --git a/techlibs/gowin/lutrams_map.v b/techlibs/gowin/lutrams_map.v new file mode 100644 index 000000000..a50ab365a --- /dev/null +++ b/techlibs/gowin/lutrams_map.v @@ -0,0 +1,31 @@ +module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 4; + parameter CFG_DBITS = 4; + + parameter [63:0] INIT = 64'bx; + input CLK1; + + input [CFG_ABITS-1:0] A1ADDR; + output [CFG_DBITS-1:0] A1DATA; + input A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + input [CFG_DBITS-1:0] B1DATA; + input B1EN; + + `include "brams_init3.vh" + + RAM16S4 + #(.INIT_0(INIT_0), + .INIT_1(INIT_1), + .INIT_2(INIT_2), + .INIT_3(INIT_3)) + _TECHMAP_REPLACE_ + (.AD(B1ADDR), + .DI(B1DATA), + .DO(A1DATA), + .CLK(CLK1), + .WRE(B1EN)); + + +endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 6cf058f29..785f2802b 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -55,7 +55,7 @@ struct SynthGowinPass : public ScriptPass log(" -nobram\n"); log(" do not use BRAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); + log(" -nolutram\n"); log(" do not use distributed RAM cells in output netlist\n"); log("\n"); log(" -noflatten\n"); @@ -80,7 +80,7 @@ struct SynthGowinPass : public ScriptPass } string top_opt, vout_file; - bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads; + bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads; void clear_flags() YS_OVERRIDE { @@ -90,7 +90,7 @@ struct SynthGowinPass : public ScriptPass flatten = true; nobram = false; nodffe = false; - nodram = false; + nolutram = false; nowidelut = false; abc9 = false; noiopads = false; @@ -128,8 +128,8 @@ struct SynthGowinPass : public ScriptPass nobram = true; continue; } - if (args[argidx] == "-nodram") { - nodram = true; + if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") { + nolutram = true; continue; } if (args[argidx] == "-nodffe") { @@ -188,24 +188,28 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/gowin/bram.txt"); + run("memory_bram -rules +/gowin/brams.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); } - if (!nodram && check_label("dram", "(skip if -nodram)")) + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/gowin/dram.txt"); - run("techmap -map +/gowin/drams_map.v"); + run("memory_bram -rules +/gowin/lutrams.txt"); + run("techmap -map +/gowin/lutrams_map.v"); run("determine_init"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); run("techmap -map +/techmap.v"); if (retime || help_mode) @@ -248,7 +252,6 @@ struct SynthGowinPass : public ScriptPass run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); run("clean"); - } if (check_label("check")) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c8c690e45..5aa1a12d4 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -187,10 +187,10 @@ struct SynthIntelPass : public ScriptPass { } if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - if (family_opt == "cycloneiv" || - family_opt == "cycloneive" || - family_opt == "max10" || - help_mode) { + if (family_opt == "cycloneiv" || + family_opt == "cycloneive" || + family_opt == "max10" || + help_mode) { run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); } else { @@ -224,7 +224,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (iopads || help_mode) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)"); - run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); + run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); } -- cgit v1.2.3 From c40b1aae42c91f200194f7f5f2caa512787ed5a3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 08:34:43 -0800 Subject: Restore abc9 -keepff --- techlibs/xilinx/abc9_map.v | 88 ++--------------------------------------- techlibs/xilinx/synth_xilinx.cc | 4 +- 2 files changed, 6 insertions(+), 86 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 6d93e508f..1b58c34c0 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -21,7 +21,8 @@ // The following techmapping rules are intended to be run (with -max_iter 1) // before invoking the `abc9` pass in order to transform the design into // a format that it understands. -// + +`ifdef DFF_MODE // For example, (complex) flip-flops are expected to be described as an // combinatorial box (containing all control logic such as clock enable // or synchronous resets) followed by a basic D-Q flop. @@ -83,7 +84,6 @@ module FDRE (output Q, input C, CE, D, R); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; -`ifdef DFF_MODE wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -114,21 +114,9 @@ module FDRE (output Q, input C, CE, D, R); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -`else - (* abc9_keep *) - FDRE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_R_INVERTED(IS_R_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .R(R) - ); -`endif endmodule module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; -`ifdef DFF_MODE wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -153,14 +141,6 @@ module FDRE_1 (output Q, input C, CE, D, R); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -`else - (* abc9_keep *) - FDRE_1 #( - .INIT(INIT) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .R(R) - ); -`endif endmodule module FDSE (output Q, input C, CE, D, S); @@ -168,7 +148,6 @@ module FDSE (output Q, input C, CE, D, S); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; -`ifdef DFF_MODE wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -198,21 +177,9 @@ module FDSE (output Q, input C, CE, D, S); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -`else - (* abc9_keep *) - FDSE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_S_INVERTED(IS_S_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .S(S) - ); -`endif endmodule module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; -`ifdef DFF_MODE wire QQ, $Q; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -236,14 +203,6 @@ module FDSE_1 (output Q, input C, CE, D, S); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; -`else - (* abc9_keep *) - FDSE_1 #( - .INIT(INIT) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .S(S) - ); -`endif endmodule module FDCE (output Q, input C, CE, D, CLR); @@ -251,7 +210,6 @@ module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; -`ifdef DFF_MODE wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -295,21 +253,9 @@ module FDCE (output Q, input C, CE, D, CLR); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; -`else - (* abc9_keep *) - FDCE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_CLR_INVERTED(IS_CLR_INVERTED) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) - ); -`endif endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; -`ifdef DFF_MODE wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -345,14 +291,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; -`else - (* abc9_keep *) - FDCE_1 #( - .INIT(INIT) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR) - ); -`endif endmodule module FDPE (output Q, input C, CE, D, PRE); @@ -360,7 +298,6 @@ module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; -`ifdef DFF_MODE wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -402,21 +339,9 @@ module FDPE (output Q, input C, CE, D, PRE); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; -`else - (* abc9_keep *) - FDPE #( - .INIT(INIT), - .IS_C_INVERTED(IS_C_INVERTED), - .IS_D_INVERTED(IS_D_INVERTED), - .IS_PRE_INVERTED(IS_PRE_INVERTED), - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) - ); -`endif endmodule module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; -`ifdef DFF_MODE wire QQ, $Q, $abc9_currQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; @@ -452,15 +377,8 @@ module FDPE_1 (output Q, input C, CE, D, PRE); wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; -`else - (* abc9_keep *) - FDPE_1 #( - .INIT(INIT) - ) _TECHMAP_REPLACE_ ( - .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE) - ); -`endif endmodule +`endif // Attach a (combinatorial) black-box onto the output // of thes LUTRAM primitives to capture their diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f2a9ae982..10aa7be5f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass log(" flatten design before synthesis\n"); log("\n"); log(" -dff\n"); - log(" run 'abc9' with -dff option\n"); + log(" enable sequential synthesis with 'abc9'\n"); log("\n"); log(" -retime\n"); log(" run 'abc' with -dff option\n"); @@ -559,6 +559,8 @@ struct SynthXilinxPass : public ScriptPass abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; + if (!dff_mode) + abc9_opts += " -keepff"; run("abc9" + abc9_opts); run("techmap -map +/xilinx/abc9_unmap.v"); } -- cgit v1.2.3 From 0e95756e960f809aaa4596ba44330e7bd6fd0309 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 08:39:00 -0800 Subject: Clamp -46ps for FDPE* too --- techlibs/xilinx/abc9_xc7.box | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 43c39544e..1dff88509 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -114,14 +114,14 @@ FDCE_1 1105 1 5 1 FDPE 1106 1 5 1 #C CE D PRE $abc9_currQ #0 109 -46 764 0 -0 109 -46 764 0 # Q (-46ps Tsu clamped to 0) +0 109 0 764 0 # Q (-46ps Tsu clamped to 0) # Box 1107 : FDPE_1 # name ID w/b ins outs FDPE_1 1107 1 5 1 #C CE D PRE $abc9_currQ #0 109 -46 764 0 -0 109 -46 764 0 # Q (-46ps Tsu clamped to 0) +0 109 0 764 0 # Q (-46ps Tsu clamped to 0) # Box 2000 : $__ABC9_LUT6 # (private cell to emulate async behaviour of LUTRAMs) -- cgit v1.2.3 From 3deec51ddcb8690901f7d99958ad71bccd19084f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 08:43:16 -0800 Subject: Fix anlogic async flop mapping --- techlibs/anlogic/cells_map.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v index cfc743a4b..8ac087d9d 100644 --- a/techlibs/anlogic/cells_map.v +++ b/techlibs/anlogic/cells_map.v @@ -6,14 +6,14 @@ module \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REG module \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule module \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(1'b0)); endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule -module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(1'b1), .sr(R)); endmodule module \$_DLATCH_N_ (E, D, Q); wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; -- cgit v1.2.3 From db04161eca76d4db7a01641429d2da6a3a8d3239 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 17:30:26 -0800 Subject: Rework abc9's DSP48E1 model --- techlibs/xilinx/abc9_map.v | 335 +++------- techlibs/xilinx/abc9_model.v | 155 +---- techlibs/xilinx/abc9_unmap.v | 194 +----- techlibs/xilinx/abc9_xc7.box | 1399 +++++++++--------------------------------- techlibs/xilinx/cells_sim.v | 79 +++ 5 files changed, 506 insertions(+), 1656 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 7b9427b2f..e3e736e8f 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -282,244 +282,113 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - parameter _TECHMAP_CELLTYPE_ = ""; - localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); + wire [47:0] $P, $PCOUT; -`define DSP48E1_INST(__CELL__) """ -__CELL__ #( - .ACASCREG(ACASCREG), - .ADREG(ADREG), - .ALUMODEREG(ALUMODEREG), - .AREG(AREG), - .AUTORESET_PATDET(AUTORESET_PATDET), - .A_INPUT(A_INPUT), - .BCASCREG(BCASCREG), - .BREG(BREG), - .B_INPUT(B_INPUT), - .CARRYINREG(CARRYINREG), - .CARRYINSELREG(CARRYINSELREG), - .CREG(CREG), - .DREG(DREG), - .INMODEREG(INMODEREG), - .MREG(MREG), - .OPMODEREG(OPMODEREG), - .PREG(PREG), - .SEL_MASK(SEL_MASK), - .SEL_PATTERN(SEL_PATTERN), - .USE_DPORT(USE_DPORT), - .USE_MULT(USE_MULT), - .USE_PATTERN_DETECT(USE_PATTERN_DETECT), - .USE_SIMD(USE_SIMD), - .MASK(MASK), - .PATTERN(PATTERN), - .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), - .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), - .IS_CLK_INVERTED(IS_CLK_INVERTED), - .IS_INMODE_INVERTED(IS_INMODE_INVERTED), - .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) - ) _TECHMAP_REPLACE_ ( - .ACOUT(ACOUT), - .BCOUT(BCOUT), - .CARRYCASCOUT(CARRYCASCOUT), - .CARRYOUT(CARRYOUT), - .MULTSIGNOUT(MULTSIGNOUT), - .OVERFLOW(OVERFLOW), - .P(oP), - .PATTERNBDETECT(PATTERNBDETECT), - .PATTERNDETECT(PATTERNDETECT), - .PCOUT(oPCOUT), - .UNDERFLOW(UNDERFLOW), - .A(iA), - .ACIN(ACIN), - .ALUMODE(ALUMODE), - .B(iB), - .BCIN(BCIN), - .C(iC), - .CARRYCASCIN(CARRYCASCIN), - .CARRYIN(CARRYIN), - .CARRYINSEL(CARRYINSEL), - .CEA1(CEA1), - .CEA2(CEA2), - .CEAD(CEAD), - .CEALUMODE(CEALUMODE), - .CEB1(CEB1), - .CEB2(CEB2), - .CEC(CEC), - .CECARRYIN(CECARRYIN), - .CECTRL(CECTRL), - .CED(CED), - .CEINMODE(CEINMODE), - .CEM(CEM), - .CEP(CEP), - .CLK(CLK), - .D(iD), - .INMODE(INMODE), - .MULTSIGNIN(MULTSIGNIN), - .OPMODE(OPMODE), - .PCIN(PCIN), - .RSTA(RSTA), - .RSTALLCARRYIN(RSTALLCARRYIN), - .RSTALUMODE(RSTALUMODE), - .RSTB(RSTB), - .RSTC(RSTC), - .RSTCTRL(RSTCTRL), - .RSTD(RSTD), - .RSTINMODE(RSTINMODE), - .RSTM(RSTM), - .RSTP(RSTP) - ); -""" - - wire [29:0] iA; - wire [17:0] iB; - wire [47:0] iC; - wire [24:0] iD; - - wire pA, pB, pC, pD, pAD, pM, pP; - wire [47:0] oP, mP; - wire [47:0] oPCOUT, mPCOUT; + DSP48E1 #( + .ACASCREG(ACASCREG), + .ADREG(ADREG), + .ALUMODEREG(ALUMODEREG), + .AREG(AREG), + .AUTORESET_PATDET(AUTORESET_PATDET), + .A_INPUT(A_INPUT), + .BCASCREG(BCASCREG), + .BREG(BREG), + .B_INPUT(B_INPUT), + .CARRYINREG(CARRYINREG), + .CARRYINSELREG(CARRYINSELREG), + .CREG(CREG), + .DREG(DREG), + .INMODEREG(INMODEREG), + .MREG(MREG), + .OPMODEREG(OPMODEREG), + .PREG(PREG), + .SEL_MASK(SEL_MASK), + .SEL_PATTERN(SEL_PATTERN), + .USE_DPORT(USE_DPORT), + .USE_MULT(USE_MULT), + .USE_PATTERN_DETECT(USE_PATTERN_DETECT), + .USE_SIMD(USE_SIMD), + .MASK(MASK), + .PATTERN(PATTERN), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED), + .IS_INMODE_INVERTED(IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) + ) _TECHMAP_REPLACE_ ( + .ACOUT(ACOUT), + .BCOUT(BCOUT), + .CARRYCASCOUT(CARRYCASCOUT), + .CARRYOUT(CARRYOUT), + .MULTSIGNOUT(MULTSIGNOUT), + .OVERFLOW(OVERFLOW), + .P($P), + .PATTERNBDETECT(PATTERNBDETECT), + .PATTERNDETECT(PATTERNDETECT), + .PCOUT($PCOUT), + .UNDERFLOW(UNDERFLOW), + .A(A), + .ACIN(ACIN), + .ALUMODE(ALUMODE), + .B(B), + .BCIN(BCIN), + .C(C), + .CARRYCASCIN(CARRYCASCIN), + .CARRYIN(CARRYIN), + .CARRYINSEL(CARRYINSEL), + .CEA1(CEA1), + .CEA2(CEA2), + .CEAD(CEAD), + .CEALUMODE(CEALUMODE), + .CEB1(CEB1), + .CEB2(CEB2), + .CEC(CEC), + .CECARRYIN(CECARRYIN), + .CECTRL(CECTRL), + .CED(CED), + .CEINMODE(CEINMODE), + .CEM(CEM), + .CEP(CEP), + .CLK(CLK), + .D(D), + .INMODE(INMODE), + .MULTSIGNIN(MULTSIGNIN), + .OPMODE(OPMODE), + .PCIN(PCIN), + .RSTA(RSTA), + .RSTALLCARRYIN(RSTALLCARRYIN), + .RSTALUMODE(RSTALUMODE), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTCTRL(RSTCTRL), + .RSTD(RSTD), + .RSTINMODE(RSTINMODE), + .RSTM(RSTM), + .RSTP(RSTP) + ); generate - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken - if (AREG == 0 && MREG == 0 && PREG == 0) - assign iA = A, pA = 1'bx; - else - \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); - if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B, pB = 1'bx; - else - \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); - if (CREG == 0 && PREG == 0) - assign iC = C, pC = 1'bx; - else - \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); - if (DREG == 0) - assign iD = D; - else if (techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - assign pD = 1'bx; - if (ADREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - assign pAD = 1'bx; - if (PREG == 0) begin - if (MREG == 1) - \$__ABC9_REG rM (.Q(pM)); - else - assign pM = 1'bx; - assign pP = 1'bx; - end else begin - assign pM = 1'bx; - \$__ABC9_REG rP (.Q(pP)); - end + wire [29:0] $A; + wire [17:0] $B; + wire [47:0] $C; + wire [24:0] $D; - if (MREG == 0 && PREG == 0) - assign mP = oP, mPCOUT = oPCOUT; - else - assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC9_DSP48E1_MULT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) - ); - \$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) - ); + if (PREG != 0) + assign P = $P, PCOUT = $PCOUT; + else begin + if (AREG == 0) assign $A = A; + if (BREG == 0) assign $B = B; + if (CREG == 0) assign $C = C; + if (DREG == 0) assign $D = D; - `DSP48E1_INST(\$__ABC9_DSP48E1_MULT ) - end - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken - if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) - assign iA = A, pA = 1'bx; - else - \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); - if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B, pB = 1'bx; - else - \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); - if (CREG == 0 && PREG == 0) - assign iC = C, pC = 1'bx; - else - \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); - if (DREG == 0 && ADREG == 0) - assign iD = D, pD = 1'bx; - else - \$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); - if (PREG == 0) begin - if (MREG == 1) begin - assign pAD = 1'bx; - \$__ABC9_REG rM (.Q(pM)); - end else begin - if (ADREG == 1) - \$__ABC9_REG rAD (.Q(pAD)); - else - assign pAD = 1'bx; - assign pM = 1'bx; - end - assign pP = 1'bx; - end else begin - assign pAD = 1'bx, pM = 1'bx; - \$__ABC9_REG rP (.Q(pP)); + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") + $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") + $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") + $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + else + $error("Invalid DSP48E1 configuration"); end - - if (MREG == 0 && PREG == 0) - assign mP = oP, mPCOUT = oPCOUT; - else - assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) - ); - \$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) - ); - - `DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT ) - end - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken - if (AREG == 0 && PREG == 0) - assign iA = A, pA = 1'bx; - else - \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); - if (BREG == 0 && PREG == 0) - assign iB = B, pB = 1'bx; - else - \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); - if (CREG == 0 && PREG == 0) - assign iC = C, pC = 1'bx; - else - \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); - if (DREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - assign pD = 1'bx; - if (ADREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - assign pAD = 1'bx; - if (MREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); - assign pM = 1'bx; - if (PREG == 1) - \$__ABC9_REG rP (.Q(pP)); - else - assign pP = 1'bx; - - if (MREG == 0 && PREG == 0) - assign mP = oP, mPCOUT = oPCOUT; - else - assign mP = 1'bx, mPCOUT = 1'bx; - \$__ABC9_DSP48E1_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) - ); - \$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) - ); - - `DSP48E1_INST(\$__ABC9_DSP48E1 ) - end - else - $error("Invalid DSP48E1 configuration"); endgenerate - `undef DSP48E1_INST endmodule diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 8c8e1556c..18d59dcd6 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -44,147 +44,22 @@ endmodule module \$__ABC9_LUT7 (input A, input [6:0] S, output Y); endmodule - -// Modules used to model the comb/seq behaviour of DSP48E1 -// With abc9_map.v responsible for splicing the below modules -// between the combinatorial DSP48E1 box (e.g. disconnecting -// A when AREG, MREG or PREG is enabled and splicing in the -// "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below) -// this acts to first disables the combinatorial path (as there -// is no connectivity through REG), and secondly, since this is -// blackbox a new PI will be introduced with an arrival time of -// zero. -// Note: Since these "$__ABC9_DSP48E1_REG" modules are of a -// sequential nature, they are not passed as a box to ABC and -// (desirably) represented as PO/PIs. -// -// At the DSP output, we place a blackbox mux ("M" in the diagram -// below) to capture the fact that the critical-path could come -// from any one of its inputs. -// In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are -// combinatorial blackboxes that do get passed to ABC. -// The propagation delay through this box (specified in the box -// file) captures the arrival time of the register (i.e. -// propagation from AREG to P after clock edge), or zero delay -// for the combinatorial path from the DSP. -// -// Doing so should means that ABC is able to analyse the -// worst-case delay through to P, regardless of if it was -// through any combinatorial paths (e.g. B, below) or an -// internal register (A2REG). -// However, the true value of being as complete as this is -// questionable since if AREG=1 and BREG=0 (as below) -// then the worse-case path would very likely be through B -// and very unlikely to be through AREG.Q...? -// -// In graphical form: -// -// +-----+ -// +------>> REG >>----+ -// | +-----+ | -// | | -// | +---------+ | __ -// A >>-+X X-| | +--| \ -// | DSP48E1 |P | M |--->> P -// | AREG=1 |-------|__/ -// B >>------| | -// +---------+ -// -`define ABC9_DSP48E1_MUX(__NAME__) """ -module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -""" -(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX ) -(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX ) -(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX ) -(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX ) -(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX ) -(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX ) - +// Boxes used to represent the comb behaviour of various modes +// of DSP48E1 `define ABC9_DSP48E1(__NAME__) """ module __NAME__ ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP -); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + input [29:0] $A, + input [17:0] $B, + input [47:0] $C, + input [24:0] $D, + input [47:0] $P, + input [47:0] $PCIN, + input [47:0] $PCOUT, + output [47:0] P, + output [47:0] PCOUT); endmodule """ -(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT ) -(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT ) -(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 ) +(* abc9_box_id=3000 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT) +(* abc9_box_id=3001 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT) +(* abc9_box_id=3002 *) `ABC9_DSP48E1($__ABC9_DSP48E1) +`undef ABC9_DSP48E1 diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index ad6469702..64135e9a7 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -20,192 +20,24 @@ // ============================================================================ -module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); +module $__ABC9_LUT6(input A, input [5:0] S, output Y); assign Y = A; endmodule -module \$__ABC9_LUT7 (input A, input [6:0] S, output Y); +module $__ABC9_LUT7(input A, input [6:0] S, output Y); assign Y = A; endmodule -module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q); - parameter WIDTH = 1; - assign O = I; -endmodule -(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *) -module \$__ABC9_DSP48E1_MUX ( - input Aq, Bq, Cq, Dq, ADq, - input [47:0] I, - input Mq, - input [47:0] P, - input Pq, - output [47:0] O -); - assign O = I; -endmodule - (* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *) -module \$__ABC9_DSP48E1 ( - (* techmap_autopurge *) output [29:0] ACOUT, - (* techmap_autopurge *) output [17:0] BCOUT, - (* techmap_autopurge *) output reg CARRYCASCOUT, - (* techmap_autopurge *) output reg [3:0] CARRYOUT, - (* techmap_autopurge *) output reg MULTSIGNOUT, - (* techmap_autopurge *) output OVERFLOW, - (* techmap_autopurge *) output reg signed [47:0] P, - (* techmap_autopurge *) output PATTERNBDETECT, - (* techmap_autopurge *) output PATTERNDETECT, - (* techmap_autopurge *) output [47:0] PCOUT, - (* techmap_autopurge *) output UNDERFLOW, - (* techmap_autopurge *) input signed [29:0] A, - (* techmap_autopurge *) input [29:0] ACIN, - (* techmap_autopurge *) input [3:0] ALUMODE, - (* techmap_autopurge *) input signed [17:0] B, - (* techmap_autopurge *) input [17:0] BCIN, - (* techmap_autopurge *) input [47:0] C, - (* techmap_autopurge *) input CARRYCASCIN, - (* techmap_autopurge *) input CARRYIN, - (* techmap_autopurge *) input [2:0] CARRYINSEL, - (* techmap_autopurge *) input CEA1, - (* techmap_autopurge *) input CEA2, - (* techmap_autopurge *) input CEAD, - (* techmap_autopurge *) input CEALUMODE, - (* techmap_autopurge *) input CEB1, - (* techmap_autopurge *) input CEB2, - (* techmap_autopurge *) input CEC, - (* techmap_autopurge *) input CECARRYIN, - (* techmap_autopurge *) input CECTRL, - (* techmap_autopurge *) input CED, - (* techmap_autopurge *) input CEINMODE, - (* techmap_autopurge *) input CEM, - (* techmap_autopurge *) input CEP, - (* techmap_autopurge *) input CLK, - (* techmap_autopurge *) input [24:0] D, - (* techmap_autopurge *) input [4:0] INMODE, - (* techmap_autopurge *) input MULTSIGNIN, - (* techmap_autopurge *) input [6:0] OPMODE, - (* techmap_autopurge *) input [47:0] PCIN, - (* techmap_autopurge *) input RSTA, - (* techmap_autopurge *) input RSTALLCARRYIN, - (* techmap_autopurge *) input RSTALUMODE, - (* techmap_autopurge *) input RSTB, - (* techmap_autopurge *) input RSTC, - (* techmap_autopurge *) input RSTCTRL, - (* techmap_autopurge *) input RSTD, - (* techmap_autopurge *) input RSTINMODE, - (* techmap_autopurge *) input RSTM, - (* techmap_autopurge *) input RSTP +module $ABC9_DSP48E1( + input [29:0] $A, + input [17:0] $B, + input [47:0] $C, + input [24:0] $D, + input [47:0] $P, + input [47:0] $PCIN, + input [47:0] $PCOUT, + output [47:0] P, + output [47:0] PCOUT ); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - - DSP48E1 #( - .ACASCREG(ACASCREG), - .ADREG(ADREG), - .ALUMODEREG(ALUMODEREG), - .AREG(AREG), - .AUTORESET_PATDET(AUTORESET_PATDET), - .A_INPUT(A_INPUT), - .BCASCREG(BCASCREG), - .BREG(BREG), - .B_INPUT(B_INPUT), - .CARRYINREG(CARRYINREG), - .CARRYINSELREG(CARRYINSELREG), - .CREG(CREG), - .DREG(DREG), - .INMODEREG(INMODEREG), - .MREG(MREG), - .OPMODEREG(OPMODEREG), - .PREG(PREG), - .SEL_MASK(SEL_MASK), - .SEL_PATTERN(SEL_PATTERN), - .USE_DPORT(USE_DPORT), - .USE_MULT(USE_MULT), - .USE_PATTERN_DETECT(USE_PATTERN_DETECT), - .USE_SIMD(USE_SIMD), - .MASK(MASK), - .PATTERN(PATTERN), - .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), - .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), - .IS_CLK_INVERTED(IS_CLK_INVERTED), - .IS_INMODE_INVERTED(IS_INMODE_INVERTED), - .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) - ) _TECHMAP_REPLACE_ ( - .ACOUT(ACOUT), - .BCOUT(BCOUT), - .CARRYCASCOUT(CARRYCASCOUT), - .CARRYOUT(CARRYOUT), - .MULTSIGNOUT(MULTSIGNOUT), - .OVERFLOW(OVERFLOW), - .P(P), - .PATTERNBDETECT(PATTERNBDETECT), - .PATTERNDETECT(PATTERNDETECT), - .PCOUT(PCOUT), - .UNDERFLOW(UNDERFLOW), - .A(A), - .ACIN(ACIN), - .ALUMODE(ALUMODE), - .B(B), - .BCIN(BCIN), - .C(C), - .CARRYCASCIN(CARRYCASCIN), - .CARRYIN(CARRYIN), - .CARRYINSEL(CARRYINSEL), - .CEA1(CEA1), - .CEA2(CEA2), - .CEAD(CEAD), - .CEALUMODE(CEALUMODE), - .CEB1(CEB1), - .CEB2(CEB2), - .CEC(CEC), - .CECARRYIN(CECARRYIN), - .CECTRL(CECTRL), - .CED(CED), - .CEINMODE(CEINMODE), - .CEM(CEM), - .CEP(CEP), - .CLK(CLK), - .D(D), - .INMODE(INMODE), - .MULTSIGNIN(MULTSIGNIN), - .OPMODE(OPMODE), - .PCIN(PCIN), - .RSTA(RSTA), - .RSTALLCARRYIN(RSTALLCARRYIN), - .RSTALUMODE(RSTALUMODE), - .RSTB(RSTB), - .RSTC(RSTC), - .RSTCTRL(RSTCTRL), - .RSTD(RSTD), - .RSTINMODE(RSTINMODE), - .RSTM(RSTM), - .RSTP(RSTP) - ); + assign P = $P, PCOUT = $PCOUT; endmodule diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 774388d49..9fb1cc0ef 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -60,1106 +60,301 @@ $__ABC9_LUT6 2000 0 7 1 $__ABC9_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 -# Boxes used to represent the comb/seq behaviour of DSP48E1 -# With abc9_map.v responsible for disconnecting inputs to -# the combinatorial DSP48E1 model by a register (e.g. -# disconnecting A when AREG, MREG or PREG is enabled) -# this mux captures the existence of a replacement path -# between AREG/BREG/CREG/etc. and P/PCOUT. -# Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -# the mux at zero time, the combinatorial delay through -# these muxes thus represents the clock-to-q delay at -# P/PCOUT. -$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 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1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT46 +1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT47 diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 72e684af5..d705451fe 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2160,9 +2160,15 @@ module DSP48E1 ( output reg [3:0] CARRYOUT, output reg MULTSIGNOUT, output OVERFLOW, +`ifndef __ICARUS__ + (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) +`endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, +`ifndef __ICARUS__ + (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) +`endif output [47:0] PCOUT, output UNDERFLOW, input signed [29:0] A, @@ -2235,6 +2241,79 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + function \DSP48E1.P_arrival ; + input USE_MULT, USE_DPORT; + input AREG, ADREG, BREG, CREG, DREG, MREG, PREG; + begin + \DSP48E1.P_arrival = 0; + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.P_arrival = 329; + // Worse-case from CREG and MREG + else if (CREG != 0) \DSP48E1.P_arrival = 1687; + else if (MREG != 0) \DSP48E1.P_arrival = 1671; + // Worse-case from AREG and BREG + else if (AREG != 0) \DSP48E1.P_arrival = 2952; + else if (BREG != 0) \DSP48E1.P_arrival = 2813; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \DSP48E1.P_arrival = 329; + // Worse-case from CREG and MREG + else if (CREG != 0) \DSP48E1.P_arrival = 1687; + else if (MREG != 0) \DSP48E1.P_arrival = 1671; + // Worse-case from AREG, ADREG, BREG, DREG + else if (AREG != 0) \DSP48E1.P_arrival = 3935; + else if (DREG != 0) \DSP48E1.P_arrival = 3908; + else if (ADREG != 0) \DSP48E1.P_arrival = 2958; + else if (BREG != 0) \DSP48E1.P_arrival = 2813; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.P_arrival = 329; + // Worse-case from AREG, BREG, CREG + else if (CREG != 0) \DSP48E1.P_arrival = 1687; + else if (AREG != 0) \DSP48E1.P_arrival = 1632; + else if (BREG != 0) \DSP48E1.P_arrival = 1616; + end + //else + // $error("Invalid DSP48E1 configuration"); + end + endfunction + function \DSP48E1.PCOUT_arrival ; + input USE_MULT, USE_DPORT; + input AREG, ADREG, BREG, CREG, DREG, MREG, PREG; + begin + \DSP48E1.PCOUT_arrival = 0; + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; + // Worse-case from CREG and MREG + else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; + else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; + // Worse-case from AREG and BREG + else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098; + else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; + end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; + // Worse-case from CREG and MREG + else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; + else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; + // Worse-case from AREG, ADREG, BREG, DREG + else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083; + else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056; + else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; + else if (ADREG != 0) \DSP48E1.PCOUT_arrival = 2859; + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; + // Worse-case from AREG, BREG, CREG + else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; + else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780; + else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765; + end + //else + // $error("Invalid DSP48E1 configuration"); + end + endfunction + initial begin `ifdef __ICARUS__ if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); -- cgit v1.2.3 From 3d98a9627312c283715a691995466568a33ce7a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 17:33:10 -0800 Subject: ifdef __ICARUS__ -> ifndef YOSYS --- techlibs/xilinx/cells_sim.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 72e684af5..c27b0f02b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2236,7 +2236,7 @@ module DSP48E1 ( parameter [6:0] IS_OPMODE_INVERTED = 7'b0; initial begin -`ifdef __ICARUS__ +`ifndef YOSYS if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); @@ -2399,12 +2399,12 @@ module DSP48E1 ( case (OPMODEr[1:0]) 2'b00: X = 48'b0; 2'b01: begin X = $signed(Mrx); -`ifdef __ICARUS__ +`ifndef YOSYS if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif end 2'b10: begin X = P; -`ifdef __ICARUS__ +`ifndef YOSYS if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); `endif end @@ -2416,7 +2416,7 @@ module DSP48E1 ( case (OPMODEr[3:2]) 2'b00: Y = 48'b0; 2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling? -`ifdef __ICARUS__ +`ifndef YOSYS if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01"); `endif end @@ -2430,13 +2430,13 @@ module DSP48E1 ( 3'b000: Z = 48'b0; 3'b001: Z = PCIN; 3'b010: begin Z = P; -`ifdef __ICARUS__ +`ifndef YOSYS if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010"); `endif end 3'b011: Z = Cr; 3'b100: begin Z = P; -`ifdef __ICARUS__ +`ifndef YOSYS if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); `endif -- cgit v1.2.3 From d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 17:33:47 -0800 Subject: ifndef __ICARUS__ -> ifdef YOSYS --- techlibs/xilinx/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d705451fe..2947fe692 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2160,13 +2160,13 @@ module DSP48E1 ( output reg [3:0] CARRYOUT, output reg MULTSIGNOUT, output OVERFLOW, -`ifndef __ICARUS__ +`ifdef YOSYS (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) `endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, -`ifndef __ICARUS__ +`ifdef YOSYS (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) `endif output [47:0] PCOUT, -- cgit v1.2.3 From 8e507bd80785db9fa6723eada4214a5a06516cae Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 Jan 2020 12:36:54 -0800 Subject: abc9 -keepff -> -dff; refactor dff operations --- techlibs/xilinx/abc9_map.v | 110 ++++++++++++++++++++-------------------- techlibs/xilinx/synth_xilinx.cc | 6 +-- 2 files changed, 58 insertions(+), 58 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 1b58c34c0..1d37952f5 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -51,29 +51,29 @@ // || || // || /\/\/\/\ || // D -->>-----< > || -// R -->>-----< Comb. > || +----------+ -// CE -->>-----< logic >--->>-- $Q --|$__ABC_FF_|--+-->> Q -// $abc9_currQ +-->>-----< > || +----------+ | -// | || \/\/\/\/ || | -// | || || | -// | ++==================++ | -// | | -// +----------------------------------------------+ +// R -->>-----< Comb. > || +-----------+ +// CE -->>-----< logic >--->>-- $Q --|$__ABC9_FF_|--+-->> Q +// abc9_ff.Q +-->>-----< > || +-----------+ | +// | || \/\/\/\/ || | +// | || || | +// | ++==================++ | +// | | +// +-----------------------------------------------+ // // The purpose of the following FD* rules are to wrap the flop with: // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to // capture asynchronous behaviour -// (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock +// (c) a special _TECHMAP_REPLACE_.abc9_ff.clock wire to capture its clock // domain and polarity (used when partitioning the module so that `abc9' only // performs sequential synthesis (with reachability analysis) correctly on // one domain at a time) and also used to infer the optional delay target // from the (* abc9_clock_period = %d *) attribute attached to any wire // within -// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial +// (d) a special _TECHMAP_REPLACE_.abc9_ff.init wire to encode the flop's initial // state -// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback +// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour // // In order to perform sequential synthesis, `abc9' also requires that @@ -108,12 +108,12 @@ module FDRE (output Q, input C, CE, D, R); ); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; + wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule module FDRE_1 (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -135,12 +135,12 @@ module FDRE_1 (output Q, input C, CE, D, R); ); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; + wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule module FDSE (output Q, input C, CE, D, S); @@ -171,12 +171,12 @@ module FDSE (output Q, input C, CE, D, S); .D(D), .Q($Q), .C(C), .CE(CE), .S(S) ); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; + wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule module FDSE_1 (output Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; @@ -197,12 +197,12 @@ module FDSE_1 (output Q, input C, CE, D, S); .D(D), .Q($Q), .C(C), .CE(CE), .S(S) ); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ; + wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule module FDCE (output Q, input C, CE, D, CLR); @@ -210,7 +210,7 @@ module FDCE (output Q, input C, CE, D, CLR); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; - wire QQ, $Q, $abc9_currQ; + wire QQ, $Q, $QQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDPE #( @@ -227,7 +227,7 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC1 below ); // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -245,18 +245,18 @@ module FDCE (output Q, input C, CE, D, CLR); // $__ABC9_ASYNC0 below ); // Since this is an async flop, async behaviour is dealt with here - $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ)); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule module FDCE_1 (output Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; - wire QQ, $Q, $abc9_currQ; + wire QQ, $Q, $QQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDPE_1 #( @@ -269,7 +269,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR); // behaviour is captured by // $__ABC9_ASYNC1 below ); - $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ)); end else begin assign Q = QQ; @@ -283,14 +283,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR); // behaviour is captured by // $__ABC9_ASYNC0 below ); - $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ)); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule module FDPE (output Q, input C, CE, D, PRE); @@ -298,7 +298,7 @@ module FDPE (output Q, input C, CE, D, PRE); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; - wire QQ, $Q, $abc9_currQ; + wire QQ, $Q, $QQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDCE #( @@ -314,7 +314,7 @@ module FDPE (output Q, input C, CE, D, PRE); // behaviour is captured by // $__ABC9_ASYNC0 below ); - $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end else begin assign Q = QQ; @@ -331,18 +331,18 @@ module FDPE (output Q, input C, CE, D, PRE); // behaviour is captured by // $__ABC9_ASYNC1 below ); - $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ)); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule module FDPE_1 (output Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; - wire QQ, $Q, $abc9_currQ; + wire QQ, $Q, $QQ; generate if (INIT == 1'b1) begin assign Q = ~QQ; FDCE_1 #( @@ -355,7 +355,7 @@ module FDPE_1 (output Q, input C, CE, D, PRE); // behaviour is captured by // $__ABC9_ASYNC0 below ); - $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); + $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ)); end else begin assign Q = QQ; @@ -369,14 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE); // behaviour is captured by // $__ABC9_ASYNC1 below ); - $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ)); + $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ)); end endgenerate - $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ)); + $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ)); // Special signals - wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */}; - wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0; - wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ; + wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */}; + wire [0:0] abc9_ff.init = 1'b0; + wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule `endif diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 10aa7be5f..af9f21756 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass log(" flatten design before synthesis\n"); log("\n"); log(" -dff\n"); - log(" enable sequential synthesis with 'abc9'\n"); + log(" run 'abc9' with -dff option\n"); log("\n"); log(" -retime\n"); log(" run 'abc' with -dff option\n"); @@ -559,8 +559,8 @@ struct SynthXilinxPass : public ScriptPass abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; - if (!dff_mode) - abc9_opts += " -keepff"; + if (dff_mode) + abc9_opts += " -dff"; run("abc9" + abc9_opts); run("techmap -map +/xilinx/abc9_unmap.v"); } -- cgit v1.2.3 From ec1756c0941fac02614c25307b17bb41fe36f468 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 Jan 2020 12:39:52 -0800 Subject: Update comments --- techlibs/xilinx/abc9_map.v | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 1d37952f5..af58e217c 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -65,19 +65,14 @@ // the connectivity of its basic D-Q flop // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to // capture asynchronous behaviour -// (c) a special _TECHMAP_REPLACE_.abc9_ff.clock wire to capture its clock -// domain and polarity (used when partitioning the module so that `abc9' only -// performs sequential synthesis (with reachability analysis) correctly on -// one domain at a time) and also used to infer the optional delay target -// from the (* abc9_clock_period = %d *) attribute attached to any wire -// within -// (d) a special _TECHMAP_REPLACE_.abc9_ff.init wire to encode the flop's initial -// state +// (c) a special abc9_ff.clock wire to capture its clock domain and polarity +// (indicated to `abc9' so that it only performs sequential synthesis +// (with reachability analysis) correctly on one domain at a time) +// (d) a special abc9_ff.init wire to encode the flop's initial state +// NOTE: in order to perform sequential synthesis, `abc9' also requires +// that the initial value of all flops be zero // (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour -// -// In order to perform sequential synthesis, `abc9' also requires that -// the initial value of all flops be zero. module FDRE (output Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; -- cgit v1.2.3 From a051801b72c7d526a1c04cf2635ae8d7fe43a135 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 Jan 2020 12:53:26 -0800 Subject: synth_xilinx -dff to work with abc too --- techlibs/xilinx/synth_xilinx.cc | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e2a625f9b..51d2cbbd2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -108,10 +108,11 @@ struct SynthXilinxPass : public ScriptPass log(" flatten design before synthesis\n"); log("\n"); log(" -dff\n"); - log(" run 'abc9' with -dff option\n"); + log(" run 'abc'/'abc9' with -dff option\n"); log("\n"); log(" -retime\n"); - log(" run 'abc' with '-dff -D 1' options\n"); + log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n"); + log(" implies -dff.\n"); log("\n"); log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); @@ -195,6 +196,7 @@ struct SynthXilinxPass : public ScriptPass continue; } if (args[argidx] == "-retime") { + dff_mode = true; retime = true; continue; } @@ -542,7 +544,7 @@ struct SynthXilinxPass : public ScriptPass if (flatten_before_abc) run("flatten"); if (help_mode) - run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')"); + run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')"); else if (abc9) { if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " @@ -565,10 +567,16 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/xilinx/abc9_unmap.v"); } else { + std::string abc_opts; if (nowidelut) - run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : "")); + abc_opts += " -luts 2:2,3,6:5"; else - run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : "")); + abc_opts += " -luts 2:2,3,6:5,10,20"; + if (dff_mode) + abc_opts += " -dff"; + if (retime) + abc_opts += " -D 1"; + run("abc" + abc_opts); } run("clean"); @@ -581,7 +589,7 @@ struct SynthXilinxPass : public ScriptPass techmap_args += stringf("[-map %s]", ff_map_file.c_str()); else if (!abc9) techmap_args += stringf(" -map %s", ff_map_file.c_str()); - run("techmap " + techmap_args, "(option without '-abc9')"); + run("techmap " + techmap_args, "(only if '-abc9')"); run("xilinx_dffopt"); } -- cgit v1.2.3 From 50b68777d3a79e283ab22388e686f615e520524d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 Jan 2020 13:28:37 -0800 Subject: Drive $[ABCD] explicitly --- techlibs/xilinx/abc9_map.v | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index e3e736e8f..cbe2a8cef 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -373,22 +373,28 @@ module DSP48E1 ( wire [47:0] $C; wire [24:0] $D; - if (PREG != 0) - assign P = $P, PCOUT = $PCOUT; - else begin - if (AREG == 0) assign $A = A; - if (BREG == 0) assign $B = B; - if (CREG == 0) assign $C = C; - if (DREG == 0) assign $D = D; + if (PREG == 0) begin + if (MREG == 0 && AREG == 0) assign $A = A; + else assign $A = 30'bx; + if (MREG == 0 && BREG == 0) assign $B = B; + else assign $B = 18'bx; + if (MREG == 0 && DREG == 0) assign $D = D; + else assign $D = 25'bx; - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") - $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); - else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") - $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); - else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") - $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); - else - $error("Invalid DSP48E1 configuration"); + if (CREG == 0) assign $C = C; + else assign $C = 48'bx; end + else begin + assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx; + end + + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") + $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") + $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") + $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); + else + $error("Invalid DSP48E1 configuration"); endgenerate endmodule -- cgit v1.2.3 From bac1e65a9cecf9a53292f28554f857e4dd3ff4dd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 Jan 2020 17:21:54 -0800 Subject: Fix spacing --- techlibs/xilinx/abc9_xc7.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 1dff88509..a68da745f 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -58,7 +58,7 @@ $__ABC9_ASYNC0 1000 1 2 1 # Box 1001 : $__ABC9_ASYNC1 # (private cell to emulate async behaviour of FDP*) # name ID w/b ins outs -$__ABC9_ASYNC1 1001 1 2 1 +$__ABC9_ASYNC1 1001 1 2 1 #A S 0 764 # Y -- cgit v1.2.3 From c5d28f5d6b20a42e6f3a4b1a4e3be341a352e5e3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 4 Jan 2020 19:00:44 +0100 Subject: Valid to have attribute starting with SB_CARRY. --- techlibs/ice40/ice40_opt.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 371ceb623..9bee0444b 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -128,6 +128,8 @@ static void run_ice40_opts(Module *module) new_attr.insert(std::make_pair(a.first, a.second)); else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) continue; + else if (a.first.begins_with("\\SB_CARRY.\\")) + continue; else log_abort(); cell->attributes = std::move(new_attr); -- cgit v1.2.3 From 27c150bfcc222512a0f3816e72ee20285acad9b4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 11:39:08 -0800 Subject: Fix return value of arrival time functions, fix word --- techlibs/xilinx/cells_sim.v | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 7bfc36aa3..5e4529fd6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2161,13 +2161,13 @@ module DSP48E1 ( output reg MULTSIGNOUT, output OVERFLOW, `ifdef YOSYS - (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) + (* abc9_arrival = \DSP48E1.P_arrival () *) `endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, `ifdef YOSYS - (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) + (* abc9_arrival = \DSP48E1.PCOUT_arrival () *) `endif output [47:0] PCOUT, output UNDERFLOW, @@ -2241,26 +2241,24 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - function \DSP48E1.P_arrival ; - input USE_MULT, USE_DPORT; - input AREG, ADREG, BREG, CREG, DREG, MREG, PREG; + function integer \DSP48E1.P_arrival ; begin \DSP48E1.P_arrival = 0; if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.P_arrival = 329; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.P_arrival = 1687; else if (MREG != 0) \DSP48E1.P_arrival = 1671; - // Worse-case from AREG and BREG + // Worst-case from AREG and BREG else if (AREG != 0) \DSP48E1.P_arrival = 2952; else if (BREG != 0) \DSP48E1.P_arrival = 2813; end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin if (PREG != 0) \DSP48E1.P_arrival = 329; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.P_arrival = 1687; else if (MREG != 0) \DSP48E1.P_arrival = 1671; - // Worse-case from AREG, ADREG, BREG, DREG + // Worst-case from AREG, ADREG, BREG, DREG else if (AREG != 0) \DSP48E1.P_arrival = 3935; else if (DREG != 0) \DSP48E1.P_arrival = 3908; else if (ADREG != 0) \DSP48E1.P_arrival = 2958; @@ -2268,7 +2266,7 @@ module DSP48E1 ( end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.P_arrival = 329; - // Worse-case from AREG, BREG, CREG + // Worst-case from AREG, BREG, CREG else if (CREG != 0) \DSP48E1.P_arrival = 1687; else if (AREG != 0) \DSP48E1.P_arrival = 1632; else if (BREG != 0) \DSP48E1.P_arrival = 1616; @@ -2277,26 +2275,24 @@ module DSP48E1 ( // $error("Invalid DSP48E1 configuration"); end endfunction - function \DSP48E1.PCOUT_arrival ; - input USE_MULT, USE_DPORT; - input AREG, ADREG, BREG, CREG, DREG, MREG, PREG; + function integer \DSP48E1.PCOUT_arrival ; begin \DSP48E1.PCOUT_arrival = 0; if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; - // Worse-case from AREG and BREG + // Worst-case from AREG and BREG else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098; else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; - // Worse-case from CREG and MREG + // Worst-case from CREG and MREG else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819; - // Worse-case from AREG, ADREG, BREG, DREG + // Worst-case from AREG, ADREG, BREG, DREG else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083; else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056; else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960; @@ -2304,7 +2300,7 @@ module DSP48E1 ( end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin if (PREG != 0) \DSP48E1.PCOUT_arrival = 435; - // Worse-case from AREG, BREG, CREG + // Worst-case from AREG, BREG, CREG else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835; else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780; else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765; -- cgit v1.2.3 From 28bf712372c494043c7adc0de904925a9199c939 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 11:55:56 -0800 Subject: Wrap arrival functions inside `YOSYS too --- techlibs/xilinx/cells_sim.v | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 5e4529fd6..1cd4d2f30 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2241,6 +2241,7 @@ module DSP48E1 ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +`ifdef YOSYS function integer \DSP48E1.P_arrival ; begin \DSP48E1.P_arrival = 0; @@ -2309,6 +2310,7 @@ module DSP48E1 ( // $error("Invalid DSP48E1 configuration"); end endfunction +`endif initial begin `ifndef YOSYS -- cgit v1.2.3 From 53aa51dc923467bf7aed46e646640e7cee7b009d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 16:21:04 -0800 Subject: Re-enable &mfs for synth_{ecp5,xilinx} --- techlibs/ecp5/synth_ecp5.cc | 4 ++-- techlibs/xilinx/synth_xilinx.cc | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index d616391b2..6583f43fd 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -323,9 +323,9 @@ struct SynthEcp5Pass : public ScriptPass if (abc9) { run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); + run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200"); else - run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); + run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200"); run("techmap -map +/ecp5/abc9_unmap.v"); } else { if (nowidelut) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b0c4795ee..e1748562e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -541,7 +541,6 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); - abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else -- cgit v1.2.3 From 01866a79093092bc2f8a8b20376f6cb552f76f00 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 16:45:29 -0800 Subject: Fix DSP48E1 sim --- techlibs/xilinx/cells_sim.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 1cd4d2f30..70ab1f293 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2388,8 +2388,8 @@ module DSP48E1 ( if (CEB2) Br2 <= Br1; end end else if (BREG == 1) begin - //initial Br1 = 25'b0; - initial Br2 = 25'b0; + //initial Br1 = 18'b0; + initial Br2 = 18'b0; always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; @@ -2436,7 +2436,7 @@ module DSP48E1 ( endgenerate // A/D input selection and pre-adder - wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; + wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); -- cgit v1.2.3 From 6e3e81402520b854eb5879964adc3434fefd3f51 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 7 Jan 2020 15:59:18 -0800 Subject: Fix abc9_xc7.box comments --- techlibs/xilinx/abc9_xc7.box | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 64170546c..13f4f0e61 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -132,15 +132,16 @@ $__ABC9_LUT6 2000 0 7 1 0 642 631 472 407 238 127 # Y # Box 2001 : $__ABC9_LUT6 -# (private cell to emulate async behaviour of LUITRAMs) +# (private cell to emulate async behaviour of LUTRAMs) # name ID w/b ins outs -$__ABC9_LUT7 2001 0 8 1 +$__ABC9_LUT7 2001 0 8 1 #A S0 S1 S2 S3 S4 S5 S6 0 1047 1036 877 812 643 532 478 # Y -# Boxes used to represent the comb behaviour of various modes -# of DSP48E1 -$__ABC9_DSP48E1_MULT 3000 0 265 96 +# Box 3000 : $__ABC9_DSP48E1_MULT +# (private cell to emulate comb behaviour of a DSP48E1 mode) +# name ID w/b ins outs +$__ABC9_DSP48E1_MULT 3000 0 265 96 #A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P0 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P1 @@ -239,7 +240,10 @@ $__ABC9_DSP48E1_MULT 3000 0 265 96 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT46 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT47 -$__ABC9_DSP48E1_MULT_DPORT 3001 0 265 96 +# Box 3001 : $__ABC9_DSP48E1_MULT_DPORT +# (private cell to emulate comb behaviour of a DSP48E1 mode) +# name ID w/b ins outs +$__ABC9_DSP48E1_MULT_DPORT 3001 0 265 96 #A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P0 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P1 @@ -338,7 +342,10 @@ $__ABC9_DSP48E1_MULT_DPORT 3001 0 265 96 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT46 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT47 -$__ABC9_DSP48E1 3002 0 265 96 +# Box 3002 : $__ABC9_DSP48E1 +# (private cell to emulate comb behaviour of a DSP48E1 mode) +# name ID w/b ins outs +$__ABC9_DSP48E1 3002 0 265 96 #A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P0 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P1 -- cgit v1.2.3 From 823a08e0d8272e8d48584eecc2d8dc57bdb98a6e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 7 Jan 2020 15:59:18 -0800 Subject: Fix abc9_xc7.box comments --- techlibs/xilinx/abc9_xc7.box | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box index 64170546c..13f4f0e61 100644 --- a/techlibs/xilinx/abc9_xc7.box +++ b/techlibs/xilinx/abc9_xc7.box @@ -132,15 +132,16 @@ $__ABC9_LUT6 2000 0 7 1 0 642 631 472 407 238 127 # Y # Box 2001 : $__ABC9_LUT6 -# (private cell to emulate async behaviour of LUITRAMs) +# (private cell to emulate async behaviour of LUTRAMs) # name ID w/b ins outs -$__ABC9_LUT7 2001 0 8 1 +$__ABC9_LUT7 2001 0 8 1 #A S0 S1 S2 S3 S4 S5 S6 0 1047 1036 877 812 643 532 478 # Y -# Boxes used to represent the comb behaviour of various modes -# of DSP48E1 -$__ABC9_DSP48E1_MULT 3000 0 265 96 +# Box 3000 : $__ABC9_DSP48E1_MULT +# (private cell to emulate comb behaviour of a DSP48E1 mode) +# name ID w/b ins outs +$__ABC9_DSP48E1_MULT 3000 0 265 96 #A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P0 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P1 @@ -239,7 +240,10 @@ $__ABC9_DSP48E1_MULT 3000 0 265 96 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT46 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT47 -$__ABC9_DSP48E1_MULT_DPORT 3001 0 265 96 +# Box 3001 : $__ABC9_DSP48E1_MULT_DPORT +# (private cell to emulate comb behaviour of a DSP48E1 mode) +# name ID w/b ins outs +$__ABC9_DSP48E1_MULT_DPORT 3001 0 265 96 #A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P0 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P1 @@ -338,7 +342,10 @@ $__ABC9_DSP48E1_MULT_DPORT 3001 0 265 96 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT46 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # PCOUT47 -$__ABC9_DSP48E1 3002 0 265 96 +# Box 3002 : $__ABC9_DSP48E1 +# (private cell to emulate comb behaviour of a DSP48E1 mode) +# name ID w/b ins outs +$__ABC9_DSP48E1 3002 0 265 96 #A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P0 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # P1 -- cgit v1.2.3 From 992b507537d6c0e5804859100e05a7a78adb21eb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 10 Jan 2020 12:34:21 +0100 Subject: Use CARRY4 for abc1 as well, preventing issues with Vivado --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 51d2cbbd2..7ff09a437 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -515,7 +515,7 @@ struct SynthXilinxPass : public ScriptPass techmap_args += " -map +/xilinx/arith_map.v"; if (vpr) techmap_args += " -D _EXPLICIT_CARRY"; - else if (abc9) + else techmap_args += " -D _CLB_CARRY"; } run("techmap " + techmap_args); -- cgit v1.2.3 From 7d94e18100a6fe61805e94e754b199826571e7ef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 10 Jan 2020 15:07:46 -0800 Subject: synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro --- techlibs/xilinx/synth_xilinx.cc | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 51d2cbbd2..5867f5d1c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -26,13 +26,16 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate - // to one LUT6 (instead of a LUT5 + LUT2) - struct SynthXilinxPass : public ScriptPass { SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { } + void on_register() YS_OVERRIDE + { + RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) + } + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -555,7 +558,11 @@ struct SynthXilinxPass : public ScriptPass run("techmap " + techmap_args); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; - abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); + if (active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; -- cgit v1.2.3 From 35e49fde4dfa67030a3e80d0bdf700c97258ed45 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 11 Jan 2020 18:57:25 -0800 Subject: Another conflict --- techlibs/xilinx/synth_xilinx.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5867f5d1c..d916093dc 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -563,7 +563,6 @@ struct SynthXilinxPass : public ScriptPass abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); else abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); - abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else -- cgit v1.2.3 From c0b55deb0bb189d1b6343b5d209f7fc4ac251596 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 12 Jan 2020 11:26:05 -0800 Subject: synth_ice40: -abc2 to always use `abc` even if `-abc9` --- techlibs/ice40/synth_ice40.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 463c2063a..121bcff1f 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -102,8 +102,8 @@ struct SynthIce40Pass : public ScriptPass log("\n"); } - string top_opt, blif_file, edif_file, json_file, abc, device_opt; - bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr; + string top_opt, blif_file, edif_file, json_file, device_opt; + bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9; int min_ce_use; void clear_flags() YS_OVERRIDE @@ -122,7 +122,7 @@ struct SynthIce40Pass : public ScriptPass noabc = false; abc2 = false; vpr = false; - abc = "abc"; + abc9 = false; device_opt = "hx"; } @@ -207,7 +207,7 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc = "abc9"; + abc9 = true; continue; } if (args[argidx] == "-device" && argidx+1 < args.size()) { @@ -223,7 +223,7 @@ struct SynthIce40Pass : public ScriptPass if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str()); - if (abc == "abc9" && retime) + if (abc9 && retime) log_cmd_error("-retime option not currently compatible with -abc9!\n"); log_header(design, "Executing SYNTH_ICE40 pass.\n"); @@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); } if (retime || help_mode) - run(abc + " -dff -D 1", "(only if -retime)"); + run("abc -dff -D 1", "(only if -retime)"); run("ice40_opt"); } @@ -340,7 +340,7 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_luts")) { if (abc2 || help_mode) { - run(abc, " (only if -abc2)"); + run("abc", " (only if -abc2)"); run("ice40_opt", "(only if -abc2)"); } run("techmap -map +/ice40/latches_map.v"); @@ -349,7 +349,7 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); } if (!noabc) { - if (abc == "abc9") { + if (abc9) { run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") @@ -358,10 +358,10 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str())); } else - run(abc + " -dress -lut 4", "(skip if -noabc)"); + run("abc -dress -lut 4", "(skip if -noabc)"); } run("ice40_wrapcarry -unwrap"); run("techmap -D NO_LUT -map +/ice40/cells_map.v"); -- cgit v1.2.3 From 36d1a2c60ff8179d9cfbdb1ae0ca5dd5d883991a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Jan 2020 11:34:40 -0800 Subject: synth_xilinx: fix default W value for non-xc7 --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d916093dc..b86484e71 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -562,7 +562,7 @@ struct SynthXilinxPass : public ScriptPass if (active_design->scratchpad.count(k)) abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str()); if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else -- cgit v1.2.3 From d21262ee0439df761b054d46752c2c3d52e6f373 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Jan 2020 12:22:21 -0800 Subject: Adding (* techmap_autopurge *) to FD* in abc9_map.v --- techlibs/xilinx/abc9_map.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 0652064cb..7dc027176 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -74,7 +74,7 @@ // (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour -module FDRE (output Q, input C, CE, D, R); +module FDRE (output Q, (* techmap_autopurge *) input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -110,7 +110,7 @@ module FDRE (output Q, input C, CE, D, R); wire [0:0] abc9_ff.init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule -module FDRE_1 (output Q, input C, CE, D, R); +module FDRE_1 (output Q, (* techmap_autopurge *) input C, CE, D, R); parameter [0:0] INIT = 1'b0; wire QQ, $Q; generate if (INIT == 1'b1) begin @@ -138,7 +138,7 @@ module FDRE_1 (output Q, input C, CE, D, R); wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule -module FDSE (output Q, input C, CE, D, S); +module FDSE (output Q, (* techmap_autopurge *) input C, CE, D, S); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -173,7 +173,7 @@ module FDSE (output Q, input C, CE, D, S); wire [0:0] abc9_ff.init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule -module FDSE_1 (output Q, input C, CE, D, S); +module FDSE_1 (output Q, (* techmap_autopurge *) input C, CE, D, S); parameter [0:0] INIT = 1'b1; wire QQ, $Q; generate if (INIT == 1'b1) begin @@ -200,7 +200,7 @@ module FDSE_1 (output Q, input C, CE, D, S); wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ; endmodule -module FDCE (output Q, input C, CE, D, CLR); +module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -249,7 +249,7 @@ module FDCE (output Q, input C, CE, D, CLR); wire [0:0] abc9_ff.init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule -module FDCE_1 (output Q, input C, CE, D, CLR); +module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; wire QQ, $Q, $QQ; generate if (INIT == 1'b1) begin @@ -288,7 +288,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR); wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule -module FDPE (output Q, input C, CE, D, PRE); +module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -335,7 +335,7 @@ module FDPE (output Q, input C, CE, D, PRE); wire [0:0] abc9_ff.init = 1'b0; wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ; endmodule -module FDPE_1 (output Q, input C, CE, D, PRE); +module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; wire QQ, $Q, $QQ; generate if (INIT == 1'b1) begin -- cgit v1.2.3 From 1e6d56dca11c7a632b74ba51361f879dc706110a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 17 Jan 2020 11:14:19 -0800 Subject: +/xilinx/arith_map.v fix $lcu rule --- techlibs/xilinx/arith_map.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 5c848d4e6..c345a3da3 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -53,9 +53,9 @@ module _80_xilinx_lcu (P, G, CI, CO); ( .CYINIT(CI), .CI (1'd0), - .DI (G [(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]), + .DI (G [(WIDTH - 1):i*4]), + .S (S [(WIDTH - 1):i*4]), + .CO (CO[(WIDTH - 1):i*4]), ); // Another one end else begin @@ -63,9 +63,9 @@ module _80_xilinx_lcu (P, G, CI, CO); ( .CYINIT(1'd0), .CI (C [i*4 - 1]), - .DI (G [(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]), + .DI (G [(WIDTH - 1):i*4]), + .S (S [(WIDTH - 1):i*4]), + .CO (CO[(WIDTH - 1):i*4]), ); end -- cgit v1.2.3 From 5c589244df2ec4fc5fde0bcdc69dee727f4b8e79 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 17 Jan 2020 12:02:46 -0800 Subject: Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 --- techlibs/xilinx/arith_map.v | 199 +++++++++++++++++----------------------- techlibs/xilinx/synth_xilinx.cc | 2 - 2 files changed, 82 insertions(+), 119 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index c345a3da3..40c378d16 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -33,7 +33,21 @@ module _80_xilinx_lcu (P, G, CI, CO); genvar i; -`ifdef _CLB_CARRY +`ifdef _EXPLICIT_CARRY + + wire [WIDTH-1:0] C = {CO, CI}; + wire [WIDTH-1:0] S = P & ~G; + + generate for (i = 0; i < WIDTH; i = i + 1) begin:slice + MUXCY muxcy ( + .CI(C[i]), + .DI(G[i]), + .S(S[i]), + .O(CO[i]) + ); + end endgenerate + +`else localparam CARRY4_COUNT = (WIDTH + 3) / 4; localparam MAX_WIDTH = CARRY4_COUNT * 4; @@ -97,34 +111,6 @@ module _80_xilinx_lcu (P, G, CI, CO); end end endgenerate - -`elsif _EXPLICIT_CARRY - - wire [WIDTH-1:0] C = {CO, CI}; - wire [WIDTH-1:0] S = P & ~G; - - generate for (i = 0; i < WIDTH; i = i + 1) begin:slice - MUXCY muxcy ( - .CI(C[i]), - .DI(G[i]), - .S(S[i]), - .O(CO[i]) - ); - end endgenerate - -`else - - wire [WIDTH-1:0] C = {CO, CI}; - wire [WIDTH-1:0] S = P & ~G; - - generate for (i = 0; i < WIDTH; i = i + 1) begin:slice - MUXCY muxcy ( - .CI(C[i]), - .DI(G[i]), - .S(S[i]), - .O(CO[i]) - ); - end endgenerate `endif endmodule @@ -161,79 +147,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); genvar i; -`ifdef _CLB_CARRY - - localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; - localparam MAX_WIDTH = CARRY4_COUNT * 4; - localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH; - - wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; - wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB}; - - wire [MAX_WIDTH-1:0] C = CO; - - genvar i; - generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice - - // Partially occupied CARRY4 - if ((i+1)*4 > Y_WIDTH) begin - - // First one - if (i == 0) begin - CARRY4 carry4_1st_part - ( - .CYINIT(CI), - .CI (1'd0), - .DI (DI[(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .O (Y [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]) - ); - // Another one - end else begin - CARRY4 carry4_part - ( - .CYINIT(1'd0), - .CI (C [i*4 - 1]), - .DI (DI[(Y_WIDTH - 1):i*4]), - .S (S [(Y_WIDTH - 1):i*4]), - .O (Y [(Y_WIDTH - 1):i*4]), - .CO (CO[(Y_WIDTH - 1):i*4]) - ); - end - - // Fully occupied CARRY4 - end else begin - - // First one - if (i == 0) begin - CARRY4 carry4_1st_full - ( - .CYINIT(CI), - .CI (1'd0), - .DI (DI[((i+1)*4 - 1):i*4]), - .S (S [((i+1)*4 - 1):i*4]), - .O (Y [((i+1)*4 - 1):i*4]), - .CO (CO[((i+1)*4 - 1):i*4]) - ); - // Another one - end else begin - CARRY4 carry4_full - ( - .CYINIT(1'd0), - .CI (C [i*4 - 1]), - .DI (DI[((i+1)*4 - 1):i*4]), - .S (S [((i+1)*4 - 1):i*4]), - .O (Y [((i+1)*4 - 1):i*4]), - .CO (CO[((i+1)*4 - 1):i*4]) - ); - end - - end - - end endgenerate - -`elsif _EXPLICIT_CARRY +`ifdef _EXPLICIT_CARRY wire [Y_WIDTH-1:0] S = AA ^ BB; wire [Y_WIDTH-1:0] DI = AA & BB; @@ -333,23 +247,74 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); `else - wire [Y_WIDTH-1:0] S = AA ^ BB; - wire [Y_WIDTH-1:0] DI = AA & BB; + localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; + localparam MAX_WIDTH = CARRY4_COUNT * 4; + localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH; - wire [Y_WIDTH-1:0] C = {CO, CI}; + wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; + wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB}; + + wire [MAX_WIDTH-1:0] C = CO; + + genvar i; + generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice + + // Partially occupied CARRY4 + if ((i+1)*4 > Y_WIDTH) begin + + // First one + if (i == 0) begin + CARRY4 carry4_1st_part + ( + .CYINIT(CI), + .CI (1'd0), + .DI (DI[(Y_WIDTH - 1):i*4]), + .S (S [(Y_WIDTH - 1):i*4]), + .O (Y [(Y_WIDTH - 1):i*4]), + .CO (CO[(Y_WIDTH - 1):i*4]) + ); + // Another one + end else begin + CARRY4 carry4_part + ( + .CYINIT(1'd0), + .CI (C [i*4 - 1]), + .DI (DI[(Y_WIDTH - 1):i*4]), + .S (S [(Y_WIDTH - 1):i*4]), + .O (Y [(Y_WIDTH - 1):i*4]), + .CO (CO[(Y_WIDTH - 1):i*4]) + ); + end + + // Fully occupied CARRY4 + end else begin + + // First one + if (i == 0) begin + CARRY4 carry4_1st_full + ( + .CYINIT(CI), + .CI (1'd0), + .DI (DI[((i+1)*4 - 1):i*4]), + .S (S [((i+1)*4 - 1):i*4]), + .O (Y [((i+1)*4 - 1):i*4]), + .CO (CO[((i+1)*4 - 1):i*4]) + ); + // Another one + end else begin + CARRY4 carry4_full + ( + .CYINIT(1'd0), + .CI (C [i*4 - 1]), + .DI (DI[((i+1)*4 - 1):i*4]), + .S (S [((i+1)*4 - 1):i*4]), + .O (Y [((i+1)*4 - 1):i*4]), + .CO (CO[((i+1)*4 - 1):i*4]) + ); + end + + end - generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - MUXCY muxcy ( - .CI(C[i]), - .DI(DI[i]), - .S(S[i]), - .O(CO[i]) - ); - XORCY xorcy ( - .CI(C[i]), - .LI(S[i]), - .O(Y[i]) - ); end endgenerate `endif diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3dc05cd10..5c3b5179d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -518,8 +518,6 @@ struct SynthXilinxPass : public ScriptPass techmap_args += " -map +/xilinx/arith_map.v"; if (vpr) techmap_args += " -D _EXPLICIT_CARRY"; - else - techmap_args += " -D _CLB_CARRY"; } run("techmap " + techmap_args); run("opt -fast"); -- cgit v1.2.3 From 78ffd5d193a72a024204cae09ff4ab05238ed311 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 17 Jan 2020 15:41:55 -0800 Subject: synth_ice40: call wreduce before mul2dsp --- techlibs/ice40/synth_ice40.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 121bcff1f..d92e40726 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,8 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("memory_dff"); + run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first + run("wreduce t:$mul"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); -- cgit v1.2.3 From da134701cd86e3958490b97fd6d840ce24586080 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Jan 2020 14:22:03 -0800 Subject: Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 --- techlibs/xilinx/abc9_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 204fa883f..15d12c89f 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -42,7 +42,7 @@ endmodule // Box to emulate async behaviour of FDP* (* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); - assign Y = S ? 1'b0 : A; + assign Y = S ? 1'b1 : A; endmodule // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} -- cgit v1.2.3 From 7858cf20a9fa3cec6993bcda39f84974d2793429 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 Jan 2020 14:22:03 -0800 Subject: Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 --- techlibs/xilinx/abc9_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 204fa883f..15d12c89f 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -42,7 +42,7 @@ endmodule // Box to emulate async behaviour of FDP* (* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); - assign Y = S ? 1'b0 : A; + assign Y = S ? 1'b1 : A; endmodule // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} -- cgit v1.2.3 From b1787615514f84c83c27d08011427e90c9bd0f4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Jan 2020 11:59:48 -0800 Subject: ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 --- techlibs/ice40/abc9_model.v | 4 +++- techlibs/ice40/abc9_u.box | 3 +-- techlibs/ice40/arith_map.v | 5 +++-- techlibs/ice40/ice40_opt.cc | 4 +++- 4 files changed, 10 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v index 26cf6cc22..a5e5f4372 100644 --- a/techlibs/ice40/abc9_model.v +++ b/techlibs/ice40/abc9_model.v @@ -9,6 +9,8 @@ module \$__ICE40_CARRY_WRAPPER ( input I0, I3 ); parameter LUT = 0; + parameter I3_IS_CI = 0; + wire I3_OR_CI = I3_IS_CI ? CI : I3; SB_CARRY carry ( .I0(A), .I1(B), @@ -21,7 +23,7 @@ module \$__ICE40_CARRY_WRAPPER ( .I0(I0), .I1(A), .I2(B), - .I3(I3), + .I3(I3_OR_CI), .O(O) ); endmodule diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box index 48a51463e..3d4b93834 100644 --- a/techlibs/ice40/abc9_u.box +++ b/techlibs/ice40/abc9_u.box @@ -6,13 +6,12 @@ # Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve # SB_LUT4+SB_CARRY) -# Outputs: O, CO # (Exception: carry chain input/output must be the # last input and output and the entire bus has been # moved there overriding the otherwise # alphabetical ordering) # name ID w/b ins outs $__ICE40_CARRY_WRAPPER 1 1 5 2 -#A B I0 I3 CI +#A B I0 I3 CI 1231 1205 1285 874 874 # O 675 609 - - 278 # CO diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index 00a07247b..ed4140e44 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -49,13 +49,14 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); // A[1]: 1100 1100 1100 1100 // A[2]: 1111 0000 1111 0000 // A[3]: 1111 1111 0000 0000 - .LUT(16'b 0110_1001_1001_0110) + .LUT(16'b 0110_1001_1001_0110), + .I3_IS_CI(1'b1) ) carry ( .A(AA[i]), .B(BB[i]), .CI(C[i]), .I0(1'b0), - .I3(C[i]), + .I3(1'bx), .CO(CO[i]), .O(Y[i]) ); diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 9bee0444b..df10a2842 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,7 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") }); + auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); + cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); @@ -148,6 +149,7 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\CO"); cell->unsetPort("\\O"); cell->setParam("\\WIDTH", 4); + cell->unsetParam("\\I3_IS_CI"); } continue; } -- cgit v1.2.3 From 81e6b040a4e9a6c8def9c4d68851e2a1f9328ed8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Jan 2020 12:16:05 -0800 Subject: ice40: add SB_SPRAM256KA arrival time --- techlibs/ice40/cells_sim.v | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 7d1b37fd6..50eab5dde 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1126,6 +1126,7 @@ module SB_SPRAM256KA ( input [15:0] DATAIN, input [3:0] MASKWREN, input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF, + `ABC9_ARRIVAL_U(1821) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207 output reg [15:0] DATAOUT ); `ifndef BLACKBOX -- cgit v1.2.3 From cef607c8b77803aa1236d250da4ca6841f78a4ea Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Mon, 27 Jan 2020 18:27:47 +0100 Subject: Add log_experimental() and experimental() API and "yosys -x" Signed-off-by: Claire Wolf --- techlibs/intel/synth_intel.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 2ebb8bf50..3689df70e 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { - SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {} + SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); } void help() YS_OVERRIDE { -- cgit v1.2.3 From ce6a690d27f3ce3b637f1d9be42b1efd744500d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Jan 2020 12:29:07 -0800 Subject: xilinx/ice40/ecp5: undo permuting LUT masks in lut_map Now done in read_aiger --- techlibs/ecp5/cells_map.v | 132 +++++++++++++++++++-------------------------- techlibs/ice40/cells_map.v | 13 +++-- techlibs/xilinx/lut_map.v | 99 +++++++++++++--------------------- 3 files changed, 98 insertions(+), 146 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 10e89a3e0..c031703a9 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -73,102 +73,80 @@ module \$lut (A, Y); input [WIDTH-1:0] A; output Y; - // Need to swap input ordering, and fix init accordingly, - // to match ABC's expectation of LUT inputs in non-decreasing - // delay order - localparam P_WIDTH = WIDTH < 4 ? 4 : WIDTH; - function [P_WIDTH-1:0] permute_index; - input [P_WIDTH-1:0] i; - integer j; - begin - permute_index = 0; - for (j = 0; j < P_WIDTH; j = j + 1) - permute_index[P_WIDTH-1 - j] = i[j]; - end - endfunction - - function [2**P_WIDTH-1:0] permute_init; - integer i; - begin - permute_init = 0; - for (i = 0; i < 2**P_WIDTH; i = i + 1) - permute_init[i] = LUT[permute_index(i)]; - end - endfunction - - parameter [2**P_WIDTH-1:0] P_LUT = permute_init(); - generate if (WIDTH == 1) begin - LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y), + localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0])); end else if (WIDTH == 2) begin - LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y), - .A(1'b0), .B(1'b0), .C(A[1]), .D(A[0])); + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1])); end else if (WIDTH == 3) begin - LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y), - .A(1'b0), .B(A[2]), .C(A[1]), .D(A[0])); + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2])); end else if (WIDTH == 4) begin - LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y), - .A(A[3]), .B(A[2]), .C(A[1]), .D(A[0])); + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); `ifndef NO_PFUMUX end else if (WIDTH == 5) begin wire f0, f1; - LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0), - .A(A[4]), .B(A[3]), .C(A[2]), .D(A[1])); - LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1), - .A(A[4]), .B(A[3]), .C(A[2]), .D(A[1])); - PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[0]), .Z(Y)); + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y)); end else if (WIDTH == 6) begin wire f0, f1, f2, f3, g0, g1; - LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0), - .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2])); - LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1), - .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2])); - - LUT4 #(.INIT(P_LUT[47:32])) lut2 (.Z(f2), - .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2])); - LUT4 #(.INIT(P_LUT[63:48])) lut3 (.Z(f3), - .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2])); - - PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[1]), .Z(g0)); - PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[1]), .Z(g1)); - L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[0]), .Z(Y)); + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y)); end else if (WIDTH == 7) begin wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1; - LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - - LUT4 #(.INIT(P_LUT[47:32])) lut2 (.Z(f2), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - LUT4 #(.INIT(P_LUT[63:48])) lut3 (.Z(f3), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - - LUT4 #(.INIT(P_LUT[79:64])) lut4 (.Z(f4), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - LUT4 #(.INIT(P_LUT[95:80])) lut5 (.Z(f5), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - - LUT4 #(.INIT(P_LUT[111: 96])) lut6 (.Z(f6), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - LUT4 #(.INIT(P_LUT[127:112])) lut7 (.Z(f7), - .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3])); - - PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[2]), .Z(g0)); - PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[2]), .Z(g1)); - PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[2]), .Z(g2)); - PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[2]), .Z(g3)); - L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[1]), .Z(h0)); - L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[1]), .Z(h1)); - L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[0]), .Z(Y)); + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2)); + PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3)); + L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0)); + L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1)); + L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y)); `endif end else begin wire _TECHMAP_FAIL_ = 1; diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 759549e30..d5362eb83 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -42,19 +42,18 @@ module \$lut (A, Y); .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0])); end else if (WIDTH == 2) begin - localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}}; + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0])); + .I0(1'b0), .I1(1'b0), .I2(A[0]), .I3(A[1])); end else if (WIDTH == 3) begin - localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}}; + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0])); + .I0(1'b0), .I1(A[0]), .I2(A[1]), .I3(A[2])); end else if (WIDTH == 4) begin - localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]}; - SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0])); + SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v index 62d501632..718ec42f1 100644 --- a/techlibs/xilinx/lut_map.v +++ b/techlibs/xilinx/lut_map.v @@ -29,90 +29,65 @@ module \$lut (A, Y); input [WIDTH-1:0] A; output Y; - // Need to swap input ordering, and fix init accordingly, - // to match ABC's expectation of LUT inputs in non-decreasing - // delay order - function [WIDTH-1:0] permute_index; - input [WIDTH-1:0] i; - integer j; - begin - permute_index = 0; - for (j = 0; j < WIDTH; j = j + 1) - permute_index[WIDTH-1 - j] = i[j]; - end - endfunction - - function [2**WIDTH-1:0] permute_init; - input [2**WIDTH-1:0] orig; - integer i; - begin - permute_init = 0; - for (i = 0; i < 2**WIDTH; i = i + 1) - permute_init[i] = orig[permute_index(i)]; - end - endfunction - - parameter [2**WIDTH-1:0] P_LUT = permute_init(LUT); - generate if (WIDTH == 1) begin - if (P_LUT == 2'b01) begin + if (LUT == 2'b01) begin INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0])); end else begin - LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), + LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0])); end end else if (WIDTH == 2) begin - LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[1]), .I1(A[0])); + LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1])); end else if (WIDTH == 3) begin - LUT3 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[2]), .I1(A[1]), .I2(A[0])); + LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2])); end else if (WIDTH == 4) begin - LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[3]), .I1(A[2]), .I2(A[1]), - .I3(A[0])); + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3])); end else if (WIDTH == 5) begin - LUT5 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[4]), .I1(A[3]), .I2(A[2]), - .I3(A[1]), .I4(A[0])); + LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4])); end else if (WIDTH == 6) begin - LUT6 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y), - .I0(A[5]), .I1(A[4]), .I2(A[3]), - .I3(A[2]), .I4(A[1]), .I5(A[0])); + LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); end else if (WIDTH == 7) begin wire T0, T1; - LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0), - .I0(A[6]), .I1(A[5]), .I2(A[4]), - .I3(A[3]), .I4(A[2]), .I5(A[1])); - LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1), - .I0(A[6]), .I1(A[5]), .I2(A[4]), - .I3(A[3]), .I4(A[2]), .I5(A[1])); - MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[0])); + LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6])); end else if (WIDTH == 8) begin wire T0, T1, T2, T3, T4, T5; - LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0), - .I0(A[7]), .I1(A[6]), .I2(A[5]), - .I3(A[4]), .I4(A[3]), .I5(A[2])); - LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1), - .I0(A[7]), .I1(A[6]), .I2(A[5]), - .I3(A[4]), .I4(A[3]), .I5(A[2])); - LUT6 #(.INIT(P_LUT[191:128])) fpga_lut_2 (.O(T2), - .I0(A[7]), .I1(A[6]), .I2(A[5]), - .I3(A[4]), .I4(A[3]), .I5(A[2])); - LUT6 #(.INIT(P_LUT[255:192])) fpga_lut_3 (.O(T3), - .I0(A[7]), .I1(A[6]), .I2(A[5]), - .I3(A[4]), .I4(A[3]), .I5(A[2])); - MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[1])); - MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[1])); - MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[0])); + LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3), + .I0(A[0]), .I1(A[1]), .I2(A[2]), + .I3(A[3]), .I4(A[4]), .I5(A[5])); + MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6])); + MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6])); + MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7])); end else begin wire _TECHMAP_FAIL_ = 1; end -- cgit v1.2.3 From cfb0366a18b0f3cab254636fdf534a3de76af8d5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 Jan 2020 13:56:16 -0800 Subject: Import tests from #1628 --- techlibs/ice40/ice40_opt.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index df10a2842..940a11063 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,8 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); + auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); + cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); -- cgit v1.2.3 From e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 Jan 2020 14:02:13 -0800 Subject: Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards Just like Verilog... --- techlibs/ice40/ice40_opt.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 940a11063..925ab31bb 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module) log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); - cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 }); + cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); -- cgit v1.2.3 From 245b8c4ab64c5c3bd7b9f71f94316a76a2576fd1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 Jan 2020 10:17:47 -0800 Subject: Fix unresolved conflict from #1573 --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5ba8c0e10..3c5599e4e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -318,7 +318,7 @@ struct SynthXilinxPass : public ScriptPass run("flatten", "(with '-flatten')"); active_design->scratchpad_unset("tribuf.added_something"); run("tribuf -logic"); - if (!do_iopad && active_design->scratchpad_get_bool("tribuf.added_something")) + if (noiopad && active_design->scratchpad_get_bool("tribuf.added_something")) log_error("Tristate buffers are unsupported without the '-iopad' option.\n"); run("deminout"); run("opt_expr"); -- cgit v1.2.3 From 7e0e42f907260e76e3c7cb01c907a0cf61a6e326 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Thu, 21 Nov 2019 13:05:30 +0100 Subject: xilinx: Add simulation model for DSP48 (Virtex 4). --- techlibs/xilinx/cells_sim.v | 230 +++++++++++++++++++++++- techlibs/xilinx/cells_xtra.py | 2 +- techlibs/xilinx/cells_xtra.v | 43 ----- techlibs/xilinx/tests/.gitignore | 3 + techlibs/xilinx/tests/test_dsp48_model.sh | 14 ++ techlibs/xilinx/tests/test_dsp48_model.v | 287 ++++++++++++++++++++++++++++++ 6 files changed, 534 insertions(+), 45 deletions(-) create mode 100644 techlibs/xilinx/tests/test_dsp48_model.sh create mode 100644 techlibs/xilinx/tests/test_dsp48_model.v (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 22dca3c47..eb145593e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2155,7 +2155,235 @@ assign PCOUT = P; endmodule -// TODO: DSP48 (Virtex 4). +module DSP48 ( + input signed [17:0] A, + input signed [17:0] B, + input signed [47:0] C, + input signed [17:0] BCIN, + input signed [47:0] PCIN, + input CARRYIN, + input [6:0] OPMODE, + input SUBTRACT, + input [1:0] CARRYINSEL, + output signed [47:0] P, + output signed [17:0] BCOUT, + output signed [47:0] PCOUT, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEC, + input CEM, + input CECARRYIN, + input CECINSUB, + input CECTRL, + input CEP, + input RSTA, + input RSTB, + input RSTC, + input RSTM, + input RSTCARRYIN, + input RSTCTRL, + input RSTP +); + +parameter integer AREG = 1; +parameter integer BREG = 1; +parameter integer CREG = 1; +parameter integer MREG = 1; +parameter integer PREG = 1; +parameter integer CARRYINREG = 1; +parameter integer CARRYINSELREG = 1; +parameter integer OPMODEREG = 1; +parameter integer SUBTRACTREG = 1; +parameter B_INPUT = "DIRECT"; +parameter LEGACY_MODE = "MULT18X18S"; + +wire signed [17:0] A_OUT; +wire signed [17:0] B_OUT; +wire signed [47:0] C_OUT; +wire signed [35:0] M_MULT; +wire signed [35:0] M_OUT; +wire signed [47:0] P_IN; +wire [6:0] OPMODE_OUT; +wire [1:0] CARRYINSEL_OUT; +wire CARRYIN_OUT; +wire SUBTRACT_OUT; +reg INT_CARRYIN_XY; +reg INT_CARRYIN_Z; +reg signed [47:0] XMUX; +reg signed [47:0] YMUX; +wire signed [47:0] XYMUX; +reg signed [47:0] ZMUX; +reg CIN; + +// The B input multiplexer. +wire signed [17:0] B_MUX; +assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN; + +// The cascade output. +assign BCOUT = B_OUT; +assign PCOUT = P; + +// The registers. +reg signed [17:0] A0_REG; +reg signed [17:0] A1_REG; +reg signed [17:0] B0_REG; +reg signed [17:0] B1_REG; +reg signed [47:0] C_REG; +reg signed [35:0] M_REG; +reg signed [47:0] P_REG; +reg [6:0] OPMODE_REG; +reg [1:0] CARRYINSEL_REG; +reg SUBTRACT_REG; +reg CARRYIN_REG; +reg INT_CARRYIN_XY_REG; + +initial begin + A0_REG = 0; + A1_REG = 0; + B0_REG = 0; + B1_REG = 0; + C_REG = 0; + M_REG = 0; + P_REG = 0; + OPMODE_REG = 0; + CARRYINSEL_REG = 0; + SUBTRACT_REG = 0; + CARRYIN_REG = 0; + INT_CARRYIN_XY_REG = 0; +end + +always @(posedge CLK) begin + if (RSTA) begin + A0_REG <= 0; + A1_REG <= 0; + end else if (CEA) begin + A0_REG <= A; + A1_REG <= A0_REG; + end + if (RSTB) begin + B0_REG <= 0; + B1_REG <= 0; + end else if (CEB) begin + B0_REG <= B_MUX; + B1_REG <= B0_REG; + end + if (RSTC) begin + C_REG <= 0; + end else if (CEC) begin + C_REG <= C; + end + if (RSTM) begin + M_REG <= 0; + end else if (CEM) begin + M_REG <= M_MULT; + end + if (RSTP) begin + P_REG <= 0; + end else if (CEP) begin + P_REG <= P_IN; + end + if (RSTCTRL) begin + OPMODE_REG <= 0; + CARRYINSEL_REG <= 0; + SUBTRACT_REG <= 0; + end else begin + if (CECTRL) begin + OPMODE_REG <= OPMODE; + CARRYINSEL_REG <= CARRYINSEL; + end + if (CECINSUB) + SUBTRACT_REG <= SUBTRACT; + end + if (RSTCARRYIN) begin + CARRYIN_REG <= 0; + INT_CARRYIN_XY_REG <= 0; + end else begin + if (CECINSUB) + CARRYIN_REG <= CARRYIN; + if (CECARRYIN) + INT_CARRYIN_XY_REG <= INT_CARRYIN_XY; + end +end + +// The register enables. +assign A_OUT = (AREG == 2) ? A1_REG : (AREG == 1) ? A0_REG : A; +assign B_OUT = (BREG == 2) ? B1_REG : (BREG == 1) ? B0_REG : B_MUX; +assign C_OUT = (CREG == 1) ? C_REG : C; +assign M_OUT = (MREG == 1) ? M_REG : M_MULT; +assign P = (PREG == 1) ? P_REG : P_IN; +assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE; +assign SUBTRACT_OUT = (SUBTRACTREG == 1) ? SUBTRACT_REG : SUBTRACT; +assign CARRYINSEL_OUT = (CARRYINSELREG == 1) ? CARRYINSEL_REG : CARRYINSEL; +assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN; + +// The multiplier. +assign M_MULT = A_OUT * B_OUT; + +// The post-adder inputs. +always @* begin + case (OPMODE_OUT[1:0]) + 2'b00: XMUX <= 0; + 2'b10: XMUX <= P; + 2'b11: XMUX <= {{12{A_OUT[17]}}, A_OUT, B_OUT}; + default: XMUX <= 48'hxxxxxxxxxxxx; + endcase + case (OPMODE_OUT[1:0]) + 2'b01: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17]; + 2'b11: INT_CARRYIN_XY <= ~A_OUT[17]; + // TODO: not tested in hardware. + default: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17]; + endcase +end + +always @* begin + case (OPMODE_OUT[3:2]) + 2'b00: YMUX <= 0; + 2'b11: YMUX <= C_OUT; + default: YMUX <= 48'hxxxxxxxxxxxx; + endcase +end + +assign XYMUX = (OPMODE_OUT[3:0] == 4'b0101) ? M_OUT : (XMUX + YMUX); + +always @* begin + case (OPMODE_OUT[6:4]) + 3'b000: ZMUX <= 0; + 3'b001: ZMUX <= PCIN; + 3'b010: ZMUX <= P; + 3'b011: ZMUX <= C_OUT; + 3'b101: ZMUX <= {{17{PCIN[47]}}, PCIN[47:17]}; + 3'b110: ZMUX <= {{17{P[47]}}, P[47:17]}; + default: ZMUX <= 48'hxxxxxxxxxxxx; + endcase + // TODO: check how all this works on actual hw. + if (OPMODE_OUT[1:0] == 2'b10) + INT_CARRYIN_Z <= ~P[47]; + else + case (OPMODE_OUT[6:4]) + 3'b001: INT_CARRYIN_Z <= ~PCIN[47]; + 3'b010: INT_CARRYIN_Z <= ~P[47]; + 3'b101: INT_CARRYIN_Z <= ~PCIN[47]; + 3'b110: INT_CARRYIN_Z <= ~P[47]; + default: INT_CARRYIN_Z <= 1'bx; + endcase +end + +always @* begin + case (CARRYINSEL_OUT) + 2'b00: CIN <= CARRYIN_OUT; + 2'b01: CIN <= INT_CARRYIN_Z; + 2'b10: CIN <= INT_CARRYIN_XY; + 2'b11: CIN <= INT_CARRYIN_XY_REG; + default: CIN <= 1'bx; + endcase +end + +// The post-adder. +assign P_IN = SUBTRACT_OUT ? (ZMUX - (XYMUX + CIN)) : (ZMUX + XYMUX + CIN); + +endmodule // TODO: DSP48E (Virtex 5). diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index d5c58c5d7..06e982a0e 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -209,7 +209,7 @@ CELLS = [ # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 - Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 + # Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), # Ultrascale diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index c3e5c72f9..54e48f1a6 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -5476,49 +5476,6 @@ module URAM288_BASE (...); input SLEEP; endmodule -module DSP48 (...); - parameter integer AREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter LEGACY_MODE = "MULT18X18S"; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter integer SUBTRACTREG = 1; - output [17:0] BCOUT; - output [47:0] P; - output [47:0] PCOUT; - input [17:0] A; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYIN; - input [1:0] CARRYINSEL; - input CEA; - input CEB; - input CEC; - input CECARRYIN; - input CECINSUB; - input CECTRL; - input CEM; - input CEP; - (* clkbuf_sink *) - input CLK; - input [6:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTB; - input RSTC; - input RSTCARRYIN; - input RSTCTRL; - input RSTM; - input RSTP; - input SUBTRACT; -endmodule - module DSP48E (...); parameter SIM_MODE = "SAFE"; parameter integer ACASCREG = 1; diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore index 848f88d53..0d9c28fde 100644 --- a/techlibs/xilinx/tests/.gitignore +++ b/techlibs/xilinx/tests/.gitignore @@ -12,4 +12,7 @@ test_dsp48a_model_ref.v test_dsp48a1_model_ref.v test_dsp48a1_model_uut.v test_dsp48a1_model +test_dsp48_model_ref.v +test_dsp48_model_uut.v +test_dsp48_model *.vcd diff --git a/techlibs/xilinx/tests/test_dsp48_model.sh b/techlibs/xilinx/tests/test_dsp48_model.sh new file mode 100644 index 000000000..9a73f9b0c --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48_model.sh @@ -0,0 +1,14 @@ +#!/bin/bash +set -ex +if [ -z $ISE_DIR ]; then + ISE_DIR=/opt/Xilinx/ISE/14.7 +fi +sed 's/DSP48 /DSP48_UUT /; /DSP48_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48_model_uut.v +if [ ! -f "test_dsp48_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48.v test_dsp48_model_ref.v +fi +for tb in mult_allreg mult_noreg mult_inreg +do + iverilog -s $tb -s glbl -o test_dsp48_model test_dsp48_model.v test_dsp48_model_uut.v test_dsp48_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v + vvp -N ./test_dsp48_model +done diff --git a/techlibs/xilinx/tests/test_dsp48_model.v b/techlibs/xilinx/tests/test_dsp48_model.v new file mode 100644 index 000000000..d69c00e93 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48_model.v @@ -0,0 +1,287 @@ +`timescale 1ns / 1ps + +module testbench; + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter integer CREG = 1; + parameter integer MREG = 1; + parameter integer PREG = 1; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer OPMODEREG = 1; + parameter integer SUBTRACTREG = 1; + parameter B_INPUT = "DIRECT"; + parameter LEGACY_MODE = "NONE"; + + reg CLK; + reg CEA, CEB, CEC, CEM, CEP, CECARRYIN, CECINSUB, CECTRL; + reg RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL; + reg [17:0] A; + reg [17:0] B; + reg [47:0] C; + reg [17:0] BCIN; + reg [47:0] PCIN; + reg CARRYIN; + reg [6:0] OPMODE; + reg SUBTRACT; + reg [1:0] CARRYINSEL; + + output [47:0] P, REF_P; + output [17:0] BCOUT, REF_BCOUT; + output [47:0] PCOUT, REF_PCOUT; + + integer errcount = 0; + + reg ERROR_FLAG = 0; + + task clkcycle; + begin + #5; + CLK = ~CLK; + #10; + CLK = ~CLK; + #2; + ERROR_FLAG = 0; + if (REF_BCOUT !== BCOUT) begin + $display("ERROR at %1t: REF_BCOUT=%b UUT_BCOUT=%b DIFF=%b", $time, REF_BCOUT, BCOUT, REF_BCOUT ^ BCOUT); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_P !== P) begin + $display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_PCOUT !== PCOUT) begin + $display("ERROR at %1t: REF_PCOUT=%b UUT_PCOUT=%b DIFF=%b", $time, REF_PCOUT, PCOUT, REF_PCOUT ^ PCOUT); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + #3; + end + endtask + + reg config_valid = 0; + task drc; + begin + config_valid = 1; + + if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; + if (OPMODE[1:0] == 2'b00 && CARRYINSEL == 2'b10) config_valid = 0; + if (OPMODE[1:0] == 2'b10 && CARRYINSEL == 2'b10) config_valid = 0; + if (OPMODE[1:0] == 2'b00 && CARRYINSEL == 2'b11) config_valid = 0; + if (OPMODE[1:0] == 2'b10 && CARRYINSEL == 2'b11) config_valid = 0; + if (OPMODE[3:2] == 2'b10) config_valid = 0; + if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; + if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0; + if (OPMODE[6:4] == 3'b100) config_valid = 0; + if (OPMODE[6:4] == 3'b111) config_valid = 0; + if (OPMODE[6:4] == 3'b000 && CARRYINSEL == 2'b01) config_valid = 0; + if (OPMODE[6:4] == 3'b011 && CARRYINSEL == 2'b01) config_valid = 0; + + // Xilinx models consider these combinations invalid for an unknown reason. + if (CARRYINSEL == 2'b01 && OPMODE[3:2] == 2'b00) config_valid = 0; + if (CARRYINSEL == 2'b10 && OPMODE == 7'b0000011) config_valid = 0; + if (CARRYINSEL == 2'b10 && OPMODE == 7'b0000101) config_valid = 0; + if (CARRYINSEL == 2'b10 && OPMODE == 7'b0100011) config_valid = 0; + if (CARRYINSEL == 2'b10 && OPMODE == 7'b0111111) config_valid = 0; + if (CARRYINSEL == 2'b10 && OPMODE == 7'b1100011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0000011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0000101) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0011111) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0010011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0100011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0100101) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0101111) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0110011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b0111111) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b1010011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b1011111) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b1100011) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b1100101) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE == 7'b1101111) config_valid = 0; + + if (CARRYINSEL == 2'b10 && OPMODE[3:0] == 4'b0101 && MREG == 1) config_valid = 0; + if (CARRYINSEL == 2'b11 && OPMODE[3:0] == 4'b0101 && MREG == 0) config_valid = 0; + end + endtask + + initial begin + $dumpfile("test_dsp48_model.vcd"); + $dumpvars(0, testbench); + + #2; + CLK = 1'b0; + {CEA, CEB, CEC, CEM, CEP, CECARRYIN, CECINSUB, CECTRL} = 8'b11111111; + {A, B, C, PCIN, OPMODE, SUBTRACT, CARRYIN, CARRYINSEL} = 0; + {RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL} = 7'b1111111; + repeat (10) begin + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + end + {RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL} = 0; + + repeat (100000) begin + clkcycle; + config_valid = 0; + while (!config_valid) begin + A = $urandom; + B = $urandom; + C = {$urandom, $urandom}; + BCIN = $urandom; + PCIN = {$urandom, $urandom}; + + {CEA, CEB, CEC, CEM, CEP, CECARRYIN, CECINSUB, CECTRL} = $urandom | $urandom | $urandom; + {RSTA, RSTB, RSTC, RSTM, RSTP, RSTCARRYIN, RSTCTRL} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + {CARRYIN, CARRYINSEL, OPMODE, SUBTRACT} = $urandom; + + drc; + end + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + DSP48 #( + .AREG (AREG), + .BREG (BREG), + .CREG (CREG), + .MREG (MREG), + .PREG (PREG), + .CARRYINREG (CARRYINREG), + .CARRYINSELREG (CARRYINSELREG), + .OPMODEREG (OPMODEREG), + .SUBTRACTREG (SUBTRACTREG), + .B_INPUT (B_INPUT), + .LEGACY_MODE (LEGACY_MODE) + ) ref ( + .A (A), + .B (B), + .C (C), + .BCIN (BCIN), + .PCIN (PCIN), + .CARRYIN (CARRYIN), + .OPMODE (OPMODE), + .SUBTRACT (SUBTRACT), + .CARRYINSEL (CARRYINSEL), + .BCOUT (REF_BCOUT), + .P (REF_P), + .PCOUT (REF_PCOUT), + .CEA (CEA), + .CEB (CEB), + .CEC (CEC), + .CEM (CEM), + .CEP (CEP), + .CECARRYIN (CECARRYIN), + .CECINSUB (CECINSUB), + .CECTRL (CECTRL), + .CLK (CLK), + .RSTA (RSTA), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTM (RSTM), + .RSTP (RSTP), + .RSTCARRYIN (RSTCARRYIN), + .RSTCTRL (RSTCTRL) + ); + + DSP48_UUT #( + .AREG (AREG), + .BREG (BREG), + .CREG (CREG), + .MREG (MREG), + .PREG (PREG), + .CARRYINREG (CARRYINREG), + .CARRYINSELREG (CARRYINSELREG), + .OPMODEREG (OPMODEREG), + .SUBTRACTREG (SUBTRACTREG), + .B_INPUT (B_INPUT), + .LEGACY_MODE (LEGACY_MODE) + ) uut ( + .A (A), + .B (B), + .C (C), + .BCIN (BCIN), + .PCIN (PCIN), + .CARRYIN (CARRYIN), + .OPMODE (OPMODE), + .SUBTRACT (SUBTRACT), + .CARRYINSEL (CARRYINSEL), + .BCOUT (BCOUT), + .P (P), + .PCOUT (PCOUT), + .CEA (CEA), + .CEB (CEB), + .CEC (CEC), + .CEM (CEM), + .CEP (CEP), + .CECARRYIN (CECARRYIN), + .CECINSUB (CECINSUB), + .CECTRL (CECTRL), + .CLK (CLK), + .RSTA (RSTA), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTM (RSTM), + .RSTP (RSTP), + .RSTCARRYIN (RSTCARRYIN), + .RSTCTRL (RSTCTRL) + ); +endmodule + +module mult_noreg; + testbench #( + .AREG (0), + .BREG (0), + .CREG (0), + .MREG (0), + .PREG (0), + .CARRYINREG (0), + .CARRYINSELREG (0), + .OPMODEREG (0), + .SUBTRACTREG (0), + .B_INPUT ("DIRECT") + ) testbench (); +endmodule + +module mult_allreg; + testbench #( + .AREG (1), + .BREG (1), + .CREG (1), + .MREG (1), + .PREG (1), + .CARRYINREG (1), + .CARRYINSELREG (1), + .OPMODEREG (1), + .SUBTRACTREG (1), + .B_INPUT ("CASCADE") + ) testbench (); +endmodule + +module mult_inreg; + testbench #( + .AREG (1), + .BREG (1), + .CREG (1), + .MREG (0), + .PREG (0), + .CARRYINREG (1), + .CARRYINSELREG (0), + .OPMODEREG (0), + .SUBTRACTREG (0), + .B_INPUT ("DIRECT") + ) testbench (); +endmodule -- cgit v1.2.3 From 0fd64aab25787e2591080cf71192ee16fcf2ae9f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 Jan 2020 17:41:57 -0800 Subject: synth_xilinx: fix help when no active_design; fixes #1664 --- techlibs/xilinx/synth_xilinx.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3c5599e4e..9b4b1f71a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -316,9 +316,10 @@ struct SynthXilinxPass : public ScriptPass run("proc"); if (flatten || help_mode) run("flatten", "(with '-flatten')"); - active_design->scratchpad_unset("tribuf.added_something"); + if (active_design) + active_design->scratchpad_unset("tribuf.added_something"); run("tribuf -logic"); - if (noiopad && active_design->scratchpad_get_bool("tribuf.added_something")) + if (noiopad && active_design && active_design->scratchpad_get_bool("tribuf.added_something")) log_error("Tristate buffers are unsupported without the '-iopad' option.\n"); run("deminout"); run("opt_expr"); -- cgit v1.2.3 From c5971cb16cdc934b9d2c615e37d0eed4cc3b5c8d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 Jan 2020 17:48:43 -0800 Subject: synth_xilinx: cleanup help --- techlibs/xilinx/synth_xilinx.cc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 9b4b1f71a..8119d307c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -530,7 +530,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_cells")) { // Needs to be done before logic optimization, so that inverters (OE vs T) are handled. if (help_mode || !noiopad) - run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if not '-noiopad')"); + run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(skip if '-noiopad')"); std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v"; if (widemux > 0) techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux); @@ -593,17 +593,15 @@ struct SynthXilinxPass : public ScriptPass if (!nosrl || help_mode) run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"; - if (help_mode) - techmap_args += stringf("[-map %s]", ff_map_file.c_str()); - else if (!abc9) + if (help_mode || !abc9) techmap_args += stringf(" -map %s", ff_map_file.c_str()); - run("techmap " + techmap_args, "(only if '-abc9')"); + run("techmap " + techmap_args); run("xilinx_dffopt"); } if (check_label("finalize")) { if (help_mode || !noclkbuf) - run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')"); + run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')"); if (help_mode || ise) run("extractinv -inv INV O:I", "(only if '-ise')"); run("clean"); -- cgit v1.2.3