From 3459d283492769263e73a0e35d0e5d253c0bbec7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Sep 2019 12:22:15 -0700
Subject: Add comments

---
 techlibs/xilinx/abc_xc7.box | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 554cc0cf0..20da3b8a0 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -15,7 +15,10 @@ F7MUX 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
-# Box containing MUXF7.[AB] + MUXF8
+# Box containing MUXF7.[AB] + MUXF8,
+#   Necessary to make these an atomic unit so that
+#   ABC cannot optimise just one of the MUXF7 away
+#   and expect to save on its delay
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
 $__MUXF78 3 1 6 1
@@ -40,6 +43,11 @@ CARRY4 4 1 10 8
 
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+#   Necessary since RAMD* and SRL* have both combinatorial (i.e.
+#   same-cycle read operation) and sequential (write operation
+#   is only committed on the next clock edge).
+#   To model the combinatorial path, such cells have to be split
+#   into comb and seq parts, with this box modelling only the former.
 # Inputs: A S0 S1 S2 S3 S4 S5
 # Outputs: Y
 $__ABC_LUT6 2000 0 7 1
-- 
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