From b97fe6e86651b3a4736c46a49d76878beb088a8c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 14:20:43 -0700 Subject: Work in progress for renaming labels/options in synth_xilinx --- techlibs/xilinx/drams.txt | 60 ------------------------- techlibs/xilinx/drams_map.v | 97 ----------------------------------------- techlibs/xilinx/lutrams.txt | 60 +++++++++++++++++++++++++ techlibs/xilinx/lutrams_map.v | 97 +++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/synth_xilinx.cc | 31 +++++++------ 5 files changed, 174 insertions(+), 171 deletions(-) delete mode 100644 techlibs/xilinx/drams.txt delete mode 100644 techlibs/xilinx/drams_map.v create mode 100644 techlibs/xilinx/lutrams.txt create mode 100644 techlibs/xilinx/lutrams_map.v (limited to 'techlibs') diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt deleted file mode 100644 index 2613c206c..000000000 --- a/techlibs/xilinx/drams.txt +++ /dev/null @@ -1,60 +0,0 @@ - -bram $__XILINX_RAM32X1D - init 1 - abits 5 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM64X1D - init 1 - abits 6 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM128X1D - init 1 - abits 7 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -match $__XILINX_RAM32X1D - min bits 3 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM64X1D - min bits 5 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM128X1D - min bits 9 - min wports 1 - make_outreg -endmatch - diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v deleted file mode 100644 index 77041ca86..000000000 --- a/techlibs/xilinx/drams_map.v +++ /dev/null @@ -1,97 +0,0 @@ - -module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [31:0] INIT = 32'bx; - parameter CLKPOL2 = 1; - input CLK1; - - input [4:0] A1ADDR; - output A1DATA; - - input [4:0] B1ADDR; - input B1DATA; - input B1EN; - - RAM32X1D #( - .INIT(INIT), - .IS_WCLK_INVERTED(!CLKPOL2) - ) _TECHMAP_REPLACE_ ( - .DPRA0(A1ADDR[0]), - .DPRA1(A1ADDR[1]), - .DPRA2(A1ADDR[2]), - .DPRA3(A1ADDR[3]), - .DPRA4(A1ADDR[4]), - .DPO(A1DATA), - - .A0(B1ADDR[0]), - .A1(B1ADDR[1]), - .A2(B1ADDR[2]), - .A3(B1ADDR[3]), - .A4(B1ADDR[4]), - .D(B1DATA), - .WCLK(CLK1), - .WE(B1EN) - ); -endmodule - -module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [63:0] INIT = 64'bx; - parameter CLKPOL2 = 1; - input CLK1; - - input [5:0] A1ADDR; - output A1DATA; - - input [5:0] B1ADDR; - input B1DATA; - input B1EN; - - RAM64X1D #( - .INIT(INIT), - .IS_WCLK_INVERTED(!CLKPOL2) - ) _TECHMAP_REPLACE_ ( - .DPRA0(A1ADDR[0]), - .DPRA1(A1ADDR[1]), - .DPRA2(A1ADDR[2]), - .DPRA3(A1ADDR[3]), - .DPRA4(A1ADDR[4]), - .DPRA5(A1ADDR[5]), - .DPO(A1DATA), - - .A0(B1ADDR[0]), - .A1(B1ADDR[1]), - .A2(B1ADDR[2]), - .A3(B1ADDR[3]), - .A4(B1ADDR[4]), - .A5(B1ADDR[5]), - .D(B1DATA), - .WCLK(CLK1), - .WE(B1EN) - ); -endmodule - -module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); - parameter [127:0] INIT = 128'bx; - parameter CLKPOL2 = 1; - input CLK1; - - input [6:0] A1ADDR; - output A1DATA; - - input [6:0] B1ADDR; - input B1DATA; - input B1EN; - - RAM128X1D #( - .INIT(INIT), - .IS_WCLK_INVERTED(!CLKPOL2) - ) _TECHMAP_REPLACE_ ( - .DPRA(A1ADDR), - .DPO(A1DATA), - - .A(B1ADDR), - .D(B1DATA), - .WCLK(CLK1), - .WE(B1EN) - ); -endmodule - diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt new file mode 100644 index 000000000..2613c206c --- /dev/null +++ b/techlibs/xilinx/lutrams.txt @@ -0,0 +1,60 @@ + +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1D + init 1 + abits 6 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM128X1D + init 1 + abits 7 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X1D + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM128X1D + min bits 9 + min wports 1 + make_outreg +endmatch + diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v new file mode 100644 index 000000000..77041ca86 --- /dev/null +++ b/techlibs/xilinx/lutrams_map.v @@ -0,0 +1,97 @@ + +module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [31:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR; + output A1DATA; + + input [4:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM32X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPRA4(A1ADDR[4]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .A4(B1ADDR[4]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [5:0] A1ADDR; + output A1DATA; + + input [5:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM64X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPRA4(A1ADDR[4]), + .DPRA5(A1ADDR[5]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .A4(B1ADDR[4]), + .A5(B1ADDR[5]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + +module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [127:0] INIT = 128'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [6:0] A1ADDR; + output A1DATA; + + input [6:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM128X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA(A1ADDR), + .DPO(A1DATA), + + .A(B1ADDR), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b672a0d4f..a6c1fa873 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,13 +64,13 @@ struct SynthXilinxPass : public ScriptPass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -nobram\n"); - log(" disable inference of block rams\n"); + log(" do not use block RAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); - log(" disable inference of distributed rams\n"); + log(" -nolutram\n"); + log(" do not use distributed RAM cells in output netlist\n"); log("\n"); log(" -nosrl\n"); - log(" disable inference of shift registers\n"); + log(" do not use distributed SRL cells in output netlist\n"); log("\n"); log(" -nocarry\n"); log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); @@ -104,7 +104,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9; + bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9; int widemux; void clear_flags() YS_OVERRIDE @@ -118,7 +118,7 @@ struct SynthXilinxPass : public ScriptPass vpr = false; nocarry = false; nobram = false; - nodram = false; + nolutram = false; nosrl = false; nocarry = false; nowidelut = false; @@ -186,8 +186,8 @@ struct SynthXilinxPass : public ScriptPass nobram = true; continue; } - if (args[argidx] == "-nodram") { - nodram = true; + if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") { + nolutram = true; continue; } if (args[argidx] == "-nosrl") { @@ -284,7 +284,7 @@ struct SynthXilinxPass : public ScriptPass run("opt_clean"); } - if (check_label("bram", "(skip if '-nobram')")) { + if (check_label("map_bram", "(skip if '-nobram')")) { if (help_mode) { run("memory_bram -rules +/xilinx/{family}_brams.txt"); run("techmap -map +/xilinx/{family}_brams_map.v"); @@ -301,20 +301,23 @@ struct SynthXilinxPass : public ScriptPass } } - if (check_label("dram", "(skip if '-nodram')")) { - if (!nodram || help_mode) { - run("memory_bram -rules +/xilinx/drams.txt"); - run("techmap -map +/xilinx/drams_map.v"); + if (check_label("map_lutram", "(skip if '-nolutram')")) { + if (!nolutram || help_mode) { + run("memory_bram -rules +/xilinx/lutrams.txt"); + run("techmap -map +/xilinx/lutrams_map.v"); } } - if (check_label("fine")) { + if (check_label("map_ffram")) { if (widemux > 0) run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover // performs less efficiently else run("opt -fast -full"); run("memory_map"); + } + + if (check_label("fine")) { run("dffsr2dff"); run("dff2dffe"); if (help_mode) { -- cgit v1.2.3 From 43616e1414ed3d98b44c4a55f4d08e2d10664aa1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 14:51:55 -0700 Subject: Update Makefile too --- techlibs/xilinx/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 2c6e7432e..2b1af289c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -32,8 +32,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) -- cgit v1.2.3 From ab98f604fd1319e0f42b0c5dc8bb6be5d3d2ba38 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 3 Aug 2019 12:29:30 +0200 Subject: Initial EFINIX support --- techlibs/efinix/Makefile.inc | 6 ++ techlibs/efinix/arith_map.v | 78 +++++++++++++++ techlibs/efinix/cells_map.v | 45 +++++++++ techlibs/efinix/cells_sim.v | 36 +++++++ techlibs/efinix/synth_efinix.cc | 205 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 370 insertions(+) create mode 100644 techlibs/efinix/Makefile.inc create mode 100644 techlibs/efinix/arith_map.v create mode 100644 techlibs/efinix/cells_map.v create mode 100644 techlibs/efinix/cells_sim.v create mode 100644 techlibs/efinix/synth_efinix.cc (limited to 'techlibs') diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc new file mode 100644 index 000000000..3f3394c96 --- /dev/null +++ b/techlibs/efinix/Makefile.inc @@ -0,0 +1,6 @@ + +OBJS += techlibs/efinix/synth_efinix.o + +$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v new file mode 100644 index 000000000..ae955663c --- /dev/null +++ b/techlibs/efinix/arith_map.v @@ -0,0 +1,78 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2018 Miodrag Milanovic + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_efinix_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH+1:0] COx; + wire [Y_WIDTH+2:0] C = {COx, CI}; + + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + adder_cin ( + .I0(C[0]), + .I1(1'b1), + .CI(1'b0), + .CO(COx[0]) + ); + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + adder_i ( + .I0(AA[i]), + .I1(BB[i]), + .CI(C[i+1]), + .O(Y[i]), + .CO(COx[i+1]) + ); + end: slice + endgenerate + + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + adder_cout ( + .I0(1'b0), + .I1(1'b0), + .CI(C[Y_WIDTH+1]), + .O(COx[Y_WIDTH+1]) + ); + assign CO = COx[Y_WIDTH+1]; + /* End implementation */ + assign X = AA ^ BB; +endmodule \ No newline at end of file diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v new file mode 100644 index 000000000..70c19635e --- /dev/null +++ b/techlibs/efinix/cells_map.v @@ -0,0 +1,45 @@ +module \$_DFF_N_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule +module \$_DFF_P_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule +module \$_DFFE_NP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule + +module \$_DFFE_PN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule +module \$_DFFE_PP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule + +module \$_DFF_NN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule + +`ifndef NO_LUT +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0)); + end else + if (WIDTH == 2) begin + EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0)); + end else + if (WIDTH == 3) begin + EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0)); + end else + if (WIDTH == 4) begin + EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule +`endif diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v new file mode 100644 index 000000000..aaff955a2 --- /dev/null +++ b/techlibs/efinix/cells_sim.v @@ -0,0 +1,36 @@ +module EFX_LUT4( + output O, + input I0, + input I1, + input I2, + input I3 +); + parameter LUTMASK = 16'h0000; +endmodule + +module EFX_ADD( + output O, + output CO, + input I0, + input I1, + input CI +); + parameter I0_POLARITY = 1; + parameter I1_POLARITY = 1; +endmodule + +module EFX_FF( + output Q, + input D, + input CE, + input CLK, + input SR +); + parameter CLK_POLARITY = 1; + parameter CE_POLARITY = 1; + parameter SR_POLARITY = 1; + parameter SR_SYNC = 0; + parameter SR_VALUE = 0; + parameter SR_SYNC_PRIORITY = 0; + parameter D_POLARITY = 1; +endmodule \ No newline at end of file diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc new file mode 100644 index 000000000..9c644d363 --- /dev/null +++ b/techlibs/efinix/synth_efinix.cc @@ -0,0 +1,205 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2019 Miodrag Milanovic + * Copyright (C) 2019 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthEfinixPass : public ScriptPass +{ + SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { } + + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_efinix [options]\n"); + log("\n"); + log("This command runs synthesis for Efinix FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, edif_file, json_file; + bool flatten, retime; + + void clear_flags() YS_OVERRIDE + { + top_opt = "-auto-top"; + edif_file = ""; + json_file = ""; + flatten = true; + retime = false; + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_EFINIX pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() YS_OVERRIDE + { + if (check_label("begin")) + { + run("read_verilog -lib +/efinix/cells_sim.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (flatten && check_label("flatten", "(unless -noflatten)")) + { + run("proc"); + run("flatten"); + run("tribuf -logic"); + run("deminout"); + } + + if (check_label("coarse")) + { + run("synth -run coarse"); + } + + if (check_label("fine")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + run("techmap -map +/techmap.v -map +/efinix/arith_map.v"); + if (retime || help_mode) + run("abc -dff", "(only if -retime)"); + } + + if (check_label("map_ffs")) + { + run("dffsr2dff"); + run("techmap -D NO_LUT -map +/efinix/cells_map.v"); + run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit"); + run("opt_expr -mux_undef"); + run("simplemap"); + } + + if (check_label("map_luts")) + { + run("abc -lut 4"); + run("clean"); + } + + if (check_label("map_cells")) + { + run("techmap -map +/efinix/cells_map.v"); + run("clean"); + } + + if (check_label("check")) + { + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + } + + if (check_label("edif")) + { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthEfinixPass; + +PRIVATE_NAMESPACE_END -- cgit v1.2.3 From 6e210f26fa97fa65c420534f0ec0e26eeb1b078a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 3 Aug 2019 14:40:23 +0200 Subject: Custom step to add global clock buffers --- techlibs/efinix/Makefile.inc | 1 + techlibs/efinix/cells_sim.v | 10 +++- techlibs/efinix/efinix_gbuf.cc | 113 ++++++++++++++++++++++++++++++++++++++++ techlibs/efinix/synth_efinix.cc | 6 +++ 4 files changed, 129 insertions(+), 1 deletion(-) create mode 100644 techlibs/efinix/efinix_gbuf.cc (limited to 'techlibs') diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 3f3394c96..82dfa3cd8 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/efinix/synth_efinix.o +OBJS += techlibs/efinix/efinix_gbuf.o $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index aaff955a2..2cbf8ae4b 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -33,4 +33,12 @@ module EFX_FF( parameter SR_VALUE = 0; parameter SR_SYNC_PRIORITY = 0; parameter D_POLARITY = 1; -endmodule \ No newline at end of file +endmodule + +module EFX_GBUFCE ( + input CE, + input I, + output O +); + parameter CE_POLARITY = 1'b1; +endmodule diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc new file mode 100644 index 000000000..50f84c30c --- /dev/null +++ b/techlibs/efinix/efinix_gbuf.cc @@ -0,0 +1,113 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2019 Miodrag Milanovic + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +static void handle_gbufs(Module *module) +{ + SigMap sigmap(module); + + pool clk_bits; + dict rewrite_bits; + vector> pad_bits; + + for (auto cell : module->cells()) + { + if (cell->type == "\\EFX_FF") { + for (auto bit : sigmap(cell->getPort("\\CLK"))) + clk_bits.insert(bit); + } + } + + for (auto wire : vector(module->wires())) + { + if (!wire->port_input) + continue; + + for (int index = 0; index < GetSize(wire); index++) + { + SigBit bit(wire, index); + SigBit canonical_bit = sigmap(bit); + + if (!clk_bits.count(canonical_bit)) + continue; + + Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE"); + SigBit new_bit = module->addWire(NEW_ID); + c->setParam("\\CE_POLARITY", State::S1); + c->setPort("\\O", new_bit); + c->setPort("\\CE", State::S1); + pad_bits.push_back(make_pair(c, bit)); + rewrite_bits[canonical_bit] = new_bit; + + log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit)); + } + } + + auto rewrite_function = [&](SigSpec &s) { + for (auto &bit : s) { + SigBit canonical_bit = sigmap(bit); + if (rewrite_bits.count(canonical_bit)) + bit = rewrite_bits.at(canonical_bit); + } + }; + + module->rewrite_sigspecs(rewrite_function); + + for (auto &it : pad_bits) + it.first->setPort("\\I", it.second); +} + +struct EfinixGbufPass : public Pass { + EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" efinix_gbuf [options] [selection]\n"); + log("\n"); + log("Add Efinix global clock buffers to top module as needed.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + Module *module = design->top_module(); + + if (module == nullptr) + log_cmd_error("No top module found.\n"); + + handle_gbufs(module); + } +} EfinixGbufPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 9c644d363..3f17bafa3 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -181,6 +181,12 @@ struct SynthEfinixPass : public ScriptPass run("clean"); } + if (check_label("map_gbuf")) + { + run("efinix_gbuf"); + run("clean"); + } + if (check_label("check")) { run("hierarchy -check"); -- cgit v1.2.3 From cf96f41c6d9c405ddc039a8d0629731924b774ed Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 4 Aug 2019 11:46:36 +0200 Subject: Added bram support --- techlibs/efinix/Makefile.inc | 3 ++ techlibs/efinix/bram.txt | 32 ++++++++++++ techlibs/efinix/brams_map.v | 65 +++++++++++++++++++++++ techlibs/efinix/cells_sim.v | 65 ++++++++++++++++++++++- techlibs/efinix/efinix_determine_init.cc | 89 ++++++++++++++++++++++++++++++++ techlibs/efinix/synth_efinix.cc | 7 +++ 6 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 techlibs/efinix/bram.txt create mode 100644 techlibs/efinix/brams_map.v create mode 100644 techlibs/efinix/efinix_determine_init.cc (limited to 'techlibs') diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 82dfa3cd8..d0593baec 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -1,7 +1,10 @@ OBJS += techlibs/efinix/synth_efinix.o OBJS += techlibs/efinix/efinix_gbuf.o +OBJS += techlibs/efinix/efinix_determine_init.o $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt)) \ No newline at end of file diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/bram.txt new file mode 100644 index 000000000..0b3fd9308 --- /dev/null +++ b/techlibs/efinix/bram.txt @@ -0,0 +1,32 @@ +bram $__EFINIX_5K + init 1 + + abits 8 @a8d16 + dbits 16 @a8d16 + abits 9 @a9d8 + dbits 8 @a9d8 + abits 10 @a10d4 + dbits 4 @a10d4 + abits 11 @a11d2 + dbits 2 @a11d2 + abits 12 @a12d1 + dbits 1 @a12d1 + abits 8 @a8d20 + dbits 20 @a8d20 + abits 9 @a9d10 + dbits 10 @a9d10 + + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 2 + clocks 2 3 + clkpol 2 3 +endbram + +match $__EFINIX_5K + min bits 256 + min efficiency 5 + shuffle_enable B +endmatch diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v new file mode 100644 index 000000000..9ef01d026 --- /dev/null +++ b/techlibs/efinix/brams_map.v @@ -0,0 +1,65 @@ +module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 8; + parameter CFG_DBITS = 20; + parameter CFG_ENABLE_A = 2; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [5119:0] INIT = 5119'bx; + parameter TRANSP2 = 0; + + input CLK2; + input CLK3; + + input [CFG_ABITS-1:0] A1ADDR; + input [CFG_DBITS-1:0] A1DATA; + input [CFG_ENABLE_A-1:0] A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + output [CFG_DBITS-1:0] B1DATA; + input B1EN; + + localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"; + + EFX_RAM_5K #( + .READ_WIDTH(20), + .WRITE_WIDTH(20), + .OUTPUT_REG(1'b0), + .RCLK_POLARITY(1'b1), + .RE_POLARITY(1'b1), + .WCLK_POLARITY(1'b1), + .WE_POLARITY(1'b1), + .WCLKE_POLARITY(1'b1), + .WRITE_MODE(WRITEMODE_A), + .INIT_0(INIT[ 0*256 +: 256]), + .INIT_1(INIT[ 1*256 +: 256]), + .INIT_2(INIT[ 2*256 +: 256]), + .INIT_3(INIT[ 3*256 +: 256]), + .INIT_4(INIT[ 4*256 +: 256]), + .INIT_5(INIT[ 5*256 +: 256]), + .INIT_6(INIT[ 6*256 +: 256]), + .INIT_7(INIT[ 7*256 +: 256]), + .INIT_8(INIT[ 8*256 +: 256]), + .INIT_9(INIT[ 9*256 +: 256]), + .INIT_A(INIT[10*256 +: 256]), + .INIT_B(INIT[11*256 +: 256]), + .INIT_C(INIT[12*256 +: 256]), + .INIT_D(INIT[13*256 +: 256]), + .INIT_E(INIT[14*256 +: 256]), + .INIT_F(INIT[15*256 +: 256]), + .INIT_10(INIT[16*256 +: 256]), + .INIT_11(INIT[17*256 +: 256]), + .INIT_12(INIT[18*256 +: 256]), + .INIT_13(INIT[19*256 +: 256]) + ) _TECHMAP_REPLACE_ ( + .WDATA(A1DATA), + .WADDR(A1ADDR), + .WE(A1EN), + .WCLK(CLK2), + .WCLKE(1'b1), + .RDATA(B1DATA), + .RADDR(B1ADDR), + .RE(B1EN), + .RCLK(CLK3) + ); +endmodule diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index 2cbf8ae4b..8c8f6afaa 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -35,10 +35,73 @@ module EFX_FF( parameter D_POLARITY = 1; endmodule -module EFX_GBUFCE ( +module EFX_GBUFCE( input CE, input I, output O ); parameter CE_POLARITY = 1'b1; endmodule + +module EFX_RAM_5K( + input [WRITE_WIDTH-1:0] WDATA, + input [WRITE_ADDR_WIDTH-1:0] WADDR, + input WE, + input WCLK, + input WCLKE, + output [READ_WIDTH-1:0] RDATA, + input [READ_ADDR_WIDTH-1:0] RADDR, + input RE, + input RCLK +); + parameter READ_WIDTH = 20; + parameter WRITE_WIDTH = 20; + parameter OUTPUT_REG = 1'b0; + parameter RCLK_POLARITY = 1'b1; + parameter RE_POLARITY = 1'b1; + parameter WCLK_POLARITY = 1'b1; + parameter WE_POLARITY = 1'b1; + parameter WCLKE_POLARITY = 1'b1; + parameter WRITE_MODE = "READ_FIRST"; + parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + localparam READ_ADDR_WIDTH = + (READ_WIDTH == 16) ? 8 : // 256x16 + (READ_WIDTH == 8) ? 9 : // 512x8 + (READ_WIDTH == 4) ? 10 : // 1024x4 + (READ_WIDTH == 2) ? 11 : // 2048x2 + (READ_WIDTH == 1) ? 12 : // 4096x1 + (READ_WIDTH == 20) ? 8 : // 256x20 + (READ_WIDTH == 10) ? 9 : // 512x10 + (READ_WIDTH == 5) ? 10 : -1; // 1024x5 + + localparam WRITE_ADDR_WIDTH = + (WRITE_WIDTH == 16) ? 8 : // 256x16 + (WRITE_WIDTH == 8) ? 9 : // 512x8 + (WRITE_WIDTH == 4) ? 10 : // 1024x4 + (WRITE_WIDTH == 2) ? 11 : // 2048x2 + (WRITE_WIDTH == 1) ? 12 : // 4096x1 + (WRITE_WIDTH == 20) ? 8 : // 256x20 + (WRITE_WIDTH == 10) ? 9 : // 512x10 + (WRITE_WIDTH == 5) ? 10 : -1; // 1024x5 + +endmodule \ No newline at end of file diff --git a/techlibs/efinix/efinix_determine_init.cc b/techlibs/efinix/efinix_determine_init.cc new file mode 100644 index 000000000..54da703ff --- /dev/null +++ b/techlibs/efinix/efinix_determine_init.cc @@ -0,0 +1,89 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2018 Icenowy Zheng + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct EfinixDetermineInitPass : public Pass { + EfinixDetermineInitPass() : Pass("efinix_determine_init", "Efinix: Determine the init value of cells") { } + void help() YS_OVERRIDE + { + log("\n"); + log(" efinix_determine_init [selection]\n"); + log("\n"); + log("Determine the init value of cells that doesn't allow unknown init value.\n"); + log("\n"); + } + + Const determine_init(Const init) + { + for (int i = 0; i < GetSize(init); i++) { + if (init[i] != State::S0 && init[i] != State::S1) + init[i] = State::S0; + } + + return init; + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing EFINIX_DETERMINE_INIT pass (determine init value for cells).\n"); + + extra_args(args, args.size(), design); + + int cnt = 0; + for (auto module : design->selected_modules()) + { + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\EFX_RAM_5K") + { + cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0"))); + cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1"))); + cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2"))); + cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3"))); + cell->setParam("\\INIT_4", determine_init(cell->getParam("\\INIT_4"))); + cell->setParam("\\INIT_5", determine_init(cell->getParam("\\INIT_5"))); + cell->setParam("\\INIT_6", determine_init(cell->getParam("\\INIT_6"))); + cell->setParam("\\INIT_7", determine_init(cell->getParam("\\INIT_7"))); + cell->setParam("\\INIT_8", determine_init(cell->getParam("\\INIT_8"))); + cell->setParam("\\INIT_9", determine_init(cell->getParam("\\INIT_9"))); + cell->setParam("\\INIT_A", determine_init(cell->getParam("\\INIT_A"))); + cell->setParam("\\INIT_B", determine_init(cell->getParam("\\INIT_B"))); + cell->setParam("\\INIT_C", determine_init(cell->getParam("\\INIT_C"))); + cell->setParam("\\INIT_D", determine_init(cell->getParam("\\INIT_D"))); + cell->setParam("\\INIT_E", determine_init(cell->getParam("\\INIT_E"))); + cell->setParam("\\INIT_F", determine_init(cell->getParam("\\INIT_F"))); + cell->setParam("\\INIT_10", determine_init(cell->getParam("\\INIT_10"))); + cell->setParam("\\INIT_11", determine_init(cell->getParam("\\INIT_11"))); + cell->setParam("\\INIT_12", determine_init(cell->getParam("\\INIT_12"))); + cell->setParam("\\INIT_13", determine_init(cell->getParam("\\INIT_13"))); + + cnt++; + } + } + } + log_header(design, "Updated %d cells with determined init value.\n", cnt); + } +} EfinixDetermineInitPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 3f17bafa3..000a17310 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -150,6 +150,13 @@ struct SynthEfinixPass : public ScriptPass run("synth -run coarse"); } + if (check_label("map_bram", "(skip if -nobram)")) + { + run("memory_bram -rules +/efinix/bram.txt"); + run("techmap -map +/efinix/brams_map.v"); + run("efinix_determine_init"); + } + if (check_label("fine")) { run("opt -fast -mux_undef -undriven -fine"); -- cgit v1.2.3 From 8a3329871ba7bab98982a101327b8375cd73344d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 4 Aug 2019 12:17:55 +0200 Subject: clock for ram trough gbuf --- techlibs/efinix/efinix_gbuf.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'techlibs') diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc index 50f84c30c..e75fb3f4d 100644 --- a/techlibs/efinix/efinix_gbuf.cc +++ b/techlibs/efinix/efinix_gbuf.cc @@ -38,6 +38,12 @@ static void handle_gbufs(Module *module) for (auto bit : sigmap(cell->getPort("\\CLK"))) clk_bits.insert(bit); } + if (cell->type == "\\EFX_RAM_5K") { + for (auto bit : sigmap(cell->getPort("\\RCLK"))) + clk_bits.insert(bit); + for (auto bit : sigmap(cell->getPort("\\WCLK"))) + clk_bits.insert(bit); + } } for (auto wire : vector(module->wires())) -- cgit v1.2.3 From 7de098ad4521a78ca109f261a53d50846f8f5667 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 5 Aug 2019 10:41:35 -0700 Subject: techlibs/intel: Clean up Makefile Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky --- techlibs/intel/Makefile.inc | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) (limited to 'techlibs') diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 7a3d2c71a..4e8f423c8 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -5,20 +5,10 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) -$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) -$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) -$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) -$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v)) -$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v)) -$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v)) -$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v)) -$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v)) -$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v)) -$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v)) -$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v)) -$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v)) -#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v)) -#$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/arith_map.v)) -#$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/arith_map.v)) + +# Add the cell models and mappings for the VQM backend +families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive +$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) +$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) -- cgit v1.2.3 From d51b135e331326032b003934905c17750e116014 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 9 Aug 2019 12:37:10 +0200 Subject: Fix CO --- techlibs/efinix/arith_map.v | 50 ++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 26 deletions(-) (limited to 'techlibs') diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index ae955663c..ef903171f 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -31,7 +31,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); output [Y_WIDTH-1:0] X, Y; input CI, BI; - output CO; + output [Y_WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; @@ -41,38 +41,36 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+2:0] C = {COx, CI}; + wire [Y_WIDTH:0] C; - EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) - adder_cin ( - .I0(C[0]), + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + adder_cin ( + .I0(CI), .I1(1'b1), .CI(1'b0), - .CO(COx[0]) + .CO(C[0]) ); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) - adder_i ( - .I0(AA[i]), - .I1(BB[i]), - .CI(C[i+1]), - .O(Y[i]), - .CO(COx[i+1]) - ); - end: slice + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + adder_i ( + .I0(AA[i]), + .I1(BB[i]), + .CI(C[i]), + .O(Y[i]), + .CO(C[i+1]) + ); + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + adder_cout ( + .I0(1'b0), + .I1(1'b0), + .CI(C[i+1]), + .O(CO[i]) + ); + end: slice endgenerate - EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) - adder_cout ( - .I0(1'b0), - .I1(1'b0), - .CI(C[Y_WIDTH+1]), - .O(COx[Y_WIDTH+1]) - ); - assign CO = COx[Y_WIDTH+1]; - /* End implementation */ - assign X = AA ^ BB; + /* End implementation */ + assign X = AA ^ BB; endmodule \ No newline at end of file -- cgit v1.2.3 From b3a91d6508943c8e5656af0a624e6ad115aec9c3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 08:37:56 +0200 Subject: cleanup --- techlibs/efinix/arith_map.v | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index ef903171f..56e1b039f 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -32,6 +32,9 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; + + wire CIx; + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; @@ -41,14 +44,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - wire [Y_WIDTH:0] C; + wire [Y_WIDTH-1:0] C = { COx, CIx }; EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) adder_cin ( .I0(CI), .I1(1'b1), .CI(1'b0), - .CO(C[0]) + .CO(CIx) ); genvar i; @@ -59,13 +62,13 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); .I1(BB[i]), .CI(C[i]), .O(Y[i]), - .CO(C[i+1]) + .CO(COx[i]) ); EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) adder_cout ( .I0(1'b0), .I1(1'b0), - .CI(C[i+1]), + .CI(COx[i]), .O(CO[i]) ); end: slice -- cgit v1.2.3 From 8c8100e0df51401870fba13fccf5240461f76051 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 10:17:49 +0200 Subject: Adding new pass to fix carry chain --- techlibs/efinix/Makefile.inc | 1 + techlibs/efinix/efinix_fixcarry.cc | 122 +++++++++++++++++++++++++++++++++++++ techlibs/efinix/synth_efinix.cc | 1 + 3 files changed, 124 insertions(+) create mode 100644 techlibs/efinix/efinix_fixcarry.cc (limited to 'techlibs') diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index d0593baec..47dadccdd 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -2,6 +2,7 @@ OBJS += techlibs/efinix/synth_efinix.o OBJS += techlibs/efinix/efinix_gbuf.o OBJS += techlibs/efinix/efinix_determine_init.o +OBJS += techlibs/efinix/efinix_fixcarry.o $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc new file mode 100644 index 000000000..b7cd995b8 --- /dev/null +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -0,0 +1,122 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2019 Miodrag Milanovic + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +static SigBit get_bit_or_zero(const SigSpec &sig) +{ + if (GetSize(sig) == 0) + return State::S0; + return sig[0]; +} + +static void fix_carry_chain(Module *module) +{ + SigMap sigmap(module); + + pool ci_bits; + dict mapping_bits; + + for (auto cell : module->cells()) + { + if (cell->type == "\\EFX_ADD") { + SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0")); + SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1")); + if (bit_i0 == State::S0 && bit_i1== State::S0) { + SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI")); + SigBit bit_o = sigmap(cell->getPort("\\O")); + ci_bits.insert(bit_ci); + mapping_bits[bit_ci] = bit_o; + } + } + } + + vector adders_to_fix_cells; + for (auto cell : module->cells()) + { + if (cell->type == "\\EFX_ADD") { + SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI")); + SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0")); + SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1")); + SigBit canonical_bit = sigmap(bit_ci); + if (!ci_bits.count(canonical_bit)) + continue; + if (bit_i0 == State::S0 && bit_i1== State::S0) + continue; + + adders_to_fix_cells.push_back(cell); + log("Found %s cell named %s with invalid CI signal.\n", log_id(cell->type), log_id(cell)); + } + } + + for (auto cell : adders_to_fix_cells) + { + SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI")); + SigBit canonical_bit = sigmap(bit_ci); + auto bit = mapping_bits.at(canonical_bit); + log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell)); + Cell *c = module->addCell(NEW_ID, "\\EFX_ADD"); + SigBit new_bit = module->addWire(NEW_ID); + c->setParam("\\I0_POLARITY", State::S1); + c->setParam("\\I1_POLARITY", State::S1); + c->setPort("\\I0", bit); + c->setPort("\\I1", State::S1); + c->setPort("\\CI", State::S0); + c->setPort("\\CO", new_bit); + + cell->setPort("\\CI", new_bit); + } +} + +struct EfinixCarryFixPass : public Pass { + EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" efinix_fixcarry [options] [selection]\n"); + log("\n"); + log("Add Efinix adders to fix carry chain if needed.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + Module *module = design->top_module(); + + if (module == nullptr) + log_cmd_error("No top module found.\n"); + + fix_carry_chain(module); + } +} EfinixCarryFixPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 000a17310..d64491ca8 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -191,6 +191,7 @@ struct SynthEfinixPass : public ScriptPass if (check_label("map_gbuf")) { run("efinix_gbuf"); + run("efinix_fixcarry"); run("clean"); } -- cgit v1.2.3 From e609537e386535047f045bf0b8df7ebc5f23c469 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 10:46:48 +0200 Subject: Fixed data width --- techlibs/efinix/brams_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v index 9ef01d026..3236f39a5 100644 --- a/techlibs/efinix/brams_map.v +++ b/techlibs/efinix/brams_map.v @@ -22,8 +22,8 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"; EFX_RAM_5K #( - .READ_WIDTH(20), - .WRITE_WIDTH(20), + .READ_WIDTH(CFG_DBITS), + .WRITE_WIDTH(CFG_DBITS), .OUTPUT_REG(1'b0), .RCLK_POLARITY(1'b1), .RE_POLARITY(1'b1), -- cgit v1.2.3 From 853c755a0ca67ae0a75b5cf7783e395d9f49f389 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 11:01:46 +0200 Subject: Replaced custom step with setundef --- techlibs/efinix/Makefile.inc | 1 - techlibs/efinix/efinix_determine_init.cc | 89 -------------------------------- techlibs/efinix/synth_efinix.cc | 2 +- 3 files changed, 1 insertion(+), 91 deletions(-) delete mode 100644 techlibs/efinix/efinix_determine_init.cc (limited to 'techlibs') diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 47dadccdd..f1ce58276 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -1,7 +1,6 @@ OBJS += techlibs/efinix/synth_efinix.o OBJS += techlibs/efinix/efinix_gbuf.o -OBJS += techlibs/efinix/efinix_determine_init.o OBJS += techlibs/efinix/efinix_fixcarry.o $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) diff --git a/techlibs/efinix/efinix_determine_init.cc b/techlibs/efinix/efinix_determine_init.cc deleted file mode 100644 index 54da703ff..000000000 --- a/techlibs/efinix/efinix_determine_init.cc +++ /dev/null @@ -1,89 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2018 Icenowy Zheng - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct EfinixDetermineInitPass : public Pass { - EfinixDetermineInitPass() : Pass("efinix_determine_init", "Efinix: Determine the init value of cells") { } - void help() YS_OVERRIDE - { - log("\n"); - log(" efinix_determine_init [selection]\n"); - log("\n"); - log("Determine the init value of cells that doesn't allow unknown init value.\n"); - log("\n"); - } - - Const determine_init(Const init) - { - for (int i = 0; i < GetSize(init); i++) { - if (init[i] != State::S0 && init[i] != State::S1) - init[i] = State::S0; - } - - return init; - } - - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing EFINIX_DETERMINE_INIT pass (determine init value for cells).\n"); - - extra_args(args, args.size(), design); - - int cnt = 0; - for (auto module : design->selected_modules()) - { - for (auto cell : module->selected_cells()) - { - if (cell->type == "\\EFX_RAM_5K") - { - cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0"))); - cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1"))); - cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2"))); - cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3"))); - cell->setParam("\\INIT_4", determine_init(cell->getParam("\\INIT_4"))); - cell->setParam("\\INIT_5", determine_init(cell->getParam("\\INIT_5"))); - cell->setParam("\\INIT_6", determine_init(cell->getParam("\\INIT_6"))); - cell->setParam("\\INIT_7", determine_init(cell->getParam("\\INIT_7"))); - cell->setParam("\\INIT_8", determine_init(cell->getParam("\\INIT_8"))); - cell->setParam("\\INIT_9", determine_init(cell->getParam("\\INIT_9"))); - cell->setParam("\\INIT_A", determine_init(cell->getParam("\\INIT_A"))); - cell->setParam("\\INIT_B", determine_init(cell->getParam("\\INIT_B"))); - cell->setParam("\\INIT_C", determine_init(cell->getParam("\\INIT_C"))); - cell->setParam("\\INIT_D", determine_init(cell->getParam("\\INIT_D"))); - cell->setParam("\\INIT_E", determine_init(cell->getParam("\\INIT_E"))); - cell->setParam("\\INIT_F", determine_init(cell->getParam("\\INIT_F"))); - cell->setParam("\\INIT_10", determine_init(cell->getParam("\\INIT_10"))); - cell->setParam("\\INIT_11", determine_init(cell->getParam("\\INIT_11"))); - cell->setParam("\\INIT_12", determine_init(cell->getParam("\\INIT_12"))); - cell->setParam("\\INIT_13", determine_init(cell->getParam("\\INIT_13"))); - - cnt++; - } - } - } - log_header(design, "Updated %d cells with determined init value.\n", cnt); - } -} EfinixDetermineInitPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index d64491ca8..26a8d4eda 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -154,7 +154,7 @@ struct SynthEfinixPass : public ScriptPass { run("memory_bram -rules +/efinix/bram.txt"); run("techmap -map +/efinix/brams_map.v"); - run("efinix_determine_init"); + run("setundef -zero -params t:EFX_RAM_5K"); } if (check_label("fine")) -- cgit v1.2.3 From aa0c37722a99a308e64ea9581111adea2d97e46d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 11:40:15 +0200 Subject: fix mixing signals on FF mapping --- techlibs/efinix/cells_map.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v index 70c19635e..0aeab1902 100644 --- a/techlibs/efinix/cells_map.v +++ b/techlibs/efinix/cells_map.v @@ -8,14 +8,14 @@ module \$_DFFE_PN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE module \$_DFFE_PP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule module \$_DFF_NN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule module \$_DFF_PN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule module \$_DFF_NP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule `ifndef NO_LUT module \$lut (A, Y); -- cgit v1.2.3 From ead2b52b5a123e2c93578555de394a7a406e1fa5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 13:59:39 +0200 Subject: one bit enable signal --- techlibs/efinix/brams_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v index 3236f39a5..6786ae769 100644 --- a/techlibs/efinix/brams_map.v +++ b/techlibs/efinix/brams_map.v @@ -1,7 +1,7 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 8; parameter CFG_DBITS = 20; - parameter CFG_ENABLE_A = 2; + parameter CFG_ENABLE_A = 1; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; -- cgit v1.2.3 From 2897fe4d09118e37934b7e76f4990cc1d69a0cb5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Aug 2019 17:05:24 +0200 Subject: Fix formating --- techlibs/efinix/arith_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 56e1b039f..178f57bc5 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -33,8 +33,8 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire CIx; - wire [Y_WIDTH-1:0] COx; + wire CIx; + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; -- cgit v1.2.3 From 5f561bdcb1d562d6f975b4a27beca1b8b7af908f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 12 Aug 2019 20:19:54 +0200 Subject: Proper arith for Anlogic and use standard pass --- techlibs/anlogic/Makefile.inc | 2 +- techlibs/anlogic/anlogic_determine_init.cc | 72 ---------------- techlibs/anlogic/anlogic_fixcarry.cc | 130 +++++++++++++++++++++++++++++ techlibs/anlogic/arith_map.v | 42 ++++++---- techlibs/anlogic/synth_anlogic.cc | 7 +- 5 files changed, 162 insertions(+), 91 deletions(-) delete mode 100644 techlibs/anlogic/anlogic_determine_init.cc create mode 100644 techlibs/anlogic/anlogic_fixcarry.cc (limited to 'techlibs') diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 67cf9cf10..9426b5ca5 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -1,7 +1,7 @@ OBJS += techlibs/anlogic/synth_anlogic.o OBJS += techlibs/anlogic/anlogic_eqn.o -OBJS += techlibs/anlogic/anlogic_determine_init.o +OBJS += techlibs/anlogic/anlogic_fixcarry.o $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc deleted file mode 100644 index c4089dac2..000000000 --- a/techlibs/anlogic/anlogic_determine_init.cc +++ /dev/null @@ -1,72 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2018 Icenowy Zheng - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct AnlogicDetermineInitPass : public Pass { - AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { } - void help() YS_OVERRIDE - { - log("\n"); - log(" anlogic_determine_init [selection]\n"); - log("\n"); - log("Determine the init value of cells that doesn't allow unknown init value.\n"); - log("\n"); - } - - Const determine_init(Const init) - { - for (int i = 0; i < GetSize(init); i++) { - if (init[i] != State::S0 && init[i] != State::S1) - init[i] = State::S0; - } - - return init; - } - - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n"); - - extra_args(args, args.size(), design); - - int cnt = 0; - for (auto module : design->selected_modules()) - { - for (auto cell : module->selected_cells()) - { - if (cell->type == "\\EG_LOGIC_DRAM16X4") - { - cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0"))); - cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1"))); - cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2"))); - cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3"))); - cnt++; - } - } - } - log_header(design, "Updated %d cells with determined init value.\n", cnt); - } -} AnlogicDetermineInitPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc new file mode 100644 index 000000000..87164d375 --- /dev/null +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -0,0 +1,130 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2019 Miodrag Milanovic + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +static SigBit get_bit_or_zero(const SigSpec &sig) +{ + if (GetSize(sig) == 0) + return State::S0; + return sig[0]; +} + +static void fix_carry_chain(Module *module) +{ + SigMap sigmap(module); + + pool ci_bits; + dict mapping_bits; + + for (auto cell : module->cells()) + { + if (cell->type == "\\AL_MAP_ADDER") { + if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue; + SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a")); + SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b")); + if (bit_i0 == State::S0 && bit_i1== State::S0) { + SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c")); + SigSpec o = cell->getPort("\\o"); + if (GetSize(o) == 2) { + SigBit bit_o = o[0]; + ci_bits.insert(bit_ci); + mapping_bits[bit_ci] = bit_o; + } + } + } + } + vector adders_to_fix_cells; + for (auto cell : module->cells()) + { + if (cell->type == "\\AL_MAP_ADDER") { + if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue; + SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c")); + SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a")); + SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b")); + SigBit canonical_bit = sigmap(bit_ci); + if (!ci_bits.count(canonical_bit)) + continue; + if (bit_i0 == State::S0 && bit_i1== State::S0) + continue; + + adders_to_fix_cells.push_back(cell); + log("Found %s cell named %s with invalid 'c' signal.\n", log_id(cell->type), log_id(cell)); + } + } + + for (auto cell : adders_to_fix_cells) + { + SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c")); + SigBit canonical_bit = sigmap(bit_ci); + auto bit = mapping_bits.at(canonical_bit); + log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell)); + Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER"); + SigBit new_bit = module->addWire(NEW_ID); + SigBit dummy_bit = module->addWire(NEW_ID); + SigSpec bits; + bits.append(dummy_bit); + bits.append(new_bit); + c->setParam("\\ALUTYPE", Const("ADD_CARRY")); + c->setPort("\\a", bit); + c->setPort("\\b", State::S0); + c->setPort("\\c", State::S0); + c->setPort("\\o", bits); + + cell->setPort("\\c", new_bit); + } + +} + +struct AnlogicCarryFixPass : public Pass { + AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" anlogic_fixcarry [options] [selection]\n"); + log("\n"); + log("Add Anlogic adders to fix carry chain if needed.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + Module *module = design->top_module(); + + if (module == nullptr) + log_cmd_error("No top module found.\n"); + + fix_carry_chain(module); + } +} AnlogicCarryFixPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index 6d6a7ca37..d783b0212 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -31,7 +31,10 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); output [Y_WIDTH-1:0] X, Y; input CI, BI; - output CO; + output [Y_WIDTH-1:0] CO; + + wire CIx; + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; @@ -41,15 +44,16 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+2:0] C = {COx, CI}; + wire [Y_WIDTH-1:0] C = { COx, CIx }; wire dummy; AL_MAP_ADDER #( .ALUTYPE("ADD_CARRY")) adder_cin ( - .a(C[0]), - .o({COx[0], dummy}) + .a(CI), + .b(1'b0), + .c(1'b0), + .o({CIx, dummy}) ); genvar i; @@ -59,18 +63,22 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); ) adder_i ( .a(AA[i]), .b(BB[i]), - .c(C[i+1]), - .o({COx[i+1],Y[i]}) + .c(C[i]), + .o({COx[i],Y[i]}) ); - end: slice + + wire cout; + AL_MAP_ADDER #( + .ALUTYPE("ADD")) + adder_cout ( + .a(1'b0), + .b(1'b0), + .c(COx[i]), + .o({cout, CO[i]}) + ); + end: slice endgenerate - /* End implementation */ - AL_MAP_ADDER #( - .ALUTYPE("ADD")) - adder_cout ( - .c(C[Y_WIDTH+1]), - .o(COx[Y_WIDTH+1]) - ); - assign CO = COx[Y_WIDTH+1]; - assign X = AA ^ BB; + + /* End implementation */ + assign X = AA ^ BB; endmodule \ No newline at end of file diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 620bf3965..b87fc8566 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); - run("anlogic_determine_init"); + run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } if (check_label("fine")) @@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass { run("techmap -map +/anlogic/cells_map.v"); run("clean"); + } + + if (check_label("map_anlogic")) + { + run("anlogic_fixcarry"); run("anlogic_eqn"); } -- cgit v1.2.3 From 12c692f6eda7367527fde2a8aad49447a73aa643 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 12 Aug 2019 12:06:45 -0700 Subject: Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. --- techlibs/ice40/Makefile.inc | 1 - techlibs/ice40/arith_map.v | 30 +++-------- techlibs/ice40/cells_map.v | 23 ++++---- techlibs/ice40/ice40_unlut.cc | 106 ------------------------------------- techlibs/ice40/synth_ice40.cc | 13 ++--- techlibs/ice40/tests/test_arith.ys | 9 +++- 6 files changed, 32 insertions(+), 150 deletions(-) delete mode 100644 techlibs/ice40/ice40_unlut.cc (limited to 'techlibs') diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index d258d5a5d..76a89b107 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -4,7 +4,6 @@ OBJS += techlibs/ice40/ice40_braminit.o OBJS += techlibs/ice40/ice40_ffssr.o OBJS += techlibs/ice40/ice40_ffinit.o OBJS += techlibs/ice40/ice40_opt.o -OBJS += techlibs/ice40/ice40_unlut.o GENFILES += techlibs/ice40/brams_init1.vh GENFILES += techlibs/ice40/brams_init2.vh diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index fe83a8e38..26b24db9e 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -44,35 +44,21 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice -`ifdef _ABC - \$__ICE40_FULL_ADDER carry ( + \$__ICE40_CARRY_WRAPPER #( + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(16'b 0110_1001_1001_0110) + ) fadd ( .A(AA[i]), .B(BB[i]), .CI(C[i]), - .CO(CO[i]), - .O(Y[i]) - ); -`else - SB_CARRY carry ( - .I0(AA[i]), - .I1(BB[i]), - .CI(C[i]), - .CO(CO[i]) - ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) - ) adder ( .I0(1'b0), - .I1(AA[i]), - .I2(BB[i]), .I3(C[i]), + .CO(CO[i]), .O(Y[i]) ); -`endif end endgenerate assign X = AA ^ BB; diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index b4b831165..0c10c9ac4 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -62,26 +62,21 @@ module \$lut (A, Y); endmodule `endif -`ifdef _ABC -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +`ifndef NO_ADDER +module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); + parameter LUT = 0; SB_CARRY carry ( .I0(A), .I1(B), .CI(CI), .CO(CO) ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) - ) adder ( - .I0(1'b0), - .I1(A), - .I2(B), - .I3(CI), - .O(O) + \$lut #( + .WIDTH(4), + .LUT(LUT) + ) lut ( + .A({I3,B,A,I0}), + .Y(O) ); endmodule `endif diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc deleted file mode 100644 index f3f70ac1f..000000000 --- a/techlibs/ice40/ice40_unlut.cc +++ /dev/null @@ -1,106 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include -#include - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -static SigBit get_bit_or_zero(const SigSpec &sig) -{ - if (GetSize(sig) == 0) - return State::S0; - return sig[0]; -} - -static void run_ice40_unlut(Module *module) -{ - SigMap sigmap(module); - - for (auto cell : module->selected_cells()) - { - if (cell->type == "\\SB_LUT4") - { - SigSpec inbits; - - inbits.append(get_bit_or_zero(cell->getPort("\\I0"))); - inbits.append(get_bit_or_zero(cell->getPort("\\I1"))); - inbits.append(get_bit_or_zero(cell->getPort("\\I2"))); - inbits.append(get_bit_or_zero(cell->getPort("\\I3"))); - sigmap.apply(inbits); - - log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell)); - - cell->type ="$lut"; - cell->setParam("\\WIDTH", 4); - cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); - cell->unsetParam("\\LUT_INIT"); - - cell->setPort("\\A", SigSpec({ - get_bit_or_zero(cell->getPort("\\I0")), - get_bit_or_zero(cell->getPort("\\I1")), - get_bit_or_zero(cell->getPort("\\I2")), - get_bit_or_zero(cell->getPort("\\I3")) - })); - cell->setPort("\\Y", cell->getPort("\\O")[0]); - cell->unsetPort("\\I0"); - cell->unsetPort("\\I1"); - cell->unsetPort("\\I2"); - cell->unsetPort("\\I3"); - cell->unsetPort("\\O"); - - cell->check(); - } - } -} - -struct Ice40UnlutPass : public Pass { - Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { } - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" ice40_unlut [options] [selection]\n"); - log("\n"); - log("This command transforms all SB_LUT4 cells to generic $lut cells.\n"); - log("\n"); - } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n"); - log_push(); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-???") { - // continue; - // } - break; - } - extra_args(args, argidx, design); - - for (auto module : design->selected_modules()) - run_ice40_unlut(module); - } -} Ice40UnlutPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index dc04eed67..c6de81bd9 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v"); + run("read_verilog -icells -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); run("proc"); } @@ -293,8 +293,10 @@ struct SynthIce40Pass : public ScriptPass { if (nocarry) run("techmap"); - else - run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : "")); + else { + run("ice40_wrapcarry"); + run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); + } if (retime || help_mode) run(abc + " -dff", "(only if -retime)"); run("ice40_opt"); @@ -309,7 +311,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_merge"); run(stringf("dff2dffe -unmap-mince %d", min_ce_use)); } - run("techmap -D NO_LUT -map +/ice40/cells_map.v"); + run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); run("ice40_ffinit"); @@ -338,13 +340,12 @@ struct SynthIce40Pass : public ScriptPass else wire_delay = 250; run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); - run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); } + run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("clean"); - run("ice40_unlut"); run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); } diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,11 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter -- cgit v1.2.3 From 8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 12 Aug 2019 12:19:25 -0700 Subject: Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER --- techlibs/ice40/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 0c10c9ac4..662423f0a 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); .WIDTH(4), .LUT(LUT) ) lut ( - .A({I3,B,A,I0}), + .A({I0,A,B,I3}), .Y(O) ); endmodule -- cgit v1.2.3 From f4c62f33ac56bc5725c44ad822e75d2387f98061 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 12 Aug 2019 15:57:43 +0000 Subject: Add clock buffer insertion pass, improve iopadmap. A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. --- techlibs/xilinx/cells_sim.v | 16 +++++ techlibs/xilinx/cells_xtra.sh | 144 +++++++++++++++++++++------------------- techlibs/xilinx/cells_xtra.v | 90 ++++++++++++++++++++++++- techlibs/xilinx/synth_xilinx.cc | 37 ++++++++++- techlibs/xilinx/xc6s_brams_bb.v | 2 + techlibs/xilinx/xc7_brams_bb.v | 2 + 6 files changed, 220 insertions(+), 71 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 05e46b4e7..d5815ca77 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -42,10 +42,12 @@ module OBUF(output O, input I); assign O = I; endmodule +(* clkbuf_driver = "O" *) module BUFG(output O, input I); assign O = I; endmodule +(* clkbuf_driver = "O" *) module BUFGCTRL( output O, input I0, input I1, @@ -72,6 +74,7 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT); endmodule +(* clkbuf_driver = "O" *) module BUFHCE(output O, input I, input CE); parameter [0:0] INIT_OUT = 1'b0; @@ -213,6 +216,7 @@ endmodule `endif +(* clkbuf_sink = "C" *) module FDRE (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -225,6 +229,7 @@ module FDRE (output reg Q, input C, CE, D, R); endcase endgenerate endmodule +(* clkbuf_sink = "C" *) module FDSE (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -237,6 +242,7 @@ module FDSE (output reg Q, input C, CE, D, S); endcase endgenerate endmodule +(* clkbuf_sink = "C" *) module FDCE (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -251,6 +257,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); endcase endgenerate endmodule +(* clkbuf_sink = "C" *) module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; @@ -265,30 +272,35 @@ module FDPE (output reg Q, input C, CE, D, PRE); endcase endgenerate endmodule +(* clkbuf_sink = "C" *) module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; endmodule +(* clkbuf_sink = "C" *) module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; endmodule +(* clkbuf_sink = "C" *) module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule +(* clkbuf_sink = "C" *) module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* clkbuf_sink = "WCLK" *) (* abc_box_id = 5, abc_scc_break="D,WE" *) module RAM32X1D ( output DPO, SPO, @@ -307,6 +319,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +(* clkbuf_sink = "WCLK" *) (* abc_box_id = 6, abc_scc_break="D,WE" *) module RAM64X1D ( output DPO, SPO, @@ -325,6 +338,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +(* clkbuf_sink = "WCLK" *) (* abc_box_id = 7, abc_scc_break="D,WE" *) module RAM128X1D ( output DPO, SPO, @@ -340,6 +354,7 @@ module RAM128X1D ( always @(posedge clk) if (WE) mem[A] <= D; endmodule +(* clkbuf_sink = "CLK" *) module SRL16E ( output Q, input A0, A1, A2, A3, CE, CLK, D @@ -358,6 +373,7 @@ module SRL16E ( endgenerate endmodule +(* clkbuf_sink = "CLK" *) module SRLC32E ( output Q, output Q31, diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index 53b528820..3291e46a8 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -1,7 +1,12 @@ #!/bin/bash set -e -libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src" +if [ -z "$1" ] +then + libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src" +else + libdir=$1 +fi function xtract_cell_decl() { @@ -24,33 +29,33 @@ function xtract_cell_decl() echo # Design elements types listed in Xilinx UG953 - xtract_cell_decl BSCANE2 - # xtract_cell_decl BUFG - xtract_cell_decl BUFGCE - xtract_cell_decl BUFGCE_1 - #xtract_cell_decl BUFGCTRL - xtract_cell_decl BUFGMUX - xtract_cell_decl BUFGMUX_1 - xtract_cell_decl BUFGMUX_CTRL - xtract_cell_decl BUFH - #xtract_cell_decl BUFHCE - xtract_cell_decl BUFIO - xtract_cell_decl BUFMR - xtract_cell_decl BUFMRCE - xtract_cell_decl BUFR + xtract_cell_decl BSCANE2 "(* keep *)" + # xtract_cell_decl BUFG "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFGCE "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFGCE_1 "(* clkbuf_driver = \"O\" *)" + #xtract_cell_decl BUFGCTRL "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFGMUX "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFGMUX_1 "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFGMUX_CTRL "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFH "(* clkbuf_driver = \"O\" *)" + #xtract_cell_decl BUFHCE "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFIO "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFMR "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFMRCE "(* clkbuf_driver = \"O\" *)" + xtract_cell_decl BUFR "(* clkbuf_driver = \"O\" *)" xtract_cell_decl CAPTUREE2 "(* keep *)" # xtract_cell_decl CARRY4 - xtract_cell_decl CFGLUT5 + xtract_cell_decl CFGLUT5 "(* clkbuf_sink = \"CLK\" *)" xtract_cell_decl DCIRESET "(* keep *)" xtract_cell_decl DNA_PORT - xtract_cell_decl DSP48E1 + xtract_cell_decl DSP48E1 "(* clkbuf_sink = \"CLK\" *)" xtract_cell_decl EFUSE_USR # xtract_cell_decl FDCE # xtract_cell_decl FDPE # xtract_cell_decl FDRE # xtract_cell_decl FDSE - xtract_cell_decl FIFO18E1 - xtract_cell_decl FIFO36E1 + xtract_cell_decl FIFO18E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" + xtract_cell_decl FIFO36E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" xtract_cell_decl FRAME_ECCE2 xtract_cell_decl GTHE2_CHANNEL xtract_cell_decl GTHE2_COMMON @@ -58,31 +63,34 @@ function xtract_cell_decl() xtract_cell_decl GTPE2_COMMON xtract_cell_decl GTXE2_CHANNEL xtract_cell_decl GTXE2_COMMON - # xtract_cell_decl IBUF - xtract_cell_decl IBUF_IBUFDISABLE - xtract_cell_decl IBUF_INTERMDISABLE - xtract_cell_decl IBUFDS - xtract_cell_decl IBUFDS_DIFF_OUT - xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE - xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE - xtract_cell_decl IBUFDS_GTE2 - xtract_cell_decl IBUFDS_IBUFDISABLE - xtract_cell_decl IBUFDS_INTERMDISABLE + # xtract_cell_decl IBUF "(* iopad_external_pin = \"I\" *)" + xtract_cell_decl IBUF_IBUFDISABLE "(* iopad_external_pin = \"I\" *)" + xtract_cell_decl IBUF_INTERMDISABLE "(* iopad_external_pin = \"I\" *)" + xtract_cell_decl IBUFDS "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFDS_GTE2 "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFDS_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFDS_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFG "(* iopad_external_pin = \"I\" *)" + xtract_cell_decl IBUFGDS "(* iopad_external_pin = \"I,IB\" *)" + xtract_cell_decl IBUFGDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)" xtract_cell_decl ICAPE2 "(* keep *)" - xtract_cell_decl IDDR - xtract_cell_decl IDDR_2CLK - xtract_cell_decl IDELAYCTRL "(* keep *)" - xtract_cell_decl IDELAYE2 - xtract_cell_decl IN_FIFO - xtract_cell_decl IOBUF - xtract_cell_decl IOBUF_DCIEN - xtract_cell_decl IOBUF_INTERMDISABLE - xtract_cell_decl IOBUFDS - xtract_cell_decl IOBUFDS_DCIEN - xtract_cell_decl IOBUFDS_DIFF_OUT - xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN - xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE - xtract_cell_decl ISERDESE2 + xtract_cell_decl IDDR "(* clkbuf_sink = \"C\" *)" + xtract_cell_decl IDDR_2CLK "(* clkbuf_sink = \"C,CB\" *)" + xtract_cell_decl IDELAYCTRL "(* keep *) (* clkbuf_sink = \"REFCLK\" *)" + xtract_cell_decl IDELAYE2 "(* clkbuf_sink = \"C\" *)" + xtract_cell_decl IN_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" + xtract_cell_decl IOBUF "(* iopad_external_pin = \"IO\" *)" + xtract_cell_decl IOBUF_DCIEN "(* iopad_external_pin = \"IO\" *)" + xtract_cell_decl IOBUF_INTERMDISABLE "(* iopad_external_pin = \"IO\" *)" + xtract_cell_decl IOBUFDS "(* iopad_external_pin = \"IO\" *)" + xtract_cell_decl IOBUFDS_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)" + xtract_cell_decl IOBUFDS_DIFF_OUT "(* iopad_external_pin = \"IO,IOB\" *)" + xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)" + xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"IO,IOB\" *)" + xtract_cell_decl ISERDESE2 "(* clkbuf_sink = \"CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB\" *)" xtract_cell_decl KEEPER xtract_cell_decl LDCE xtract_cell_decl LDPE @@ -97,14 +105,14 @@ function xtract_cell_decl() xtract_cell_decl MMCME2_BASE # xtract_cell_decl MUXF7 # xtract_cell_decl MUXF8 - # xtract_cell_decl OBUF - xtract_cell_decl OBUFDS - xtract_cell_decl OBUFT - xtract_cell_decl OBUFTDS - xtract_cell_decl ODDR - xtract_cell_decl ODELAYE2 - xtract_cell_decl OSERDESE2 - xtract_cell_decl OUT_FIFO + # xtract_cell_decl OBUF "(* iopad_external_pin = \"O\" *)" + xtract_cell_decl OBUFDS "(* iopad_external_pin = \"O,OB\" *)" + xtract_cell_decl OBUFT "(* iopad_external_pin = \"O\" *)" + xtract_cell_decl OBUFTDS "(* iopad_external_pin = \"O,OB\" *)" + xtract_cell_decl ODDR "(* clkbuf_sink = \"C\" *)" + xtract_cell_decl ODELAYE2 "(* clkbuf_sink = \"C\" *)" + xtract_cell_decl OSERDESE2 "(* clkbuf_sink = \"CLK,CLKDIV\" *)" + xtract_cell_decl OUT_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" xtract_cell_decl PHASER_IN xtract_cell_decl PHASER_IN_PHY xtract_cell_decl PHASER_OUT @@ -116,27 +124,27 @@ function xtract_cell_decl() xtract_cell_decl PS7 "(* keep *)" xtract_cell_decl PULLDOWN xtract_cell_decl PULLUP - #xtract_cell_decl RAM128X1D - xtract_cell_decl RAM128X1S - xtract_cell_decl RAM256X1S - xtract_cell_decl RAM32M - #xtract_cell_decl RAM32X1D - xtract_cell_decl RAM32X1S - xtract_cell_decl RAM32X1S_1 - xtract_cell_decl RAM32X2S - xtract_cell_decl RAM64M - #xtract_cell_decl RAM64X1D - xtract_cell_decl RAM64X1S - xtract_cell_decl RAM64X1S_1 - xtract_cell_decl RAM64X2S - # xtract_cell_decl RAMB18E1 - # xtract_cell_decl RAMB36E1 + #xtract_cell_decl RAM128X1D "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM128X1S "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM256X1S "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM32M "(* clkbuf_sink = \"WCLK\" *)" + #xtract_cell_decl RAM32X1D "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM32X1S "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM32X1S_1 "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM32X2S "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM64M "(* clkbuf_sink = \"WCLK\" *)" + #xtract_cell_decl RAM64X1D "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM64X1S "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM64X1S_1 "(* clkbuf_sink = \"WCLK\" *)" + xtract_cell_decl RAM64X2S "(* clkbuf_sink = \"WCLK\" *)" + # xtract_cell_decl RAMB18E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)" + # xtract_cell_decl RAMB36E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)" xtract_cell_decl ROM128X1 xtract_cell_decl ROM256X1 xtract_cell_decl ROM32X1 xtract_cell_decl ROM64X1 - #xtract_cell_decl SRL16E - #xtract_cell_decl SRLC32E + #xtract_cell_decl SRL16E "(* clkbuf_sink = \"CLK\" *)" + #xtract_cell_decl SRLC32E "(* clkbuf_sink = \"CLK\" *)" xtract_cell_decl STARTUPE2 "(* keep *)" xtract_cell_decl USR_ACCESSE2 xtract_cell_decl XADC diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 15fa1b63a..0fbbc0fdf 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -1,5 +1,6 @@ // Created by cells_xtra.sh from Xilinx models +(* keep *) module BSCANE2 (...); parameter DISABLE_JTAG = "FALSE"; parameter integer JTAG_CHAIN = 1; @@ -16,6 +17,7 @@ module BSCANE2 (...); input TDO; endmodule +(* clkbuf_driver = "O" *) module BUFGCE (...); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; @@ -25,23 +27,28 @@ module BUFGCE (...); input I; endmodule +(* clkbuf_driver = "O" *) module BUFGCE_1 (...); output O; - input CE, I; + input CE; + input I; endmodule +(* clkbuf_driver = "O" *) module BUFGMUX (...); parameter CLK_SEL_TYPE = "SYNC"; output O; input I0, I1, S; endmodule +(* clkbuf_driver = "O" *) module BUFGMUX_1 (...); parameter CLK_SEL_TYPE = "SYNC"; output O; input I0, I1, S; endmodule +(* clkbuf_driver = "O" *) module BUFGMUX_CTRL (...); output O; input I0; @@ -49,21 +56,25 @@ module BUFGMUX_CTRL (...); input S; endmodule +(* clkbuf_driver = "O" *) module BUFH (...); output O; input I; endmodule +(* clkbuf_driver = "O" *) module BUFIO (...); output O; input I; endmodule +(* clkbuf_driver = "O" *) module BUFMR (...); output O; input I; endmodule +(* clkbuf_driver = "O" *) module BUFMRCE (...); parameter CE_TYPE = "SYNC"; parameter integer INIT_OUT = 0; @@ -73,6 +84,7 @@ module BUFMRCE (...); input I; endmodule +(* clkbuf_driver = "O" *) module BUFR (...); output O; input CE; @@ -89,6 +101,7 @@ module CAPTUREE2 (...); input CLK; endmodule +(* clkbuf_sink = "CLK" *) module CFGLUT5 (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -111,6 +124,7 @@ module DNA_PORT (...); input CLK, DIN, READ, SHIFT; endmodule +(* clkbuf_sink = "CLK" *) module DSP48E1 (...); parameter integer ACASCREG = 1; parameter integer ADREG = 1; @@ -198,6 +212,7 @@ module EFUSE_USR (...); output [31:0] EFUSEUSR; endmodule +(* clkbuf_sink = "RDCLK,WRCLK" *) module FIFO18E1 (...); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; @@ -236,6 +251,7 @@ module FIFO18E1 (...); input WREN; endmodule +(* clkbuf_sink = "RDCLK,WRCLK" *) module FIFO36E1 (...); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; @@ -1963,6 +1979,7 @@ module GTXE2_COMMON (...); input [7:0] PMARSVD; endmodule +(* iopad_external_pin = "I" *) module IBUF_IBUFDISABLE (...); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -1973,6 +1990,7 @@ module IBUF_IBUFDISABLE (...); input IBUFDISABLE; endmodule +(* iopad_external_pin = "I" *) module IBUF_INTERMDISABLE (...); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; @@ -1984,6 +2002,7 @@ module IBUF_INTERMDISABLE (...); input INTERMDISABLE; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; @@ -1996,6 +2015,7 @@ module IBUFDS (...); input I, IB; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS_DIFF_OUT (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2005,6 +2025,7 @@ module IBUFDS_DIFF_OUT (...); input I, IB; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS_DIFF_OUT_IBUFDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2019,6 +2040,7 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...); input IBUFDISABLE; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2034,6 +2056,7 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...); input INTERMDISABLE; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS_GTE2 (...); parameter CLKCM_CFG = "TRUE"; parameter CLKRCV_TRST = "TRUE"; @@ -2045,6 +2068,7 @@ module IBUFDS_GTE2 (...); input IB; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS_IBUFDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2058,6 +2082,7 @@ module IBUFDS_IBUFDISABLE (...); input IBUFDISABLE; endmodule +(* iopad_external_pin = "I,IB" *) module IBUFDS_INTERMDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2072,6 +2097,37 @@ module IBUFDS_INTERMDISABLE (...); input INTERMDISABLE; endmodule +(* iopad_external_pin = "I" *) +module IBUFG (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + input I; +endmodule + +(* iopad_external_pin = "I,IB" *) +module IBUFGDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + input I, IB; +endmodule + +(* iopad_external_pin = "I,IB" *) +module IBUFGDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O, OB; + input I, IB; +endmodule + (* keep *) module ICAPE2 (...); parameter [31:0] DEVICE_ID = 32'h04244093; @@ -2084,6 +2140,7 @@ module ICAPE2 (...); input [31:0] I; endmodule +(* clkbuf_sink = "C" *) module IDDR (...); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; @@ -2102,6 +2159,7 @@ module IDDR (...); input S; endmodule +(* clkbuf_sink = "C,CB" *) module IDDR_2CLK (...); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; @@ -2120,7 +2178,7 @@ module IDDR_2CLK (...); input S; endmodule -(* keep *) +(* keep *) (* clkbuf_sink = "REFCLK" *) module IDELAYCTRL (...); parameter SIM_DEVICE = "7SERIES"; output RDY; @@ -2128,6 +2186,7 @@ module IDELAYCTRL (...); input RST; endmodule +(* clkbuf_sink = "C" *) module IDELAYE2 (...); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "IDATAIN"; @@ -2155,6 +2214,7 @@ module IDELAYE2 (...); input REGRST; endmodule +(* clkbuf_sink = "RDCLK,WRCLK" *) module IN_FIFO (...); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; @@ -2191,6 +2251,7 @@ module IN_FIFO (...); input [7:0] D6; endmodule +(* iopad_external_pin = "IO" *) module IOBUF (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -2201,6 +2262,7 @@ module IOBUF (...); input I, T; endmodule +(* iopad_external_pin = "IO" *) module IOBUF_DCIEN (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -2216,6 +2278,7 @@ module IOBUF_DCIEN (...); input T; endmodule +(* iopad_external_pin = "IO" *) module IOBUF_INTERMDISABLE (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -2231,6 +2294,7 @@ module IOBUF_INTERMDISABLE (...); input T; endmodule +(* iopad_external_pin = "IO" *) module IOBUFDS (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2242,6 +2306,7 @@ module IOBUFDS (...); input I, T; endmodule +(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DCIEN (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2259,6 +2324,7 @@ module IOBUFDS_DCIEN (...); input T; endmodule +(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DIFF_OUT (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2273,6 +2339,7 @@ module IOBUFDS_DIFF_OUT (...); input TS; endmodule +(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DIFF_OUT_DCIEN (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2291,6 +2358,7 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); input TS; endmodule +(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2309,6 +2377,7 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); input TS; endmodule +(* clkbuf_sink = "CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB" *) module ISERDESE2 (...); parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; @@ -2529,6 +2598,7 @@ module MMCME2_BASE (...); input RST; endmodule +(* iopad_external_pin = "O,OB" *) module OBUFDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; @@ -2537,6 +2607,7 @@ module OBUFDS (...); input I; endmodule +(* iopad_external_pin = "O" *) module OBUFT (...); parameter CAPACITANCE = "DONT_CARE"; parameter integer DRIVE = 12; @@ -2546,6 +2617,7 @@ module OBUFT (...); input I, T; endmodule +(* iopad_external_pin = "O,OB" *) module OBUFTDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; @@ -2554,6 +2626,7 @@ module OBUFTDS (...); input I, T; endmodule +(* clkbuf_sink = "C" *) module ODDR (...); output Q; input C; @@ -2572,6 +2645,7 @@ module ODDR (...); parameter XON = "TRUE"; endmodule +(* clkbuf_sink = "C" *) module ODELAYE2 (...); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "ODATAIN"; @@ -2598,6 +2672,7 @@ module ODELAYE2 (...); input REGRST; endmodule +(* clkbuf_sink = "CLK,CLKDIV" *) module OSERDESE2 (...); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; @@ -2653,6 +2728,7 @@ module OSERDESE2 (...); input TCE; endmodule +(* clkbuf_sink = "RDCLK,WRCLK" *) module OUT_FIFO (...); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; @@ -3655,6 +3731,7 @@ module PULLUP (...); output O; endmodule +(* clkbuf_sink = "WCLK" *) module RAM128X1S (...); parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3662,6 +3739,7 @@ module RAM128X1S (...); input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM256X1S (...); parameter [255:0] INIT = 256'h0; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3672,6 +3750,7 @@ module RAM256X1S (...); input WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM32M (...); parameter [63:0] INIT_A = 64'h0000000000000000; parameter [63:0] INIT_B = 64'h0000000000000000; @@ -3694,6 +3773,7 @@ module RAM32M (...); input WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM32X1S (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3701,6 +3781,7 @@ module RAM32X1S (...); input A0, A1, A2, A3, A4, D, WCLK, WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM32X1S_1 (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3708,6 +3789,7 @@ module RAM32X1S_1 (...); input A0, A1, A2, A3, A4, D, WCLK, WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM32X2S (...); parameter [31:0] INIT_00 = 32'h00000000; parameter [31:0] INIT_01 = 32'h00000000; @@ -3716,6 +3798,7 @@ module RAM32X2S (...); input A0, A1, A2, A3, A4, D0, D1, WCLK, WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM64M (...); parameter [63:0] INIT_A = 64'h0000000000000000; parameter [63:0] INIT_B = 64'h0000000000000000; @@ -3738,6 +3821,7 @@ module RAM64M (...); input WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM64X1S (...); parameter [63:0] INIT = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3745,6 +3829,7 @@ module RAM64X1S (...); input A0, A1, A2, A3, A4, A5, D, WCLK, WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM64X1S_1 (...); parameter [63:0] INIT = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3752,6 +3837,7 @@ module RAM64X1S_1 (...); input A0, A1, A2, A3, A4, A5, D, WCLK, WE; endmodule +(* clkbuf_sink = "WCLK" *) module RAM64X2S (...); parameter [63:0] INIT_00 = 64'h0000000000000000; parameter [63:0] INIT_01 = 64'h0000000000000000; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d143c6823..a7362d26b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -ise\n"); + log(" generate an output netlist suitable for ISE\n"); + log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); log("\n"); @@ -78,6 +81,12 @@ struct SynthXilinxPass : public ScriptPass log(" -nowidelut\n"); log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n"); log("\n"); + log(" -iopads\n"); + log(" perform I/O buffer insertion (selected automatically by -ise)\n"); + log("\n"); + log(" -noiopads\n"); + log(" disable I/O buffer insertion (only useful with -ise)\n"); + log("\n"); log(" -widemux \n"); log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n"); log(" above this number of inputs (minimum value 2, recommended value >= 5).\n"); @@ -104,7 +113,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9; + bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9; int widemux; void clear_flags() YS_OVERRIDE @@ -116,6 +125,9 @@ struct SynthXilinxPass : public ScriptPass flatten = false; retime = false; vpr = false; + ise = false; + iopads = false; + noiopads = false; nocarry = false; nobram = false; nodram = false; @@ -178,6 +190,18 @@ struct SynthXilinxPass : public ScriptPass vpr = true; continue; } + if (args[argidx] == "-ise") { + ise = true; + continue; + } + if (args[argidx] == "-iopads") { + iopads = true; + continue; + } + if (args[argidx] == "-noiopads") { + noiopads = true; + continue; + } if (args[argidx] == "-nocarry") { nocarry = true; continue; @@ -410,6 +434,17 @@ struct SynthXilinxPass : public ScriptPass run("clean"); } + if (check_label("finalize")) { + bool do_iopads = iopads || (ise && !noiopads); + if (help_mode || do_iopads) + run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')"); + else + run("clkbufmap -buf BUFG O:I"); + + if (do_iopads) + run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')"); + } + if (check_label("check")) { run("hierarchy -check"); run("stat -tech xilinx"); diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v index eb1a29579..1287e2c53 100644 --- a/techlibs/xilinx/xc6s_brams_bb.v +++ b/techlibs/xilinx/xc6s_brams_bb.v @@ -1,3 +1,4 @@ +(* clkbuf_sink = "CLKAWRCLK,CLKBRDCLK" *) module RAMB8BWER ( input CLKAWRCLK, input CLKBRDCLK, @@ -86,6 +87,7 @@ module RAMB8BWER ( parameter SIM_COLLISION_CHECK = "ALL"; endmodule +(* clkbuf_sink = "CLKA,CLKB" *) module RAMB16BWER ( input CLKA, input CLKB, diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index a682ba4a7..046a8fa26 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -1,3 +1,4 @@ +(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *) module RAMB18E1 ( input CLKARDCLK, input CLKBWRCLK, @@ -122,6 +123,7 @@ module RAMB18E1 ( parameter SIM_DEVICE = "VIRTEX6"; endmodule +(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *) module RAMB36E1 ( input CLKARDCLK, input CLKBWRCLK, -- cgit v1.2.3 From c6d5b97b98e6edc395ee14ad60430f7ebc264f01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 13 Aug 2019 00:35:54 +0000 Subject: review fixes --- techlibs/xilinx/synth_xilinx.cc | 45 ++++++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 18 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a7362d26b..e9e8dbfea 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -81,12 +81,15 @@ struct SynthXilinxPass : public ScriptPass log(" -nowidelut\n"); log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n"); log("\n"); - log(" -iopads\n"); - log(" perform I/O buffer insertion (selected automatically by -ise)\n"); + log(" -iopad\n"); + log(" enable I/O buffer insertion (selected automatically by -ise)\n"); log("\n"); - log(" -noiopads\n"); + log(" -noiopad\n"); log(" disable I/O buffer insertion (only useful with -ise)\n"); log("\n"); + log(" -noclkbuf\n"); + log(" disable automatic clock buffer insertion\n"); + log("\n"); log(" -widemux \n"); log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n"); log(" above this number of inputs (minimum value 2, recommended value >= 5).\n"); @@ -113,7 +116,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9; + bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nodram, nosrl, nocarry, nowidelut, abc9; int widemux; void clear_flags() YS_OVERRIDE @@ -126,8 +129,9 @@ struct SynthXilinxPass : public ScriptPass retime = false; vpr = false; ise = false; - iopads = false; - noiopads = false; + iopad = false; + noiopad = false; + noclkbuf = false; nocarry = false; nobram = false; nodram = false; @@ -194,12 +198,16 @@ struct SynthXilinxPass : public ScriptPass ise = true; continue; } - if (args[argidx] == "-iopads") { - iopads = true; + if (args[argidx] == "-iopad") { + iopad = true; + continue; + } + if (args[argidx] == "-noiopad") { + noiopad = true; continue; } - if (args[argidx] == "-noiopads") { - noiopads = true; + if (args[argidx] == "-noclkbuf") { + noclkbuf = true; continue; } if (args[argidx] == "-nocarry") { @@ -435,14 +443,15 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("finalize")) { - bool do_iopads = iopads || (ise && !noiopads); - if (help_mode || do_iopads) - run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')"); - else - run("clkbufmap -buf BUFG O:I"); - - if (do_iopads) - run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')"); + bool do_iopad = iopad || (ise && !noiopad); + if (help_mode || !noclkbuf) { + if (help_mode || do_iopad) + run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')"); + else + run("clkbufmap -buf BUFG O:I"); + } + if (do_iopad) + run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); } if (check_label("check")) { -- cgit v1.2.3 From 49765ec19ea63bff5f04e28e5729d5852a2f8287 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 13 Aug 2019 18:05:49 +0000 Subject: minor review fixes --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e9e8dbfea..4069094a6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -ise\n"); - log(" generate an output netlist suitable for ISE\n"); + log(" generate an output netlist suitable for ISE (enables -iopad)\n"); log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); -- cgit v1.2.3 From 3c75a72feb1cf83fa8fc138aa69155446b6b74f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 13 Aug 2019 19:36:59 +0000 Subject: move attributes to wires --- techlibs/xilinx/cells_sim.v | 75 +++++----- techlibs/xilinx/cells_xtra.py | 257 ++++++++++++++++++++++++++++++++ techlibs/xilinx/cells_xtra.sh | 155 ------------------- techlibs/xilinx/cells_xtra.v | 321 ++++++++++++++++++++++++++++------------ techlibs/xilinx/xc6s_brams_bb.v | 6 +- techlibs/xilinx/xc7_brams_bb.v | 6 +- 6 files changed, 537 insertions(+), 283 deletions(-) create mode 100644 techlibs/xilinx/cells_xtra.py delete mode 100644 techlibs/xilinx/cells_xtra.sh (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d5815ca77..27511a05f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -29,26 +29,35 @@ module GND(output G); assign G = 0; endmodule -module IBUF(output O, input I); +module IBUF( + output O, + (* iopad_external_pin *) + input I); parameter IOSTANDARD = "default"; parameter IBUF_LOW_PWR = 0; assign O = I; endmodule -module OBUF(output O, input I); +module OBUF( + (* iopad_external_pin *) + output O, + input I); parameter IOSTANDARD = "default"; parameter DRIVE = 12; parameter SLEW = "SLOW"; assign O = I; endmodule -(* clkbuf_driver = "O" *) -module BUFG(output O, input I); +module BUFG( + (* clkbuf_driver *) + output O, + input I); + assign O = I; endmodule -(* clkbuf_driver = "O" *) module BUFGCTRL( + (* clkbuf_driver *) output O, input I0, input I1, input S0, input S1, @@ -74,8 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT); endmodule -(* clkbuf_driver = "O" *) -module BUFHCE(output O, input I, input CE); +module BUFHCE( + (* clkbuf_driver *) + output O, + input I, + input CE); parameter [0:0] INIT_OUT = 1'b0; parameter CE_TYPE = "SYNC"; @@ -216,8 +228,7 @@ endmodule `endif -(* clkbuf_sink = "C" *) -module FDRE (output reg Q, input C, CE, D, R); +module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -229,8 +240,7 @@ module FDRE (output reg Q, input C, CE, D, R); endcase endgenerate endmodule -(* clkbuf_sink = "C" *) -module FDSE (output reg Q, input C, CE, D, S); +module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -242,8 +252,7 @@ module FDSE (output reg Q, input C, CE, D, S); endcase endgenerate endmodule -(* clkbuf_sink = "C" *) -module FDCE (output reg Q, input C, CE, D, CLR); +module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -257,8 +266,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); endcase endgenerate endmodule -(* clkbuf_sink = "C" *) -module FDPE (output reg Q, input C, CE, D, PRE); +module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE); parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -272,39 +280,36 @@ module FDPE (output reg Q, input C, CE, D, PRE); endcase endgenerate endmodule -(* clkbuf_sink = "C" *) -module FDRE_1 (output reg Q, input C, CE, D, R); +module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; endmodule -(* clkbuf_sink = "C" *) -module FDSE_1 (output reg Q, input C, CE, D, S); +module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; endmodule -(* clkbuf_sink = "C" *) -module FDCE_1 (output reg Q, input C, CE, D, CLR); +module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule -(* clkbuf_sink = "C" *) -module FDPE_1 (output reg Q, input C, CE, D, PRE); +module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* clkbuf_sink = "WCLK" *) (* abc_box_id = 5, abc_scc_break="D,WE" *) module RAM32X1D ( output DPO, SPO, - input D, WCLK, WE, + (* clkbuf_sink *) + input WCLK, + input D, WE, input A0, A1, A2, A3, A4, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); @@ -319,11 +324,12 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* clkbuf_sink = "WCLK" *) (* abc_box_id = 6, abc_scc_break="D,WE" *) module RAM64X1D ( output DPO, SPO, - input D, WCLK, WE, + (* clkbuf_sink *) + input WCLK, + input D, WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); @@ -338,11 +344,12 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* clkbuf_sink = "WCLK" *) (* abc_box_id = 7, abc_scc_break="D,WE" *) module RAM128X1D ( output DPO, SPO, - input D, WCLK, WE, + input D, WE, + (* clkbuf_sink *) + input WCLK, input [6:0] A, DPRA ); parameter INIT = 128'h0; @@ -354,10 +361,11 @@ module RAM128X1D ( always @(posedge clk) if (WE) mem[A] <= D; endmodule -(* clkbuf_sink = "CLK" *) module SRL16E ( output Q, - input A0, A1, A2, A3, CE, CLK, D + (* clkbuf_sink *) + input CLK, + input A0, A1, A2, A3, CE, D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -373,12 +381,13 @@ module SRL16E ( endgenerate endmodule -(* clkbuf_sink = "CLK" *) module SRLC32E ( output Q, output Q31, input [4:0] A, - input CE, CLK, D + (* clkbuf_sink *) + input CLK, + input CE, D ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py new file mode 100644 index 000000000..dd4e300ae --- /dev/null +++ b/techlibs/xilinx/cells_xtra.py @@ -0,0 +1,257 @@ +#!/usr/bin/env python3 + +from argparse import ArgumentParser +from io import StringIO +from enum import Enum, auto +import os.path +import sys + + +class Cell: + def __init__(self, name, keep=False, port_attrs={}): + self.name = name + self.keep = keep + self.port_attrs = port_attrs + + +CELLS = [ + # Design elements types listed in Xilinx UG953 + Cell('BSCANE2', keep=True), + # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), + #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), + #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}), + Cell('CAPTUREE2', keep=True), + # Cell('CARRY4'), + Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('DCIRESET', keep=True), + Cell('DNA_PORT'), + Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('EFUSE_USR'), + # Cell('FDCE'), + # Cell('FDPE'), + # Cell('FDRE'), + # Cell('FDSE'), + Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FRAME_ECCE2'), + Cell('GTHE2_CHANNEL'), + Cell('GTHE2_COMMON'), + Cell('GTPE2_CHANNEL'), + Cell('GTPE2_COMMON'), + Cell('GTXE2_CHANNEL'), + Cell('GTXE2_COMMON'), + # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('ICAPE2', keep=True), + Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), + Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), + Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}), + Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('ISERDESE2', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'OCLKB': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + 'CLKDIVP': ['clkbuf_sink'], + }), + Cell('KEEPER'), + Cell('LDCE'), + Cell('LDPE'), + # Cell('LUT1'), + # Cell('LUT2'), + # Cell('LUT3'), + # Cell('LUT4'), + # Cell('LUT5'), + # Cell('LUT6'), + #Cell('LUT6_2'), + Cell('MMCME2_ADV'), + Cell('MMCME2_BASE'), + # Cell('MUXF7'), + # Cell('MUXF8'), + # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), + Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), + Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), + Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}), + Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('PHASER_IN'), + Cell('PHASER_IN_PHY'), + Cell('PHASER_OUT'), + Cell('PHASER_OUT_PHY'), + Cell('PHASER_REF'), + Cell('PHY_CONTROL'), + Cell('PLLE2_ADV'), + Cell('PLLE2_BASE'), + Cell('PS7', keep=True), + Cell('PULLDOWN'), + Cell('PULLUP'), + #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), + #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), + #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + Cell('ROM128X1'), + Cell('ROM256X1'), + Cell('ROM32X1'), + Cell('ROM64X1'), + #Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('STARTUPE2', keep=True), + Cell('USR_ACCESSE2'), + Cell('XADC'), +] + +class State(Enum): + OUTSIDE = auto() + IN_MODULE = auto() + IN_OTHER_MODULE = auto() + IN_FUNCTION = auto() + IN_TASK = auto() + +def xtract_cell_decl(cell, dirs, outf): + for dir in dirs: + fname = os.path.join(dir, cell.name + '.v') + try: + with open(fname) as f: + state = State.OUTSIDE + found = False + # Probably the most horrible Verilog "parser" ever written. + for l in f: + l = l.partition('//')[0] + l = l.strip() + if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)): + if found: + print('Multiple modules in {}.'.format(fname)) + sys.exit(1) + elif state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + found = True + state = State.IN_MODULE + if cell.keep: + outf.write('(* keep *)\n') + outf.write('module {} (...);\n'.format(cell.name)) + elif l.startswith('module '): + if state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + state = State.IN_OTHER_MODULE + elif l.startswith('task '): + if state == State.IN_MODULE: + state = State.IN_TASK + elif l.startswith('function '): + if state == State.IN_MODULE: + state = State.IN_FUNCTION + elif l == 'endtask': + if state == State.IN_TASK: + state = State.IN_MODULE + elif l == 'endfunction': + if state == State.IN_FUNCTION: + state = State.IN_MODULE + elif l == 'endmodule': + if state == State.IN_MODULE: + outf.write(l + '\n') + outf.write('\n') + elif state != State.IN_OTHER_MODULE: + print('endmodule in weird place in {}.'.format(cell.name, fname)) + sys.exit(1) + state = State.OUTSIDE + elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: + if l.endswith((';', ',')): + l = l[:-1] + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + kind, _, ports = l.partition(' ') + for port in ports.split(','): + port = port.strip() + for attr in cell.port_attrs.get(port, []): + outf.write(' (* {} *)\n'.format(attr)) + outf.write(' {} {};\n'.format(kind, port)) + elif l.startswith('parameter ') and state == State.IN_MODULE: + if 'UNPLACED' in l: + continue + if l.endswith((';', ',')): + l = l[:-1] + while ' ' in l: + l = l.replace(' ', ' ') + if ';' in l: + print('Weird parameter line in {} [{}].'.format(fname, l)) + sys.exit(1) + outf.write(' {};\n'.format(l)) + if state != State.OUTSIDE: + print('endmodule not found in {}.'.format(fname)) + sys.exit(1) + if not found: + print('Cannot find module {} in {}.'.format(cell.name, fname)) + sys.exit(1) + return + except FileNotFoundError: + continue + print('Cannot find {}.'.format(cell.name)) + sys.exit(1) + +if __name__ == '__main__': + parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from Vivado.') + parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1') + args = parser.parse_args() + + dirs = [ + os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'), + os.path.join(args.vivado_dir, 'data/verilog/src/retarget'), + ] + for dir in dirs: + if not os.path.isdir(dir): + print('{} is not a directory'.format(dir)) + + out = StringIO() + for cell in CELLS: + xtract_cell_decl(cell, dirs, out) + + with open('cells_xtra.v', 'w') as f: + f.write('// Created by cells_xtra.py from Xilinx models\n') + f.write('\n') + f.write(out.getvalue()) diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh deleted file mode 100644 index 3291e46a8..000000000 --- a/techlibs/xilinx/cells_xtra.sh +++ /dev/null @@ -1,155 +0,0 @@ -#!/bin/bash - -set -e -if [ -z "$1" ] -then - libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src" -else - libdir=$1 -fi - -function xtract_cell_decl() -{ - for dir in $libdir/xeclib $libdir/retarget; do - [ -f $dir/$1.v ] || continue - [ -z "$2" ] || echo $2 - egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v | - sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d; - s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/; - s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g; - s/^ ((end)?module)/\1/; s/^ / /; /module.*_bb/,/endmodule/ d;' - echo; return - done - echo "Can't find $1." - exit 1 -} - -{ - echo "// Created by cells_xtra.sh from Xilinx models" - echo - - # Design elements types listed in Xilinx UG953 - xtract_cell_decl BSCANE2 "(* keep *)" - # xtract_cell_decl BUFG "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFGCE "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFGCE_1 "(* clkbuf_driver = \"O\" *)" - #xtract_cell_decl BUFGCTRL "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFGMUX "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFGMUX_1 "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFGMUX_CTRL "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFH "(* clkbuf_driver = \"O\" *)" - #xtract_cell_decl BUFHCE "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFIO "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFMR "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFMRCE "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl BUFR "(* clkbuf_driver = \"O\" *)" - xtract_cell_decl CAPTUREE2 "(* keep *)" - # xtract_cell_decl CARRY4 - xtract_cell_decl CFGLUT5 "(* clkbuf_sink = \"CLK\" *)" - xtract_cell_decl DCIRESET "(* keep *)" - xtract_cell_decl DNA_PORT - xtract_cell_decl DSP48E1 "(* clkbuf_sink = \"CLK\" *)" - xtract_cell_decl EFUSE_USR - # xtract_cell_decl FDCE - # xtract_cell_decl FDPE - # xtract_cell_decl FDRE - # xtract_cell_decl FDSE - xtract_cell_decl FIFO18E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" - xtract_cell_decl FIFO36E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" - xtract_cell_decl FRAME_ECCE2 - xtract_cell_decl GTHE2_CHANNEL - xtract_cell_decl GTHE2_COMMON - xtract_cell_decl GTPE2_CHANNEL - xtract_cell_decl GTPE2_COMMON - xtract_cell_decl GTXE2_CHANNEL - xtract_cell_decl GTXE2_COMMON - # xtract_cell_decl IBUF "(* iopad_external_pin = \"I\" *)" - xtract_cell_decl IBUF_IBUFDISABLE "(* iopad_external_pin = \"I\" *)" - xtract_cell_decl IBUF_INTERMDISABLE "(* iopad_external_pin = \"I\" *)" - xtract_cell_decl IBUFDS "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFDS_GTE2 "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFDS_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFDS_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFG "(* iopad_external_pin = \"I\" *)" - xtract_cell_decl IBUFGDS "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl IBUFGDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)" - xtract_cell_decl ICAPE2 "(* keep *)" - xtract_cell_decl IDDR "(* clkbuf_sink = \"C\" *)" - xtract_cell_decl IDDR_2CLK "(* clkbuf_sink = \"C,CB\" *)" - xtract_cell_decl IDELAYCTRL "(* keep *) (* clkbuf_sink = \"REFCLK\" *)" - xtract_cell_decl IDELAYE2 "(* clkbuf_sink = \"C\" *)" - xtract_cell_decl IN_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" - xtract_cell_decl IOBUF "(* iopad_external_pin = \"IO\" *)" - xtract_cell_decl IOBUF_DCIEN "(* iopad_external_pin = \"IO\" *)" - xtract_cell_decl IOBUF_INTERMDISABLE "(* iopad_external_pin = \"IO\" *)" - xtract_cell_decl IOBUFDS "(* iopad_external_pin = \"IO\" *)" - xtract_cell_decl IOBUFDS_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)" - xtract_cell_decl IOBUFDS_DIFF_OUT "(* iopad_external_pin = \"IO,IOB\" *)" - xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)" - xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"IO,IOB\" *)" - xtract_cell_decl ISERDESE2 "(* clkbuf_sink = \"CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB\" *)" - xtract_cell_decl KEEPER - xtract_cell_decl LDCE - xtract_cell_decl LDPE - # xtract_cell_decl LUT1 - # xtract_cell_decl LUT2 - # xtract_cell_decl LUT3 - # xtract_cell_decl LUT4 - # xtract_cell_decl LUT5 - # xtract_cell_decl LUT6 - #xtract_cell_decl LUT6_2 - xtract_cell_decl MMCME2_ADV - xtract_cell_decl MMCME2_BASE - # xtract_cell_decl MUXF7 - # xtract_cell_decl MUXF8 - # xtract_cell_decl OBUF "(* iopad_external_pin = \"O\" *)" - xtract_cell_decl OBUFDS "(* iopad_external_pin = \"O,OB\" *)" - xtract_cell_decl OBUFT "(* iopad_external_pin = \"O\" *)" - xtract_cell_decl OBUFTDS "(* iopad_external_pin = \"O,OB\" *)" - xtract_cell_decl ODDR "(* clkbuf_sink = \"C\" *)" - xtract_cell_decl ODELAYE2 "(* clkbuf_sink = \"C\" *)" - xtract_cell_decl OSERDESE2 "(* clkbuf_sink = \"CLK,CLKDIV\" *)" - xtract_cell_decl OUT_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)" - xtract_cell_decl PHASER_IN - xtract_cell_decl PHASER_IN_PHY - xtract_cell_decl PHASER_OUT - xtract_cell_decl PHASER_OUT_PHY - xtract_cell_decl PHASER_REF - xtract_cell_decl PHY_CONTROL - xtract_cell_decl PLLE2_ADV - xtract_cell_decl PLLE2_BASE - xtract_cell_decl PS7 "(* keep *)" - xtract_cell_decl PULLDOWN - xtract_cell_decl PULLUP - #xtract_cell_decl RAM128X1D "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM128X1S "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM256X1S "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM32M "(* clkbuf_sink = \"WCLK\" *)" - #xtract_cell_decl RAM32X1D "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM32X1S "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM32X1S_1 "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM32X2S "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM64M "(* clkbuf_sink = \"WCLK\" *)" - #xtract_cell_decl RAM64X1D "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM64X1S "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM64X1S_1 "(* clkbuf_sink = \"WCLK\" *)" - xtract_cell_decl RAM64X2S "(* clkbuf_sink = \"WCLK\" *)" - # xtract_cell_decl RAMB18E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)" - # xtract_cell_decl RAMB36E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)" - xtract_cell_decl ROM128X1 - xtract_cell_decl ROM256X1 - xtract_cell_decl ROM32X1 - xtract_cell_decl ROM64X1 - #xtract_cell_decl SRL16E "(* clkbuf_sink = \"CLK\" *)" - #xtract_cell_decl SRLC32E "(* clkbuf_sink = \"CLK\" *)" - xtract_cell_decl STARTUPE2 "(* keep *)" - xtract_cell_decl USR_ACCESSE2 - xtract_cell_decl XADC -} > cells_xtra.new - -mv cells_xtra.new cells_xtra.v -exit 0 - diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 0fbbc0fdf..a6669b872 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -1,4 +1,4 @@ -// Created by cells_xtra.sh from Xilinx models +// Created by cells_xtra.py from Xilinx models (* keep *) module BSCANE2 (...); @@ -17,75 +17,79 @@ module BSCANE2 (...); input TDO; endmodule -(* clkbuf_driver = "O" *) module BUFGCE (...); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; parameter [0:0] IS_I_INVERTED = 1'b0; + (* clkbuf_driver *) output O; input CE; input I; endmodule -(* clkbuf_driver = "O" *) module BUFGCE_1 (...); + (* clkbuf_driver *) output O; input CE; input I; endmodule -(* clkbuf_driver = "O" *) module BUFGMUX (...); parameter CLK_SEL_TYPE = "SYNC"; + (* clkbuf_driver *) output O; - input I0, I1, S; + input I0; + input I1; + input S; endmodule -(* clkbuf_driver = "O" *) module BUFGMUX_1 (...); parameter CLK_SEL_TYPE = "SYNC"; + (* clkbuf_driver *) output O; - input I0, I1, S; + input I0; + input I1; + input S; endmodule -(* clkbuf_driver = "O" *) module BUFGMUX_CTRL (...); + (* clkbuf_driver *) output O; input I0; input I1; input S; endmodule -(* clkbuf_driver = "O" *) module BUFH (...); + (* clkbuf_driver *) output O; input I; endmodule -(* clkbuf_driver = "O" *) module BUFIO (...); + (* clkbuf_driver *) output O; input I; endmodule -(* clkbuf_driver = "O" *) module BUFMR (...); + (* clkbuf_driver *) output O; input I; endmodule -(* clkbuf_driver = "O" *) module BUFMRCE (...); parameter CE_TYPE = "SYNC"; parameter integer INIT_OUT = 0; parameter [0:0] IS_CE_INVERTED = 1'b0; + (* clkbuf_driver *) output O; input CE; input I; endmodule -(* clkbuf_driver = "O" *) module BUFR (...); + (* clkbuf_driver *) output O; input CE; input CLR; @@ -101,15 +105,21 @@ module CAPTUREE2 (...); input CLK; endmodule -(* clkbuf_sink = "CLK" *) module CFGLUT5 (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; output CDO; output O5; output O6; - input I4, I3, I2, I1, I0; - input CDI, CE, CLK; + input I4; + input I3; + input I2; + input I1; + input I0; + input CDI; + input CE; + (* clkbuf_sink *) + input CLK; endmodule (* keep *) @@ -121,10 +131,12 @@ endmodule module DNA_PORT (...); parameter [56:0] SIM_DNA_VALUE = 57'h0; output DOUT; - input CLK, DIN, READ, SHIFT; + input CLK; + input DIN; + input READ; + input SHIFT; endmodule -(* clkbuf_sink = "CLK" *) module DSP48E1 (...); parameter integer ACASCREG = 1; parameter integer ADREG = 1; @@ -189,6 +201,7 @@ module DSP48E1 (...); input CEINMODE; input CEM; input CEP; + (* clkbuf_sink *) input CLK; input [24:0] D; input [4:0] INMODE; @@ -212,7 +225,6 @@ module EFUSE_USR (...); output [31:0] EFUSEUSR; endmodule -(* clkbuf_sink = "RDCLK,WRCLK" *) module FIFO18E1 (...); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; @@ -242,16 +254,17 @@ module FIFO18E1 (...); output WRERR; input [31:0] DI; input [3:0] DIP; + (* clkbuf_sink *) input RDCLK; input RDEN; input REGCE; input RST; input RSTREG; + (* clkbuf_sink *) input WRCLK; input WREN; endmodule -(* clkbuf_sink = "RDCLK,WRCLK" *) module FIFO36E1 (...); parameter ALMOST_EMPTY_OFFSET = 13'h0080; parameter ALMOST_FULL_OFFSET = 13'h0080; @@ -288,11 +301,13 @@ module FIFO36E1 (...); input [7:0] DIP; input INJECTDBITERR; input INJECTSBITERR; + (* clkbuf_sink *) input RDCLK; input RDEN; input REGCE; input RST; input RSTREG; + (* clkbuf_sink *) input WRCLK; input WREN; endmodule @@ -1979,30 +1994,29 @@ module GTXE2_COMMON (...); input [7:0] PMARSVD; endmodule -(* iopad_external_pin = "I" *) module IBUF_IBUFDISABLE (...); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SIM_DEVICE = "7SERIES"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) input I; input IBUFDISABLE; endmodule -(* iopad_external_pin = "I" *) module IBUF_INTERMDISABLE (...); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SIM_DEVICE = "7SERIES"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) input I; input IBUFDISABLE; input INTERMDISABLE; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; @@ -2012,20 +2026,25 @@ module IBUFDS (...); parameter IFD_DELAY_VALUE = "AUTO"; parameter IOSTANDARD = "DEFAULT"; output O; - input I, IB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS_DIFF_OUT (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; - output O, OB; - input I, IB; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS_DIFF_OUT_IBUFDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2035,12 +2054,13 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + (* iopad_external_pin *) input I; + (* iopad_external_pin *) input IB; input IBUFDISABLE; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2050,13 +2070,14 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + (* iopad_external_pin *) input I; + (* iopad_external_pin *) input IB; input IBUFDISABLE; input INTERMDISABLE; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS_GTE2 (...); parameter CLKCM_CFG = "TRUE"; parameter CLKRCV_TRST = "TRUE"; @@ -2064,11 +2085,12 @@ module IBUFDS_GTE2 (...); output O; output ODIV2; input CEB; + (* iopad_external_pin *) input I; + (* iopad_external_pin *) input IB; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS_IBUFDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2077,12 +2099,13 @@ module IBUFDS_IBUFDISABLE (...); parameter SIM_DEVICE = "7SERIES"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) input I; + (* iopad_external_pin *) input IB; input IBUFDISABLE; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFDS_INTERMDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2091,23 +2114,24 @@ module IBUFDS_INTERMDISABLE (...); parameter SIM_DEVICE = "7SERIES"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) input I; + (* iopad_external_pin *) input IB; input IBUFDISABLE; input INTERMDISABLE; endmodule -(* iopad_external_pin = "I" *) module IBUFG (...); parameter CAPACITANCE = "DONT_CARE"; parameter IBUF_DELAY_VALUE = "0"; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; output O; + (* iopad_external_pin *) input I; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; @@ -2115,17 +2139,23 @@ module IBUFGDS (...); parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; output O; - input I, IB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; endmodule -(* iopad_external_pin = "I,IB" *) module IBUFGDS_DIFF_OUT (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; - output O, OB; - input I, IB; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; endmodule (* keep *) @@ -2140,7 +2170,6 @@ module ICAPE2 (...); input [31:0] I; endmodule -(* clkbuf_sink = "C" *) module IDDR (...); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; @@ -2152,6 +2181,7 @@ module IDDR (...); parameter XON = "TRUE"; output Q1; output Q2; + (* clkbuf_sink *) input C; input CE; input D; @@ -2159,7 +2189,6 @@ module IDDR (...); input S; endmodule -(* clkbuf_sink = "C,CB" *) module IDDR_2CLK (...); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT_Q1 = 1'b0; @@ -2170,7 +2199,9 @@ module IDDR_2CLK (...); parameter SRTYPE = "SYNC"; output Q1; output Q2; + (* clkbuf_sink *) input C; + (* clkbuf_sink *) input CB; input CE; input D; @@ -2178,15 +2209,15 @@ module IDDR_2CLK (...); input S; endmodule -(* keep *) (* clkbuf_sink = "REFCLK" *) +(* keep *) module IDELAYCTRL (...); parameter SIM_DEVICE = "7SERIES"; output RDY; + (* clkbuf_sink *) input REFCLK; input RST; endmodule -(* clkbuf_sink = "C" *) module IDELAYE2 (...); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "IDATAIN"; @@ -2202,6 +2233,7 @@ module IDELAYE2 (...); parameter integer SIM_DELAY_D = 0; output [4:0] CNTVALUEOUT; output DATAOUT; + (* clkbuf_sink *) input C; input CE; input CINVCTRL; @@ -2214,7 +2246,6 @@ module IDELAYE2 (...); input REGRST; endmodule -(* clkbuf_sink = "RDCLK,WRCLK" *) module IN_FIFO (...); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; @@ -2234,9 +2265,11 @@ module IN_FIFO (...); output [7:0] Q7; output [7:0] Q8; output [7:0] Q9; + (* clkbuf_sink *) input RDCLK; input RDEN; input RESET; + (* clkbuf_sink *) input WRCLK; input WREN; input [3:0] D0; @@ -2251,18 +2284,18 @@ module IN_FIFO (...); input [7:0] D6; endmodule -(* iopad_external_pin = "IO" *) module IOBUF (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; + (* iopad_external_pin *) inout IO; - input I, T; + input I; + input T; endmodule -(* iopad_external_pin = "IO" *) module IOBUF_DCIEN (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -2271,6 +2304,7 @@ module IOBUF_DCIEN (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) inout IO; input DCITERMDISABLE; input I; @@ -2278,7 +2312,6 @@ module IOBUF_DCIEN (...); input T; endmodule -(* iopad_external_pin = "IO" *) module IOBUF_INTERMDISABLE (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; @@ -2287,6 +2320,7 @@ module IOBUF_INTERMDISABLE (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) inout IO; input I; input IBUFDISABLE; @@ -2294,7 +2328,6 @@ module IOBUF_INTERMDISABLE (...); input T; endmodule -(* iopad_external_pin = "IO" *) module IOBUFDS (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2302,11 +2335,13 @@ module IOBUFDS (...); parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; output O; - inout IO, IOB; - input I, T; + (* iopad_external_pin *) + inout IO; + inout IOB; + input I; + input T; endmodule -(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DCIEN (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2316,7 +2351,9 @@ module IOBUFDS_DCIEN (...); parameter SLEW = "SLOW"; parameter USE_IBUFDISABLE = "TRUE"; output O; + (* iopad_external_pin *) inout IO; + (* iopad_external_pin *) inout IOB; input DCITERMDISABLE; input I; @@ -2324,7 +2361,6 @@ module IOBUFDS_DCIEN (...); input T; endmodule -(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DIFF_OUT (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2332,14 +2368,15 @@ module IOBUFDS_DIFF_OUT (...); parameter IOSTANDARD = "DEFAULT"; output O; output OB; + (* iopad_external_pin *) inout IO; + (* iopad_external_pin *) inout IOB; input I; input TM; input TS; endmodule -(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DIFF_OUT_DCIEN (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2349,7 +2386,9 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + (* iopad_external_pin *) inout IO; + (* iopad_external_pin *) inout IOB; input DCITERMDISABLE; input I; @@ -2358,7 +2397,6 @@ module IOBUFDS_DIFF_OUT_DCIEN (...); input TS; endmodule -(* iopad_external_pin = "IO,IOB" *) module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter DIFF_TERM = "FALSE"; parameter DQS_BIAS = "FALSE"; @@ -2368,7 +2406,9 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); parameter USE_IBUFDISABLE = "TRUE"; output O; output OB; + (* iopad_external_pin *) inout IO; + (* iopad_external_pin *) inout IOB; input I; input IBUFDISABLE; @@ -2377,7 +2417,6 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); input TS; endmodule -(* clkbuf_sink = "CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB" *) module ISERDESE2 (...); parameter DATA_RATE = "DDR"; parameter integer DATA_WIDTH = 4; @@ -2417,15 +2456,21 @@ module ISERDESE2 (...); input BITSLIP; input CE1; input CE2; + (* clkbuf_sink *) input CLK; + (* clkbuf_sink *) input CLKB; + (* clkbuf_sink *) input CLKDIV; + (* clkbuf_sink *) input CLKDIVP; input D; input DDLY; input DYNCLKDIVSEL; input DYNCLKSEL; + (* clkbuf_sink *) input OCLK; + (* clkbuf_sink *) input OCLKB; input OFB; input RST; @@ -2444,7 +2489,10 @@ module LDCE (...); parameter MSGON = "TRUE"; parameter XON = "TRUE"; output Q; - input CLR, D, G, GE; + input CLR; + input D; + input G; + input GE; endmodule module LDPE (...); @@ -2454,7 +2502,10 @@ module LDPE (...); parameter MSGON = "TRUE"; parameter XON = "TRUE"; output Q; - input D, G, GE, PRE; + input D; + input G; + input GE; + input PRE; endmodule module MMCME2_ADV (...); @@ -2598,37 +2649,43 @@ module MMCME2_BASE (...); input RST; endmodule -(* iopad_external_pin = "O,OB" *) module OBUFDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; - output O, OB; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; input I; endmodule -(* iopad_external_pin = "O" *) module OBUFT (...); parameter CAPACITANCE = "DONT_CARE"; parameter integer DRIVE = 12; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; + (* iopad_external_pin *) output O; - input I, T; + input I; + input T; endmodule -(* iopad_external_pin = "O,OB" *) module OBUFTDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter IOSTANDARD = "DEFAULT"; parameter SLEW = "SLOW"; - output O, OB; - input I, T; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input I; + input T; endmodule -(* clkbuf_sink = "C" *) module ODDR (...); output Q; + (* clkbuf_sink *) input C; input CE; input D1; @@ -2645,7 +2702,6 @@ module ODDR (...); parameter XON = "TRUE"; endmodule -(* clkbuf_sink = "C" *) module ODELAYE2 (...); parameter CINVCTRL_SEL = "FALSE"; parameter DELAY_SRC = "ODATAIN"; @@ -2660,6 +2716,7 @@ module ODELAYE2 (...); parameter integer SIM_DELAY_D = 0; output [4:0] CNTVALUEOUT; output DATAOUT; + (* clkbuf_sink *) input C; input CE; input CINVCTRL; @@ -2672,7 +2729,6 @@ module ODELAYE2 (...); input REGRST; endmodule -(* clkbuf_sink = "CLK,CLKDIV" *) module OSERDESE2 (...); parameter DATA_RATE_OQ = "DDR"; parameter DATA_RATE_TQ = "DDR"; @@ -2706,7 +2762,9 @@ module OSERDESE2 (...); output TBYTEOUT; output TFB; output TQ; + (* clkbuf_sink *) input CLK; + (* clkbuf_sink *) input CLKDIV; input D1; input D2; @@ -2728,7 +2786,6 @@ module OSERDESE2 (...); input TCE; endmodule -(* clkbuf_sink = "RDCLK,WRCLK" *) module OUT_FIFO (...); parameter integer ALMOST_EMPTY_VALUE = 1; parameter integer ALMOST_FULL_VALUE = 1; @@ -2749,9 +2806,11 @@ module OUT_FIFO (...); output [3:0] Q9; output [7:0] Q5; output [7:0] Q6; + (* clkbuf_sink *) input RDCLK; input RDEN; input RESET; + (* clkbuf_sink *) input WRCLK; input WREN; input [7:0] D0; @@ -3731,26 +3790,34 @@ module PULLUP (...); output O; endmodule -(* clkbuf_sink = "WCLK" *) module RAM128X1S (...); parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; output O; - input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; + input D; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM256X1S (...); parameter [255:0] INIT = 256'h0; parameter [0:0] IS_WCLK_INVERTED = 1'b0; output O; input [7:0] A; input D; + (* clkbuf_sink *) input WCLK; input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM32M (...); parameter [63:0] INIT_A = 64'h0000000000000000; parameter [63:0] INIT_B = 64'h0000000000000000; @@ -3769,36 +3836,59 @@ module RAM32M (...); input [1:0] DIB; input [1:0] DIC; input [1:0] DID; + (* clkbuf_sink *) input WCLK; input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM32X1S (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; output O; - input A0, A1, A2, A3, A4, D, WCLK, WE; + input A0; + input A1; + input A2; + input A3; + input A4; + input D; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM32X1S_1 (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; output O; - input A0, A1, A2, A3, A4, D, WCLK, WE; + input A0; + input A1; + input A2; + input A3; + input A4; + input D; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM32X2S (...); parameter [31:0] INIT_00 = 32'h00000000; parameter [31:0] INIT_01 = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0, O1; - input A0, A1, A2, A3, A4, D0, D1, WCLK, WE; + output O0; + output O1; + input A0; + input A1; + input A2; + input A3; + input A4; + input D0; + input D1; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM64M (...); parameter [63:0] INIT_A = 64'h0000000000000000; parameter [63:0] INIT_B = 64'h0000000000000000; @@ -3817,57 +3907,106 @@ module RAM64M (...); input DIB; input DIC; input DID; + (* clkbuf_sink *) input WCLK; input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM64X1S (...); parameter [63:0] INIT = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; output O; - input A0, A1, A2, A3, A4, A5, D, WCLK, WE; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM64X1S_1 (...); parameter [63:0] INIT = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; output O; - input A0, A1, A2, A3, A4, A5, D, WCLK, WE; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule -(* clkbuf_sink = "WCLK" *) module RAM64X2S (...); parameter [63:0] INIT_00 = 64'h0000000000000000; parameter [63:0] INIT_01 = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0, O1; - input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE; + output O0; + output O1; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D0; + input D1; + (* clkbuf_sink *) + input WCLK; + input WE; endmodule module ROM128X1 (...); parameter [127:0] INIT = 128'h00000000000000000000000000000000; output O; - input A0, A1, A2, A3, A4, A5, A6; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; endmodule module ROM256X1 (...); parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; output O; - input A0, A1, A2, A3, A4, A5, A6, A7; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; + input A7; endmodule module ROM32X1 (...); parameter [31:0] INIT = 32'h00000000; output O; - input A0, A1, A2, A3, A4; + input A0; + input A1; + input A2; + input A3; + input A4; endmodule module ROM64X1 (...); parameter [63:0] INIT = 64'h0000000000000000; output O; - input A0, A1, A2, A3, A4, A5; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; endmodule (* keep *) diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v index 1287e2c53..041d6b54f 100644 --- a/techlibs/xilinx/xc6s_brams_bb.v +++ b/techlibs/xilinx/xc6s_brams_bb.v @@ -1,6 +1,7 @@ -(* clkbuf_sink = "CLKAWRCLK,CLKBRDCLK" *) module RAMB8BWER ( + (* clkbuf_sink *) input CLKAWRCLK, + (* clkbuf_sink *) input CLKBRDCLK, input ENAWREN, input ENBRDEN, @@ -87,9 +88,10 @@ module RAMB8BWER ( parameter SIM_COLLISION_CHECK = "ALL"; endmodule -(* clkbuf_sink = "CLKA,CLKB" *) module RAMB16BWER ( + (* clkbuf_sink *) input CLKA, + (* clkbuf_sink *) input CLKB, input ENA, input ENB, diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index 046a8fa26..a43b4b5a1 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -1,6 +1,7 @@ -(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *) module RAMB18E1 ( + (* clkbuf_sink *) input CLKARDCLK, + (* clkbuf_sink *) input CLKBWRCLK, input ENARDEN, input ENBWREN, @@ -123,9 +124,10 @@ module RAMB18E1 ( parameter SIM_DEVICE = "VIRTEX6"; endmodule -(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *) module RAMB36E1 ( + (* clkbuf_sink *) input CLKARDCLK, + (* clkbuf_sink *) input CLKBWRCLK, input ENARDEN, input ENBWREN, -- cgit v1.2.3 From 562c9e362487e0aa3a3d250a1a0a8cfcf10cafaa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 16 Aug 2019 15:40:53 -0700 Subject: Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules --- techlibs/xilinx/cells_sim.v | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 05e46b4e7..910d0e246 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -181,8 +181,14 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *) -module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); +(* abc_box_id = 4, lib_whitebox *) +module CARRY4( + (* abc_carry_out *) output [3:0] CO, + output [3:0] O, + (* abc_carry_in *) input CI, + input CYINIT, + input [3:0] DI, S +); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; assign CO[1] = S[1] ? CO[0] : DI[1]; @@ -289,10 +295,12 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 5, abc_scc_break="D,WE" *) +(* abc_box_id = 5 *) module RAM32X1D ( output DPO, SPO, - input D, WCLK, WE, + (* abc_scc_break *) input D, + input WCLK, + (* abc_scc_break *) input WE, input A0, A1, A2, A3, A4, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); @@ -307,10 +315,12 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 6, abc_scc_break="D,WE" *) +(* abc_box_id = 6 *) module RAM64X1D ( output DPO, SPO, - input D, WCLK, WE, + (* abc_scc_break *) input D, + input WCLK, + (* abc_scc_break *) input WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); @@ -325,10 +335,12 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 7, abc_scc_break="D,WE" *) +(* abc_box_id = 7 *) module RAM128X1D ( output DPO, SPO, - input D, WCLK, WE, + (* abc_scc_break *) input D, + input WCLK, + (* abc_scc_break *) input WE, input [6:0] A, DPRA ); parameter INIT = 128'h0; -- cgit v1.2.3 From 1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 16 Aug 2019 15:56:57 -0700 Subject: Update abc_* attr in ecp5 and ice40 --- techlibs/ecp5/cells_sim.v | 22 +++++++++++++--------- techlibs/ice40/cells_sim.v | 10 ++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 3d343b315..864a3550f 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z); endmodule // --------------------------------------- -(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *) -module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, COUT); - +(* abc_box_id=1, lib_whitebox *) +module CCU2C( + (* abc_carry_in *) input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + (* abc_carry_out *) output COUT +); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; parameter INJECT1_0 = "YES"; @@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) +//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, WCK, - input [3:0] RAD, + (* abc_scc_break *) input [3:0] DI, + (* abc_scc_break *) input [3:0] WAD, + (* abc_scc_break *) input WRE, + input WCK, + input [3:0] RAD, output [3:0] DO ); parameter WCKMUX = "WCK"; diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2205be27d..5b18fec27 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +(* abc_box_id = 1, lib_whitebox *) +module \$__ICE40_FULL_ADDER ( + (* abc_carry_out *) output CO, + output O, + input A, + input B, + (* abc_carry_in *) input CI +); SB_CARRY carry ( .I0(A), .I1(B), -- cgit v1.2.3 From d81a090d89d87837d3e18f9c724fe5c89ddf1f64 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:56:17 -0700 Subject: Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro --- techlibs/ecp5/cells_sim.v | 4 ++-- techlibs/ice40/cells_sim.v | 4 ++-- techlibs/xilinx/cells_sim.v | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 864a3550f..2fcb0369e 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -17,10 +17,10 @@ endmodule // --------------------------------------- (* abc_box_id=1, lib_whitebox *) module CCU2C( - (* abc_carry_in *) input CIN, + (* abc_carry *) input CIN, input A0, B0, C0, D0, A1, B1, C1, D1, output S0, S1, - (* abc_carry_out *) output COUT + (* abc_carry *) output COUT ); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 5b18fec27..ab04808f4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -143,11 +143,11 @@ endmodule (* abc_box_id = 1, lib_whitebox *) module \$__ICE40_FULL_ADDER ( - (* abc_carry_out *) output CO, + (* abc_carry *) output CO, output O, input A, input B, - (* abc_carry_in *) input CI + (* abc_carry *) input CI ); SB_CARRY carry ( .I0(A), diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 910d0e246..bec9ea1a0 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -183,9 +183,9 @@ endmodule (* abc_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry_out *) output [3:0] CO, + (* abc_carry *) output [3:0] CO, output [3:0] O, - (* abc_carry_in *) input CI, + (* abc_carry *) input CI, input CYINIT, input [3:0] DI, S ); -- cgit v1.2.3 From 076af2e6176ecc440be7b7fa984ea5b461bb95de Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 20:37:52 -0700 Subject: Missing newline --- techlibs/common/synth.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 555de9fba..a176357a7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (abc == "abc9" && !lut) - log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); -- cgit v1.2.3 From 4c449caf9bb7a855b8e61cb96f99f59141ea6ef5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 22 Aug 2019 18:06:36 +0200 Subject: Fix missing newline at end of file Signed-off-by: Clifford Wolf --- techlibs/efinix/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index f1ce58276..5013f7fc1 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v)) -$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt)) \ No newline at end of file +$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt)) -- cgit v1.2.3 From 151db528e44fd12f3c31561df3bb37c12dca48ad Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 22 Aug 2019 18:09:37 +0200 Subject: Fix missing newline at end of file Signed-off-by: Clifford Wolf --- techlibs/anlogic/arith_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index d783b0212..1186543da 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -81,4 +81,4 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); /* End implementation */ assign X = AA ^ BB; -endmodule \ No newline at end of file +endmodule -- cgit v1.2.3 From a270af00cc133ac03ec97cf81ed0a7146b7b225e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:21:44 -0700 Subject: Put abc_* attributes above port --- techlibs/ecp5/cells_sim.v | 15 ++++++++++----- techlibs/ice40/cells_sim.v | 6 ++++-- techlibs/xilinx/cells_sim.v | 21 ++++++++++++++------- 3 files changed, 28 insertions(+), 14 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 2fcb0369e..dc8334acb 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -17,10 +17,12 @@ endmodule // --------------------------------------- (* abc_box_id=1, lib_whitebox *) module CCU2C( - (* abc_carry *) input CIN, + (* abc_carry *) + input CIN, input A0, B0, C0, D0, A1, B1, C1, D1, output S0, S1, - (* abc_carry *) output COUT + (* abc_carry *) + output COUT ); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; @@ -109,9 +111,12 @@ endmodule // --------------------------------------- //(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( - (* abc_scc_break *) input [3:0] DI, - (* abc_scc_break *) input [3:0] WAD, - (* abc_scc_break *) input WRE, + (* abc_scc_break *) + input [3:0] DI, + (* abc_scc_break *) + input [3:0] WAD, + (* abc_scc_break *) + input WRE, input WCK, input [3:0] RAD, output [3:0] DO diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index ab04808f4..c7f3bdad2 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -143,11 +143,13 @@ endmodule (* abc_box_id = 1, lib_whitebox *) module \$__ICE40_FULL_ADDER ( - (* abc_carry *) output CO, + (* abc_carry *) + output CO, output O, input A, input B, - (* abc_carry *) input CI + (* abc_carry *) + input CI ); SB_CARRY carry ( .I0(A), diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index bec9ea1a0..e3897d9a6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -183,9 +183,11 @@ endmodule (* abc_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry *) output [3:0] CO, + (* abc_carry *) + output [3:0] CO, output [3:0] O, - (* abc_carry *) input CI, + (* abc_carry *) + input CI, input CYINIT, input [3:0] DI, S ); @@ -298,9 +300,11 @@ endmodule (* abc_box_id = 5 *) module RAM32X1D ( output DPO, SPO, - (* abc_scc_break *) input D, + (* abc_scc_break *) + input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input A0, A1, A2, A3, A4, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); @@ -318,7 +322,8 @@ endmodule (* abc_box_id = 6 *) module RAM64X1D ( output DPO, SPO, - (* abc_scc_break *) input D, + (* abc_scc_break *) + input D, input WCLK, (* abc_scc_break *) input WE, input A0, A1, A2, A3, A4, A5, @@ -338,9 +343,11 @@ endmodule (* abc_box_id = 7 *) module RAM128X1D ( output DPO, SPO, - (* abc_scc_break *) input D, + (* abc_scc_break *) + input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input [6:0] A, DPRA ); parameter INIT = 128'h0; -- cgit v1.2.3 From 509c353fe981c95ca667a637bf2b47477962a60b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:23:50 -0700 Subject: Forgot one --- techlibs/xilinx/cells_sim.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e3897d9a6..3ad96d7fb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -325,7 +325,8 @@ module RAM64X1D ( (* abc_scc_break *) input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); -- cgit v1.2.3 From d7051b90de19ba0faed0a4eff4af7c3bc92dd3fd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 16:41:32 -0700 Subject: Add undocumented feature --- techlibs/xilinx/synth_xilinx.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7ba67409b..87f4af8f7 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -105,6 +105,7 @@ struct SynthXilinxPass : public ScriptPass std::string top_opt, edif_file, blif_file, family; bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9; + bool flatten_before_abc; int widemux; void clear_flags() YS_OVERRIDE @@ -123,6 +124,7 @@ struct SynthXilinxPass : public ScriptPass nocarry = false; nowidelut = false; abc9 = false; + flatten_before_abc = false; widemux = 0; } @@ -162,6 +164,10 @@ struct SynthXilinxPass : public ScriptPass flatten = true; continue; } + if (args[argidx] == "-flatten_before_abc") { + flatten_before_abc = true; + continue; + } if (args[argidx] == "-retime") { retime = true; continue; @@ -385,6 +391,8 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { run("opt_expr -mux_undef"); + if (flatten_before_abc) + run("flatten"); if (help_mode) run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')"); else if (abc9) { -- cgit v1.2.3 From fc001b473187f13fa0e6f01063ffc9640fb11ef8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 27 Aug 2019 13:07:06 +0100 Subject: ecp5: Add GSR support Signed-off-by: David Shah --- techlibs/ecp5/Makefile.inc | 3 +- techlibs/ecp5/brams_map.v | 10 ++-- techlibs/ecp5/cells_bb.v | 20 +++++++ techlibs/ecp5/cells_map.v | 96 +++++++++++++++---------------- techlibs/ecp5/ecp5_gsr.cc | 135 ++++++++++++++++++++++++++++++++++++++++++++ techlibs/ecp5/synth_ecp5.cc | 2 + 6 files changed, 212 insertions(+), 54 deletions(-) create mode 100644 techlibs/ecp5/ecp5_gsr.cc (limited to 'techlibs') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 73e18112f..c41d16076 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -1,5 +1,6 @@ -OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o +OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \ + techlibs/ecp5/ecp5_gsr.o $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v index b2c136863..0353cbadb 100644 --- a/techlibs/ecp5/brams_map.v +++ b/techlibs/ecp5/brams_map.v @@ -33,7 +33,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), - .GSR("DISABLED") + .GSR("AUTO") ) _TECHMAP_REPLACE_ ( `include "bram_conn_1.vh" .CLKA(CLK2), .CLKB(CLK3), @@ -50,7 +50,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), - .GSR("DISABLED") + .GSR("AUTO") ) _TECHMAP_REPLACE_ ( `include "bram_conn_2.vh" .CLKA(CLK2), .CLKB(CLK3), @@ -67,7 +67,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), - .GSR("DISABLED") + .GSR("AUTO") ) _TECHMAP_REPLACE_ ( `include "bram_conn_4.vh" .CLKA(CLK2), .CLKB(CLK3), @@ -84,7 +84,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), - .GSR("DISABLED") + .GSR("AUTO") ) _TECHMAP_REPLACE_ ( `include "bram_conn_9.vh" .CLKA(CLK2), .CLKB(CLK3), @@ -101,7 +101,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .CLKBMUX(CLKBMUX), .WRITEMODE_A(WRITEMODE_A), .WRITEMODE_B("READBEFOREWRITE"), - .GSR("DISABLED") + .GSR("AUTO") ) _TECHMAP_REPLACE_ ( `include "bram_conn_18.vh" .CLKA(CLK2), .CLKB(CLK3), diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 223e19b9e..8557053b6 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -664,3 +664,23 @@ module PCSCLKDIV ( ); parameter GSR = "DISABLED"; endmodule + +// Note: this module is not marked keep as we want it swept away in synth (sim use only) +(* blackbox *) +module PUR ( + input PUR +); + parameter RST_PULSE = 1; +endmodule + +(* blackbox, keep *) +module GSR ( + input GSR +); +endmodule + +(* blackbox, keep *) +module SGSR ( + input GSR, CLK +); +endmodule \ No newline at end of file diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 6985fbbc8..0a92d906d 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -1,51 +1,51 @@ -module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule - -module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule - -module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule - -module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule - -module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule // TODO: Diamond flip-flops // module FD1P3AX(); endmodule diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc new file mode 100644 index 000000000..8b8927d31 --- /dev/null +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -0,0 +1,135 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2019 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct Ecp5GsrPass : public Pass { + Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ecp5_gsr [options] [selection]\n"); + log("\n"); + log("Trim active low async resets connected to GSR and resolve GSR parameter,\n"); + log("if a GSR or SGSR primitive is used in the design.\n"); + log("\n"); + log("If any cell has the GSR parameter set to \"AUTO\", this will be resolved\n"); + log("to \"ENABLED\" if a GSR primitive is present and the (* nogsr *) attribute\n"); + log("is not set, otherwise it will be resolved to \"DISABLED\".\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-singleton") { + // singleton_mode = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + log("Handling GSR in %s.\n", log_id(module)); + + SigMap sigmap(module); + + SigBit gsr; + bool found_gsr = false; + + for (auto cell : module->selected_cells()) + { + if (cell->type != ID(GSR) && cell->type != ID(SGSR)) + continue; + if (found_gsr) + log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module)); + found_gsr = true; + SigSpec sig_gsr = cell->getPort(ID(GSR)); + if (GetSize(sig_gsr) < 1) + log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell)); + gsr = sigmap(sig_gsr[0]); + } + + // Resolve GSR parameter + + for (auto cell : module->selected_cells()) + { + if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") + continue; + + bool gsren = found_gsr; + if (cell->get_bool_attribute("\\nogsr")) + gsren = false; + cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED")); + + } + + if (!found_gsr) + continue; + + // For finding active low FF inputs + pool inverted_gsr; + + log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr)); + for (auto cell : module->selected_cells()) + { + if (cell->type != ID($_NOT_)) + continue; + SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y)); + if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1) + continue; + SigBit a = sigmap(sig_a[0]); + if (a == gsr) + inverted_gsr.insert(sigmap(sig_y[0])); + } + + for (auto cell : module->selected_cells()) + { + if (cell->type != ID(TRELLIS_FF)) + continue; + if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "ENABLED") + continue; + if (!cell->hasParam(ID(SRMODE)) || cell->getParam(ID(SRMODE)).decode_string() != "ASYNC") + continue; + SigSpec sig_lsr = cell->getPort(ID(LSR)); + if (GetSize(sig_lsr) < 1) + continue; + SigBit lsr = sigmap(sig_lsr[0]); + if (!inverted_gsr.count(lsr)) + continue; + cell->setParam(ID(SRMODE), Const("SYNC")); + cell->unsetPort(ID(LSR)); + } + + } + } +} Ecp5GsrPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 143d1f95c..a8075e86e 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -271,6 +271,8 @@ struct SynthEcp5Pass : public ScriptPass run("opt_expr -undriven -mux_undef"); run("simplemap"); run("ecp5_ffinit"); + run("ecp5_gsr"); + run("opt_clean"); } if (check_label("map_luts")) -- cgit v1.2.3 From d361f5ab795f5b823a594f1fee75f93a78995481 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 27 Aug 2019 18:08:51 +0200 Subject: xilinx: Add SRLC16E primitive. Fixes #1331. --- techlibs/xilinx/cells_sim.v | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index aeef7f885..973e17212 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -394,7 +394,27 @@ module SRL16E ( always @(negedge CLK) if (CE) r <= { r[14:0], D }; end else - always @(posedge CLK) if (CE) r <= { r[14:0], D }; + always @(posedge CLK) if (CE) r <= { r[14:0], D }; + endgenerate +endmodule + +module SRLC16E ( + output Q, + output Q15, + input A0, A1, A2, A3, CE, CLK, D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [15:0] r = INIT; + assign Q15 = r[15]; + assign Q = r[{A3,A2,A1,A0}]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[14:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[14:0], D }; endgenerate endmodule -- cgit v1.2.3 From 9314a0a42ec05e82d2d3d77aebddfb06271a4730 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 10:51:39 -0700 Subject: Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor --- techlibs/xilinx/cells_sim.v | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 973e17212..e12b77c02 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -380,9 +380,10 @@ endmodule module SRL16E ( output Q, + input A0, A1, A2, A3, CE, (* clkbuf_sink *) input CLK, - input A0, A1, A2, A3, CE, D + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -401,7 +402,10 @@ endmodule module SRLC16E ( output Q, output Q15, - input A0, A1, A2, A3, CE, CLK, D + input A0, A1, A2, A3, CE, + (* clkbuf_sink *) + input CLK, + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -422,9 +426,10 @@ module SRLC32E ( output Q, output Q31, input [4:0] A, + input CE, (* clkbuf_sink *) input CLK, - input CE, D + input D ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; -- cgit v1.2.3 From 129df7184a2b85553366f9d56e26ac4eaccc5a52 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:07:07 -0700 Subject: Update to new $__ICE40_CARRY_WRAPPER --- techlibs/ice40/cells_sim.v | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index c7f3bdad2..02726605f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI); endmodule (* abc_box_id = 1, lib_whitebox *) -module \$__ICE40_FULL_ADDER ( +module \$__ICE40_CARRY_WRAPPER ( (* abc_carry *) output CO, output O, - input A, - input B, + input A, B, (* abc_carry *) - input CI + input CI, + input I0, I3, ); + parameter LUT = 0; SB_CARRY carry ( .I0(A), .I1(B), @@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER ( .CO(CO) ); SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) + .LUT_INIT(LUT) ) adder ( - .I0(1'b0), + .I0(I0), .I1(A), .I2(B), - .I3(CI), + .I3(I3), .O(O) ); endmodule -- cgit v1.2.3 From 077e9d4ada7fbc75ab87fe7f390d58e2d53b4472 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:07:24 -0700 Subject: Update box size and timings --- techlibs/ice40/abc_hx.box | 8 ++++---- techlibs/ice40/abc_lp.box | 8 ++++---- techlibs/ice40/abc_u.box | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box index c0ea742e2..571152129 100644 --- a/techlibs/ice40/abc_hx.box +++ b/techlibs/ice40/abc_hx.box @@ -3,11 +3,11 @@ # NB: Inputs/Outputs must be ordered alphabetically # (with exceptions for carry in/out) -# Inputs: A B CI +# Inputs: A B I0 I3 CI # Outputs: O CO # (NB: carry chain input/output must be last # input/output and have been moved there # overriding the alphabetical ordering) -$__ICE40_FULL_ADDER 1 1 3 2 -400 379 316 -259 231 126 +$__ICE40_FULL_ADDER 1 1 5 2 +400 379 449 316 316 +259 231 - - 126 diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box index d73b6d649..a9f8699fc 100644 --- a/techlibs/ice40/abc_lp.box +++ b/techlibs/ice40/abc_lp.box @@ -3,11 +3,11 @@ # NB: Inputs/Outputs must be ordered alphabetically # (with exceptions for carry in/out) -# Inputs: A B CI +# Inputs: A B I0 I3 CI # Outputs: O CO # (NB: carry chain input/output must be last # input/output and have been moved there # overriding the alphabetical ordering) -$__ICE40_FULL_ADDER 1 1 3 2 -589 558 465 -675 609 186 +$__ICE40_FULL_ADDER 1 1 5 2 +589 558 661 465 465 +675 609 - - 186 diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box index 42d666051..bc8a8d9cd 100644 --- a/techlibs/ice40/abc_u.box +++ b/techlibs/ice40/abc_u.box @@ -3,11 +3,11 @@ # NB: Inputs/Outputs must be ordered alphabetically # (with exceptions for carry in/out) -# Inputs: A B CI +# Inputs: A B I0 I3 CI # Outputs: O CO # (NB: carry chain input/output must be last # input/output and have been moved there # overriding the alphabetical ordering) -$__ICE40_FULL_ADDER 1 1 3 2 -1231 1205 874 -675 609 278 +$__ICE40_FULL_ADDER 1 1 5 2 +1231 1205 1285 874 874 +675 609 - - 278 -- cgit v1.2.3 From 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:07:36 -0700 Subject: Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with CARRY_WRAPPER in the same way since I0 and I3 could be used --- techlibs/ice40/ice40_opt.cc | 45 --------------------------------------------- 1 file changed, 45 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index d5106b805..f528607d6 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module) } continue; } - - if (cell->type == "$__ICE40_FULL_ADDER") - { - SigSpec non_const_inputs, replacement_output; - int count_zeros = 0, count_ones = 0; - - SigBit inbit[3] = { - cell->getPort("\\A"), - cell->getPort("\\B"), - cell->getPort("\\CI") - }; - for (int i = 0; i < 3; i++) - if (inbit[i].wire == nullptr) { - if (inbit[i] == State::S1) - count_ones++; - else - count_zeros++; - } else - non_const_inputs.append(inbit[i]); - - if (count_zeros >= 2) - replacement_output = State::S0; - else if (count_ones >= 2) - replacement_output = State::S1; - else if (GetSize(non_const_inputs) == 1) - replacement_output = non_const_inputs; - - if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); - module->connect(cell->getPort("\\CO")[0], replacement_output); - module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", - log_id(module), log_id(cell), log_signal(replacement_output)); - cell->type = "$lut"; - cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); - cell->setPort("\\Y", cell->getPort("\\O")); - cell->unsetPort("\\B"); - cell->unsetPort("\\CI"); - cell->unsetPort("\\CO"); - cell->unsetPort("\\O"); - cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); - cell->setParam("\\WIDTH", 4); - } - continue; - } } for (auto cell : sb_lut_cells) -- cgit v1.2.3 From e569f138704a28654cc52c917bba4decffa29f54 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:22:44 -0700 Subject: Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f. --- techlibs/ice40/ice40_opt.cc | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index f528607d6..d5106b805 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module) } continue; } + + if (cell->type == "$__ICE40_FULL_ADDER") + { + SigSpec non_const_inputs, replacement_output; + int count_zeros = 0, count_ones = 0; + + SigBit inbit[3] = { + cell->getPort("\\A"), + cell->getPort("\\B"), + cell->getPort("\\CI") + }; + for (int i = 0; i < 3; i++) + if (inbit[i].wire == nullptr) { + if (inbit[i] == State::S1) + count_ones++; + else + count_zeros++; + } else + non_const_inputs.append(inbit[i]); + + if (count_zeros >= 2) + replacement_output = State::S0; + else if (count_ones >= 2) + replacement_output = State::S1; + else if (GetSize(non_const_inputs) == 1) + replacement_output = non_const_inputs; + + if (GetSize(replacement_output)) { + optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); + module->connect(cell->getPort("\\CO")[0], replacement_output); + module->design->scratchpad_set_bool("opt.did_something", true); + log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", + log_id(module), log_id(cell), log_signal(replacement_output)); + cell->type = "$lut"; + cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\Y", cell->getPort("\\O")); + cell->unsetPort("\\B"); + cell->unsetPort("\\CI"); + cell->unsetPort("\\CO"); + cell->unsetPort("\\O"); + cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); + cell->setParam("\\WIDTH", 4); + } + continue; + } } for (auto cell : sb_lut_cells) -- cgit v1.2.3 From f5b4bc847c02d6c3e06c086a1375840ccac936cd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:25:05 -0700 Subject: Adapt to $__ICE40_CARRY_WRAPPER --- techlibs/ice40/ice40_opt.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index d5106b805..58f106f7c 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module) continue; } - if (cell->type == "$__ICE40_FULL_ADDER") + if (cell->type == "$__ICE40_CARRY_WRAPPER") { SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; @@ -114,13 +114,15 @@ static void run_ice40_opts(Module *module) optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", + log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); + cell->unsetPort("\\I0"); + cell->unsetPort("\\I3"); cell->unsetPort("\\CO"); cell->unsetPort("\\O"); cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); -- cgit v1.2.3 From d46d38e4d5e1502ea5cb6075161c87bd837af9eb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 17:25:54 -0700 Subject: Trailing comma --- techlibs/ice40/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 02726605f..2a7487f6b 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -149,7 +149,7 @@ module \$__ICE40_CARRY_WRAPPER ( input A, B, (* abc_carry *) input CI, - input I0, I3, + input I0, I3 ); parameter LUT = 0; SB_CARRY carry ( -- cgit v1.2.3 From a4f641f2303bc6f04751a15ec49cf2658ea8eb63 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 18:45:09 -0700 Subject: Do not overwrite LUT param --- techlibs/ice40/ice40_opt.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 58f106f7c..ea56d3f4d 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\I3"); cell->unsetPort("\\CO"); cell->unsetPort("\\O"); - cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); cell->setParam("\\WIDTH", 4); } continue; -- cgit v1.2.3 From 25b1670a8425198abfcef4602a3d1ddcc0ca5d40 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 07:03:32 -0700 Subject: Rename boxes too --- techlibs/ice40/abc_hx.box | 2 +- techlibs/ice40/abc_lp.box | 2 +- techlibs/ice40/abc_u.box | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box index 571152129..3ea70bc91 100644 --- a/techlibs/ice40/abc_hx.box +++ b/techlibs/ice40/abc_hx.box @@ -8,6 +8,6 @@ # (NB: carry chain input/output must be last # input/output and have been moved there # overriding the alphabetical ordering) -$__ICE40_FULL_ADDER 1 1 5 2 +$__ICE40_CARRY_WRAPPER 1 1 5 2 400 379 449 316 316 259 231 - - 126 diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box index a9f8699fc..473e92fe9 100644 --- a/techlibs/ice40/abc_lp.box +++ b/techlibs/ice40/abc_lp.box @@ -8,6 +8,6 @@ # (NB: carry chain input/output must be last # input/output and have been moved there # overriding the alphabetical ordering) -$__ICE40_FULL_ADDER 1 1 5 2 +$__ICE40_CARRY_WRAPPER 1 1 5 2 589 558 661 465 465 675 609 - - 186 diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box index bc8a8d9cd..f00e247b8 100644 --- a/techlibs/ice40/abc_u.box +++ b/techlibs/ice40/abc_u.box @@ -8,6 +8,6 @@ # (NB: carry chain input/output must be last # input/output and have been moved there # overriding the alphabetical ordering) -$__ICE40_FULL_ADDER 1 1 5 2 +$__ICE40_CARRY_WRAPPER 1 1 5 2 1231 1205 1285 874 874 675 609 - - 278 -- cgit v1.2.3