From 9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 Mon Sep 17 00:00:00 2001 From: KrystalDelusion Date: Wed, 24 Aug 2022 10:28:27 +1200 Subject: Fitting help messages to 80 character width Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?\n"); - log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n"); - log(" default: hx\n"); + log(" relevant only for '-abc9' flow, optimise timing for the specified\n"); + log(" device. default: hx\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module\n"); diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 166c81843..e9594e6d8 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -39,21 +39,22 @@ struct SynthIntelPass : public ScriptPass { log(" -family \n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); - log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); - log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n"); + log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use\n"); + log(" cycloneive. For Cyclone V and Cyclone 10 GX, use the synth_intel_alm\n"); + log(" backend instead.\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module (default='top')\n"); log("\n"); log(" -vqm \n"); - log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" write the design to the specified Verilog Quartus Mapping File. Writing\n"); + log(" of an output file is omitted if this parameter is not specified.\n"); log(" Note that this backend has not been tested and is likely incompatible\n"); log(" with recent versions of Quartus.\n"); log("\n"); log(" -vpr \n"); - log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); - log(" compatible with the Quartus flow. Writing of an\n"); + log(" write BLIF files for VPR flow experiments. The synthesized BLIF output\n"); + log(" file is not compatible with the Quartus flow. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); log(" -run :\n"); diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 43d3592d5..c33eb43bf 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -43,21 +43,24 @@ struct SynthIntelALMPass : public ScriptPass { log(" -family \n"); log(" target one of:\n"); log(" \"cyclonev\" - Cyclone V (default)\n"); - log(" \"arriav\" - Arria V (non-GZ)"); + log(" \"arriav\" - Arria V (non-GZ)\n"); log(" \"cyclone10gx\" - Cyclone 10GX\n"); log("\n"); log(" -vqm \n"); - log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); - log(" output file is omitted if this parameter is not specified. Implies -quartus.\n"); + log(" write the design to the specified Verilog Quartus Mapping File. Writing\n"); + log(" of an output file is omitted if this parameter is not specified. Implies\n"); + log(" -quartus.\n"); log("\n"); log(" -noflatten\n"); - log(" do not flatten design before synthesis; useful for per-module area statistics\n"); + log(" do not flatten design before synthesis; useful for per-module area\n"); + log(" statistics\n"); log("\n"); log(" -quartus\n"); log(" output a netlist using Quartus cells instead of MISTRAL_* cells\n"); log("\n"); log(" -dff\n"); - log(" pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n"); + log(" pass DFFs to ABC to perform sequential logic optimisations\n"); + log(" (EXPERIMENTAL)\n"); log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 754de2de6..94bd44db0 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -48,8 +48,8 @@ struct SynthQuickLogicPass : public ScriptPass { log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -verilog \n"); - log(" write the design to the specified verilog file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); + log(" write the design to the specified verilog file. writing of an output\n"); + log(" file is omitted if this parameter is not specified.\n"); log("\n"); log(" -abc\n"); log(" use old ABC flow, which has generally worse mapping results but is less\n"); diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 8d78a6097..f78b4f012 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -45,8 +45,8 @@ struct SynthSf2Pass : public ScriptPass log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -vlog \n"); - log(" write the design to the specified Verilog file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); + log(" write the design to the specified Verilog file. writing of an output\n"); + log(" file is omitted if this parameter is not specified.\n"); log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6214e1411..a242cdef1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -93,7 +93,8 @@ struct SynthXilinxPass : public ScriptPass log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); log("\n"); log(" -nowidelut\n"); - log(" do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n"); + log(" do not use MUXF[5-9] resources to implement LUTs larger than native for\n"); + log(" the target\n"); log("\n"); log(" -nodsp\n"); log(" do not use DSP48*s to implement multipliers and associated logic\n"); @@ -109,8 +110,8 @@ struct SynthXilinxPass : public ScriptPass log(" infer URAM288s for large memories (xcup only)\n"); log("\n"); log(" -widemux \n"); - log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n"); - log(" above this number of inputs (minimum value 2, recommended value >= 5).\n"); + log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n"); + log(" or above this number of inputs (minimum value 2, recommended value >= 5)\n"); log(" default: 0 (no inference)\n"); log("\n"); log(" -run :\n"); -- cgit v1.2.3