From 65c022c2572036a66bd06bafd3e3efa088aafb79 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 20:41:14 -0700 Subject: Remove DFF and RAMD box info for now --- techlibs/xilinx/abc_xc7.box | 34 ---------------------------------- techlibs/xilinx/cells_sim.v | 2 -- 2 files changed, 36 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 8a48bad4e..c9d80a333 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -26,37 +26,3 @@ CARRY4 3 1 10 8 433 469 - - 494 465 445 - - 157 512 548 292 - 592 540 520 356 - 228 508 528 378 380 580 526 507 398 385 114 - -# SLICEM/A6LUT -# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE -# Outputs: DPO SPO -RAM64X1D 4 0 15 2 -- - - - - - - 124 124 124 124 124 124 - - -124 124 124 124 124 124 - - - - - - 124 - - - -# SLICEM/A6LUT + F7[AB]MUX -# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE -# Outputs: DPO SPO -RAM128X1D 5 0 17 2 -- - - - - - - - 314 314 314 314 314 314 292 - - -347 347 347 347 347 347 296 - - - - - - - - - - - -# Inputs: C CE D R -# Outputs: Q -FDRE 6 0 4 1 -- - - - - -# Inputs: C CE D S -# Outputs: Q -FDSE 7 0 4 1 -- - - - - -# Inputs: C CE CLR D -# Outputs: Q -FDCE 8 0 4 1 -- - - - - -# Inputs: C CE D PRE -# Outputs: Q -FDPE 9 0 4 1 -- - - - diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index bf7a0ed44..84939818e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -//(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -299,7 +298,6 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -//(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, -- cgit v1.2.3 From 7903ebe3e004c03e7870f1b21c4fb478481756eb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 22 Jun 2019 14:18:42 -0700 Subject: Carry in/out box ordering now move to end, not swap with end --- techlibs/xilinx/abc_xc7.box | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index c9d80a333..0a6a6eaf0 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -12,17 +12,17 @@ MUXF8 2 1 3 1 104 94 273 # CARRY4 + CARRY4_[ABCD]X -# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI +# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 -# (NB: carry chain input/output must be last input/output, -# swapped with what normally would have been the last -# output, here: CI <-> S, CO <-> O +# (NB: carry chain input/output must be last +# input/output and have been moved there +# overriding the alphabetical ordering) CARRY4 3 1 10 8 -223 - - - 482 - - - - 222 -400 205 - - 598 407 - - - 334 -523 558 226 - 584 556 537 - - 239 -582 618 330 227 642 615 596 438 - 313 -340 - - - 536 379 - - - 271 -433 469 - - 494 465 445 - - 157 -512 548 292 - 592 540 520 356 - 228 -508 528 378 380 580 526 507 398 385 114 +482 - - - - 223 - - - 222 +598 407 - - - 400 205 - - 334 +584 556 537 - - 523 558 226 - 239 +642 615 596 438 - 582 618 330 227 313 +536 379 - - - 340 - - - 271 +494 465 445 - - 433 469 - - 157 +592 540 520 356 - 512 548 292 - 228 +580 526 507 398 385 508 528 378 380 114 -- cgit v1.2.3 From 63182ed57d3a62c8c5e316cea48216024afb38a4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 22 Jun 2019 14:27:41 -0700 Subject: Fix and cleanup ice40 boxes for carry in/out --- techlibs/ice40/abc_hx.box | 112 ++++----------------------------------------- techlibs/ice40/abc_lp.box | 110 +++----------------------------------------- techlibs/ice40/abc_u.box | 112 ++++----------------------------------------- techlibs/ice40/cells_sim.v | 4 +- 4 files changed, 25 insertions(+), 313 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box index a0655643d..f8e12b527 100644 --- a/techlibs/ice40/abc_hx.box +++ b/techlibs/ice40/abc_hx.box @@ -1,113 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt # NB: Inputs/Outputs must be ordered alphabetically +# (with exceptions for carry in/out) -# Inputs: C D -# Outputs: Q -SB_DFF 1 0 2 1 -- - - -# Inputs: C D E -# Outputs: Q -SB_DFFE 2 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFSR 3 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFR 4 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFSS 5 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFS 6 0 3 1 -- - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFESR 7 0 4 1 -- - - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFER 8 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFESS 9 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFES 10 0 4 1 -- - - - - -# Inputs: C D -# Outputs: Q -SB_DFFN 11 0 2 1 -- - - -# Inputs: C D E -# Outputs: Q -SB_DFFNE 12 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFNSR 13 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFNR 14 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFNSS 15 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFNS 16 0 3 1 -- - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFNESR 17 0 4 1 -- - - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFNER 18 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFNESS 19 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFNES 20 0 4 1 -- - - - - -# Inputs: CI I0 I1 +# Inputs: I0 I1 CI # Outputs: CO -SB_CARRY 21 1 3 1 -126 259 231 +# (NB: carry chain input/output must be last +# input/output and have been moved there +# overriding the alphabetical ordering) +SB_CARRY 1 1 3 1 +259 231 126 # Inputs: I0 I1 I2 I3 # Outputs: O -SB_LUT4 22 1 4 1 +SB_LUT4 2 1 4 1 449 400 379 316 diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box index eb1cd0937..fbe4c56e6 100644 --- a/techlibs/ice40/abc_lp.box +++ b/techlibs/ice40/abc_lp.box @@ -1,113 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt # NB: Inputs/Outputs must be ordered alphabetically - -# Inputs: C D -# Outputs: Q -SB_DFF 1 0 2 1 -- - - -# Inputs: C D E -# Outputs: Q -SB_DFFE 2 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFSR 3 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFR 4 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFSS 5 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFS 6 0 3 1 -- - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFESR 7 0 4 1 -- - - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFER 8 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFESS 9 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFES 10 0 4 1 -- - - - - -# Inputs: C D -# Outputs: Q -SB_DFFN 11 0 2 1 -- - - -# Inputs: C D E -# Outputs: Q -SB_DFFNE 12 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFNSR 13 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFNR 14 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFNSS 15 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFNS 16 0 3 1 -- - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFNESR 17 0 4 1 -- - - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFNER 18 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFNESS 19 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFNES 20 0 4 1 -- - - - +# (with exceptions for carry in/out) # Inputs: CI I0 I1 # Outputs: CO -SB_CARRY 21 1 3 1 -186 675 609 +# (NB: carry chain input/output must be last +# input/output and have been moved there +# overriding the alphabetical ordering) +SB_CARRY 1 1 3 1 +675 609 186 # Inputs: I0 I1 I2 I3 # Outputs: O -SB_LUT4 22 1 4 1 +SB_LUT4 2 1 4 1 661 589 558 465 diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box index 3b5834e40..f44deabc4 100644 --- a/techlibs/ice40/abc_u.box +++ b/techlibs/ice40/abc_u.box @@ -1,113 +1,17 @@ # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt # NB: Inputs/Outputs must be ordered alphabetically +# (with exceptions for carry in/out) -# Inputs: C D -# Outputs: Q -SB_DFF 1 0 2 1 -- - - -# Inputs: C D E -# Outputs: Q -SB_DFFE 2 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFSR 3 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFR 4 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFSS 5 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFS 6 0 3 1 -- - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFESR 7 0 4 1 -- - - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFER 8 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFESS 9 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFES 10 0 4 1 -- - - - - -# Inputs: C D -# Outputs: Q -SB_DFFN 11 0 2 1 -- - - -# Inputs: C D E -# Outputs: Q -SB_DFFNE 12 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFNSR 13 0 3 1 -- - - - -# Inputs: C D R -# Outputs: Q -SB_DFFNR 14 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFNSS 15 0 3 1 -- - - - -# Inputs: C D S -# Outputs: Q -SB_DFFNS 16 0 3 1 -- - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFNESR 17 0 4 1 -- - - - - -# Inputs: C D E R -# Outputs: Q -SB_DFFNER 18 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFNESS 19 0 4 1 -- - - - - -# Inputs: C D E S -# Outputs: Q -SB_DFFNES 20 0 4 1 -- - - - - -# Inputs: CI I0 I1 +# Inputs: I0 I1 CI # Outputs: CO -SB_CARRY 21 1 3 1 -278 675 609 +# (NB: carry chain input/output must be last +# input/output and have been moved there +# overriding the alphabetical ordering) +SB_CARRY 1 1 3 1 +675 609 278 # Inputs: I0 I1 I2 I3 # Outputs: O -SB_LUT4 22 1 4 1 +SB_LUT4 2 1 4 1 1285 1231 1205 874 diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 031afa85c..317ae2c1f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,7 +127,7 @@ endmodule // SiliconBlue Logic Cells -(* abc_box_id = 22, lib_whitebox *) +(* abc_box_id = 2, lib_whitebox *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -136,7 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -(* abc_box_id = 21, abc_carry, lib_whitebox *) +(* abc_box_id = 1, abc_carry, lib_whitebox *) module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -- cgit v1.2.3 From 792d0670c3bfe5af7946c6deb0df4656b820d195 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 22 Jun 2019 14:28:24 -0700 Subject: Add comment to xc7 box --- techlibs/xilinx/abc_xc7.box | 3 +++ 1 file changed, 3 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 0a6a6eaf0..b5817a6e0 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -1,5 +1,8 @@ # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf +# NB: Inputs/Outputs must be ordered alphabetically +# (with exceptions for carry in/out) + # F7BMUX slower than F7AMUX # Inputs: I0 I1 S0 # Outputs: O -- cgit v1.2.3 From 6027549464bf91cee4d4bcbe9586e719dce78c80 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 22 Jun 2019 14:33:47 -0700 Subject: Add comments to ecp5 box --- techlibs/ecp5/abc_5g.box | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'techlibs') diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index 72af6d9cb..15e26b5d5 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -1,5 +1,11 @@ +# NB: Inputs/Outputs must be ordered alphabetically +# (with exceptions for carry in/out) + # Box 1 : CCU2C (2xCARRY + 2xLUT4) # Outputs: S0, S1, COUT +# (NB: carry chain input/output must be last +# input/output and have been moved there +# overriding the alphabetical ordering) # name ID w/b ins outs CCU2C 1 1 9 3 -- cgit v1.2.3