From c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 11:06:12 +0200
Subject: Moved all tests in arch sub directory

---
 tests/arch/anlogic/.gitignore  |  4 +++
 tests/arch/anlogic/add_sub.v   | 13 +++++++++
 tests/arch/anlogic/add_sub.ys  | 10 +++++++
 tests/arch/anlogic/counter.v   | 17 +++++++++++
 tests/arch/anlogic/counter.ys  | 11 +++++++
 tests/arch/anlogic/dffs.v      | 15 ++++++++++
 tests/arch/anlogic/dffs.ys     | 20 +++++++++++++
 tests/arch/anlogic/fsm.v       | 55 +++++++++++++++++++++++++++++++++++
 tests/arch/anlogic/fsm.ys      | 15 ++++++++++
 tests/arch/anlogic/latches.v   | 24 ++++++++++++++++
 tests/arch/anlogic/latches.ys  | 33 +++++++++++++++++++++
 tests/arch/anlogic/memory.v    | 21 ++++++++++++++
 tests/arch/anlogic/memory.ys   | 21 ++++++++++++++
 tests/arch/anlogic/mux.v       | 65 ++++++++++++++++++++++++++++++++++++++++++
 tests/arch/anlogic/mux.ys      | 42 +++++++++++++++++++++++++++
 tests/arch/anlogic/run-test.sh | 20 +++++++++++++
 tests/arch/anlogic/shifter.v   | 16 +++++++++++
 tests/arch/anlogic/shifter.ys  | 10 +++++++
 tests/arch/anlogic/tribuf.v    |  8 ++++++
 tests/arch/anlogic/tribuf.ys   |  9 ++++++
 20 files changed, 429 insertions(+)
 create mode 100644 tests/arch/anlogic/.gitignore
 create mode 100644 tests/arch/anlogic/add_sub.v
 create mode 100644 tests/arch/anlogic/add_sub.ys
 create mode 100644 tests/arch/anlogic/counter.v
 create mode 100644 tests/arch/anlogic/counter.ys
 create mode 100644 tests/arch/anlogic/dffs.v
 create mode 100644 tests/arch/anlogic/dffs.ys
 create mode 100644 tests/arch/anlogic/fsm.v
 create mode 100644 tests/arch/anlogic/fsm.ys
 create mode 100644 tests/arch/anlogic/latches.v
 create mode 100644 tests/arch/anlogic/latches.ys
 create mode 100644 tests/arch/anlogic/memory.v
 create mode 100644 tests/arch/anlogic/memory.ys
 create mode 100644 tests/arch/anlogic/mux.v
 create mode 100644 tests/arch/anlogic/mux.ys
 create mode 100755 tests/arch/anlogic/run-test.sh
 create mode 100644 tests/arch/anlogic/shifter.v
 create mode 100644 tests/arch/anlogic/shifter.ys
 create mode 100644 tests/arch/anlogic/tribuf.v
 create mode 100644 tests/arch/anlogic/tribuf.ys

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/.gitignore b/tests/arch/anlogic/.gitignore
new file mode 100644
index 000000000..9a71dca69
--- /dev/null
+++ b/tests/arch/anlogic/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v
new file mode 100644
index 000000000..177c32e30
--- /dev/null
+++ b/tests/arch/anlogic/add_sub.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x + y;
+assign B =  x - y;
+
+endmodule
diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys
new file mode 100644
index 000000000..b8b67cc46
--- /dev/null
+++ b/tests/arch/anlogic/add_sub.ys
@@ -0,0 +1,10 @@
+read_verilog add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 10 t:AL_MAP_ADDER
+select -assert-count 4 t:AL_MAP_LUT1
+
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v
new file mode 100644
index 000000000..52852f8ac
--- /dev/null
+++ b/tests/arch/anlogic/counter.v
@@ -0,0 +1,17 @@
+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (reset) begin
+			out <= 8'b0 ;
+		end else
+			out <= out + 1;
+
+
+endmodule
diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
new file mode 100644
index 000000000..036fdba46
--- /dev/null
+++ b/tests/arch/anlogic/counter.ys
@@ -0,0 +1,11 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:AL_MAP_ADDER
+select -assert-count 8 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D
diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v
new file mode 100644
index 000000000..3418787c9
--- /dev/null
+++ b/tests/arch/anlogic/dffs.v
@@ -0,0 +1,15 @@
+module dff
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys
new file mode 100644
index 000000000..9cbe5fce7
--- /dev/null
+++ b/tests/arch/anlogic/dffs.ys
@@ -0,0 +1,20 @@
+read_verilog dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_SEQ %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+select -assert-count 1 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v
new file mode 100644
index 000000000..368fbaace
--- /dev/null
+++ b/tests/arch/anlogic/fsm.v
@@ -0,0 +1,55 @@
+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+                 gnt_0 <= 1;
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end
+    default : state <=  #1  IDLE;
+ endcase
+ end
+
+endmodule
diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
new file mode 100644
index 000000000..452ef9251
--- /dev/null
+++ b/tests/arch/anlogic/fsm.ys
@@ -0,0 +1,15 @@
+read_verilog fsm.v
+hierarchy -top fsm
+proc
+#flatten
+#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
+#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT2
+select -assert-count 5 t:AL_MAP_LUT5
+select -assert-count 1 t:AL_MAP_LUT6
+select -assert-count 6 t:AL_MAP_SEQ
+
+select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v
new file mode 100644
index 000000000..adb5d5319
--- /dev/null
+++ b/tests/arch/anlogic/latches.v
@@ -0,0 +1,24 @@
+module latchp
+    ( input d, clk, en, output reg q );
+	always @*
+		if ( en )
+			q <= d;
+endmodule
+
+module latchn
+    ( input d, clk, en, output reg q );
+	always @*
+		if ( !en )
+			q <= d;
+endmodule
+
+module latchsr
+    ( input d, clk, en, clr, pre, output reg q );
+	always @*
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else if ( en )
+			q <= d;
+endmodule
diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys
new file mode 100644
index 000000000..c00c7a25d
--- /dev/null
+++ b/tests/arch/anlogic/latches.ys
@@ -0,0 +1,33 @@
+read_verilog latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_anlogic
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+
+select -assert-none t:AL_MAP_LUT3 %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_anlogic
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+
+select -assert-none t:AL_MAP_LUT3 %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_anlogic
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT5
+
+select -assert-none t:AL_MAP_LUT5 %% t:* %D
diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v
new file mode 100644
index 000000000..cb7753f7b
--- /dev/null
+++ b/tests/arch/anlogic/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		q_a <= ram[addr_a];
+	end
+endmodule
diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys
new file mode 100644
index 000000000..8c0ce844e
--- /dev/null
+++ b/tests/arch/anlogic/memory.ys
@@ -0,0 +1,21 @@
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database.
+#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+
+select -assert-count 8  t:AL_MAP_LUT2
+select -assert-count 8  t:AL_MAP_LUT4
+select -assert-count 8   t:AL_MAP_LUT5
+select -assert-count 36 t:AL_MAP_SEQ
+select -assert-count 8  t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
+select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v
new file mode 100644
index 000000000..27bc0bf0b
--- /dev/null
+++ b/tests/arch/anlogic/mux.v
@@ -0,0 +1,65 @@
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys
new file mode 100644
index 000000000..64ed2a2bd
--- /dev/null
+++ b/tests/arch/anlogic/mux.ys
@@ -0,0 +1,42 @@
+read_verilog mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+
+select -assert-none t:AL_MAP_LUT3 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT6
+
+select -assert-none t:AL_MAP_LUT6 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 3 t:AL_MAP_LUT4
+select -assert-count 1 t:AL_MAP_LUT6
+
+select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 5 t:AL_MAP_LUT6
+
+select -assert-none t:AL_MAP_LUT6 %% t:* %D
diff --git a/tests/arch/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh
new file mode 100755
index 000000000..46716f9a0
--- /dev/null
+++ b/tests/arch/anlogic/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v
new file mode 100644
index 000000000..04ae49d83
--- /dev/null
+++ b/tests/arch/anlogic/shifter.v
@@ -0,0 +1,16 @@
+module top    (
+out,
+clk,
+in
+);
+    output [7:0] out;
+    input signed clk, in;
+    reg signed [7:0] out = 0;
+
+    always @(posedge clk)
+	begin
+		out    <= out >> 1;
+		out[7] <= in;
+	end
+
+endmodule
diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys
new file mode 100644
index 000000000..5eaed30a3
--- /dev/null
+++ b/tests/arch/anlogic/shifter.ys
@@ -0,0 +1,10 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:AL_MAP_SEQ
+
+select -assert-none t:AL_MAP_SEQ %% t:* %D
diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v
new file mode 100644
index 000000000..90dd314e4
--- /dev/null
+++ b/tests/arch/anlogic/tribuf.v
@@ -0,0 +1,8 @@
+module tristate (en, i, o);
+    input en;
+    input i;
+    output o;
+
+	assign o = en ? i : 1'bz;
+
+endmodule
diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys
new file mode 100644
index 000000000..0eb1338ac
--- /dev/null
+++ b/tests/arch/anlogic/tribuf.ys
@@ -0,0 +1,9 @@
+read_verilog tribuf.v
+hierarchy -top tristate
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From 56f94826753c1f26c9026493a40ecef14806d779 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 11:12:03 +0200
Subject: Fix path to yosys

---
 tests/arch/anlogic/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh
index 46716f9a0..bf19b887d 100755
--- a/tests/arch/anlogic/run-test.sh
+++ b/tests/arch/anlogic/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-- 
cgit v1.2.3


From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 12:19:59 +0200
Subject: Share common tests

---
 tests/arch/anlogic/add_sub.v  | 13 ---------
 tests/arch/anlogic/add_sub.ys |  2 +-
 tests/arch/anlogic/counter.v  | 17 -----------
 tests/arch/anlogic/counter.ys |  2 +-
 tests/arch/anlogic/dffs.v     | 15 ----------
 tests/arch/anlogic/dffs.ys    |  2 +-
 tests/arch/anlogic/fsm.v      | 55 ------------------------------------
 tests/arch/anlogic/fsm.ys     |  2 +-
 tests/arch/anlogic/latches.v  | 24 ----------------
 tests/arch/anlogic/latches.ys |  2 +-
 tests/arch/anlogic/logic.ys   | 11 ++++++++
 tests/arch/anlogic/mux.v      | 65 -------------------------------------------
 tests/arch/anlogic/mux.ys     |  2 +-
 tests/arch/anlogic/shifter.v  | 16 -----------
 tests/arch/anlogic/shifter.ys |  2 +-
 tests/arch/anlogic/tribuf.v   |  8 ------
 tests/arch/anlogic/tribuf.ys  |  2 +-
 17 files changed, 19 insertions(+), 221 deletions(-)
 delete mode 100644 tests/arch/anlogic/add_sub.v
 delete mode 100644 tests/arch/anlogic/counter.v
 delete mode 100644 tests/arch/anlogic/dffs.v
 delete mode 100644 tests/arch/anlogic/fsm.v
 delete mode 100644 tests/arch/anlogic/latches.v
 create mode 100644 tests/arch/anlogic/logic.ys
 delete mode 100644 tests/arch/anlogic/mux.v
 delete mode 100644 tests/arch/anlogic/shifter.v
 delete mode 100644 tests/arch/anlogic/tribuf.v

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v
deleted file mode 100644
index 177c32e30..000000000
--- a/tests/arch/anlogic/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys
index b8b67cc46..5396ce7ec 100644
--- a/tests/arch/anlogic/add_sub.ys
+++ b/tests/arch/anlogic/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v
deleted file mode 100644
index 52852f8ac..000000000
--- a/tests/arch/anlogic/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
index 036fdba46..d363ec24e 100644
--- a/tests/arch/anlogic/counter.ys
+++ b/tests/arch/anlogic/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v
deleted file mode 100644
index 3418787c9..000000000
--- a/tests/arch/anlogic/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys
index 9cbe5fce7..d3281ab89 100644
--- a/tests/arch/anlogic/dffs.ys
+++ b/tests/arch/anlogic/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v
deleted file mode 100644
index 368fbaace..000000000
--- a/tests/arch/anlogic/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule
diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index 452ef9251..f45951b13 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 #flatten
diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v
deleted file mode 100644
index adb5d5319..000000000
--- a/tests/arch/anlogic/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys
index c00c7a25d..8d66f77b3 100644
--- a/tests/arch/anlogic/latches.ys
+++ b/tests/arch/anlogic/latches.ys
@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys
new file mode 100644
index 000000000..125ee5d0f
--- /dev/null
+++ b/tests/arch/anlogic/logic.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT1
+select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 2 t:AL_MAP_LUT4
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D
diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v
deleted file mode 100644
index 27bc0bf0b..000000000
--- a/tests/arch/anlogic/mux.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys
index 64ed2a2bd..3d5fe7c9a 100644
--- a/tests/arch/anlogic/mux.ys
+++ b/tests/arch/anlogic/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v
deleted file mode 100644
index 04ae49d83..000000000
--- a/tests/arch/anlogic/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out >> 1;
-		out[7] <= in;
-	end
-
-endmodule
diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys
index 5eaed30a3..12df44b2a 100644
--- a/tests/arch/anlogic/shifter.ys
+++ b/tests/arch/anlogic/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v
deleted file mode 100644
index 90dd314e4..000000000
--- a/tests/arch/anlogic/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys
index 0eb1338ac..eaa073750 100644
--- a/tests/arch/anlogic/tribuf.ys
+++ b/tests/arch/anlogic/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten
-- 
cgit v1.2.3


From 12383f37b2e1d72784e01db0431efc8882f25430 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 12:33:35 +0200
Subject: Common memory test now shared

---
 tests/arch/anlogic/memory.v  | 21 ---------------------
 tests/arch/anlogic/memory.ys |  2 +-
 2 files changed, 1 insertion(+), 22 deletions(-)
 delete mode 100644 tests/arch/anlogic/memory.v

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v
deleted file mode 100644
index cb7753f7b..000000000
--- a/tests/arch/anlogic/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys
index 8c0ce844e..87b93c2fe 100644
--- a/tests/arch/anlogic/memory.ys
+++ b/tests/arch/anlogic/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap
-- 
cgit v1.2.3


From 3e0ffe05a79d3196b3644cddf422edb927673b04 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Nov 2019 15:41:33 +0100
Subject: Fixed tests

---
 tests/arch/anlogic/fsm.ys | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index f45951b13..0bcc4e011 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -1,12 +1,15 @@
 read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
-#flatten
-#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
-#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+flatten
+
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
+
 select -assert-count 1 t:AL_MAP_LUT2
 select -assert-count 5 t:AL_MAP_LUT5
 select -assert-count 1 t:AL_MAP_LUT6
-- 
cgit v1.2.3