From caab66111e2b5052bd26c8fd64b1324e7e4a4106 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 17:44:37 -0800
Subject: Rename memory tests to lutram, add more xilinx tests

---
 tests/arch/anlogic/lutram.ys | 21 +++++++++++++++++++++
 tests/arch/anlogic/memory.ys | 21 ---------------------
 2 files changed, 21 insertions(+), 21 deletions(-)
 create mode 100644 tests/arch/anlogic/lutram.ys
 delete mode 100644 tests/arch/anlogic/memory.ys

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys
new file mode 100644
index 000000000..9ebb75443
--- /dev/null
+++ b/tests/arch/anlogic/lutram.ys
@@ -0,0 +1,21 @@
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+proc
+memory -nomap
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database.
+#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+
+select -assert-count 8  t:AL_MAP_LUT2
+select -assert-count 8  t:AL_MAP_LUT4
+select -assert-count 8   t:AL_MAP_LUT5
+select -assert-count 36 t:AL_MAP_SEQ
+select -assert-count 8  t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
+select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys
deleted file mode 100644
index 87b93c2fe..000000000
--- a/tests/arch/anlogic/memory.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog ../common/memory.v
-hierarchy -top top
-proc
-memory -nomap
-equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database.
-#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd top
-
-select -assert-count 8  t:AL_MAP_LUT2
-select -assert-count 8  t:AL_MAP_LUT4
-select -assert-count 8   t:AL_MAP_LUT5
-select -assert-count 36 t:AL_MAP_SEQ
-select -assert-count 8  t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
-select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
-- 
cgit v1.2.3


From c082329af33cd428f53f5afbcb51fab8de545090 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:39:32 -0800
Subject: Call equiv_opt with -multiclock and -assert

---
 tests/arch/anlogic/counter.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/arch/anlogic')

diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
index d363ec24e..a6eab248c 100644
--- a/tests/arch/anlogic/counter.ys
+++ b/tests/arch/anlogic/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-- 
cgit v1.2.3