From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 12:19:59 +0200
Subject: Share common tests

---
 tests/arch/common/adffs.v | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 tests/arch/common/adffs.v

(limited to 'tests/arch/common/adffs.v')

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
new file mode 100644
index 000000000..223b52d21
--- /dev/null
+++ b/tests/arch/common/adffs.v
@@ -0,0 +1,47 @@
+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffs
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
-- 
cgit v1.2.3


From 9bd9db56c8ef8ca413f97086fd53609c50df343b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 12:50:24 +0200
Subject: Unify verilog style

---
 tests/arch/common/adffs.v | 54 ++++++++++++++++++++++-------------------------
 1 file changed, 25 insertions(+), 29 deletions(-)

(limited to 'tests/arch/common/adffs.v')

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 223b52d21..576bd81a6 100644
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,47 +1,43 @@
-module adff
-    ( input d, clk, clr, output reg q );
+module adff( input d, clk, clr, output reg q );
     initial begin
-      q = 0;
+        q = 0;
     end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
+	  always @( posedge clk, posedge clr )
+      if ( clr )
+        q <= 1'b0;
+      else
+        q <= d;
 endmodule
 
-module adffn
-    ( input d, clk, clr, output reg q );
+module adffn( input d, clk, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
+	  always @( posedge clk, negedge clr )
+		  if ( !clr )
+			  q <= 1'b0;
+  		else
+        q <= d;
 endmodule
 
-module dffs
-    ( input d, clk, pre, clr, output reg q );
+module dffs( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
+    always @( posedge clk )
+      if ( pre )
+        q <= 1'b1;
+      else
+        q <= d;
 endmodule
 
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
+module ndffnr( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
+    always @( negedge clk )
+      if ( !clr )
+        q <= 1'b0;
+      else
+        q <= d;
 endmodule
-- 
cgit v1.2.3