From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: Share common tests --- tests/arch/common/logic.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 tests/arch/common/logic.v (limited to 'tests/arch/common/logic.v') diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/arch/common/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule -- cgit v1.2.3 From 9bd9db56c8ef8ca413f97086fd53609c50df343b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:50:24 +0200 Subject: Unify verilog style --- tests/arch/common/logic.v | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) (limited to 'tests/arch/common/logic.v') diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v index e5343cae0..c17899fa0 100644 --- a/tests/arch/common/logic.v +++ b/tests/arch/common/logic.v @@ -1,18 +1,16 @@ module top ( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 +); + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; endmodule -- cgit v1.2.3