From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: Share common tests --- tests/arch/common/mux.v | 65 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/arch/common/mux.v (limited to 'tests/arch/common/mux.v') diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/common/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule -- cgit v1.2.3 From 9bd9db56c8ef8ca413f97086fd53609c50df343b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:50:24 +0200 Subject: Unify verilog style --- tests/arch/common/mux.v | 83 +++++++++++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 44 deletions(-) (limited to 'tests/arch/common/mux.v') diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v index 27bc0bf0b..71c1ac7f2 100644 --- a/tests/arch/common/mux.v +++ b/tests/arch/common/mux.v @@ -8,51 +8,47 @@ module mux2 (S,A,B,Y); endmodule module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - + input[1:0] S; + input[3:0] D; + output Y; + + reg Y; + wire[1:0] S; + wire[3:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase + end endmodule module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - + input[2:0] S; + input[7:0] D; + output Y; + + reg Y; + wire[2:0] S; + wire[7:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase + end endmodule module mux16 (D, S, Y); @@ -60,6 +56,5 @@ module mux16 (D, S, Y); input [3:0] S; output Y; -assign Y = D[S]; - + assign Y = D[S]; endmodule -- cgit v1.2.3