From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: Share common tests --- tests/arch/common/shifter.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 tests/arch/common/shifter.v (limited to 'tests/arch/common/shifter.v') diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/common/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule -- cgit v1.2.3 From 9bd9db56c8ef8ca413f97086fd53609c50df343b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:50:24 +0200 Subject: Unify verilog style --- tests/arch/common/shifter.v | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'tests/arch/common/shifter.v') diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index 04ae49d83..cace3b588 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,8 +1,4 @@ -module top ( -out, -clk, -in -); +module top(out, clk, in); output [7:0] out; input signed clk, in; reg signed [7:0] out = 0; @@ -11,6 +7,5 @@ in begin out <= out >> 1; out[7] <= in; - end - + end endmodule -- cgit v1.2.3