From c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:06:12 +0200 Subject: Moved all tests in arch sub directory --- tests/arch/efinix/logic.ys | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/arch/efinix/logic.ys (limited to 'tests/arch/efinix/logic.ys') diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys new file mode 100644 index 000000000..fdedb337b --- /dev/null +++ b/tests/arch/efinix/logic.ys @@ -0,0 +1,9 @@ +read_verilog logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D -- cgit v1.2.3 From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: Share common tests --- tests/arch/efinix/logic.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/arch/efinix/logic.ys') diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys index fdedb337b..76e98e079 100644 --- a/tests/arch/efinix/logic.ys +++ b/tests/arch/efinix/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -- cgit v1.2.3