From c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:06:12 +0200 Subject: Moved all tests in arch sub directory --- tests/arch/ice40/.gitignore | 4 ++ tests/arch/ice40/add_sub.v | 13 ++++++ tests/arch/ice40/add_sub.ys | 9 ++++ tests/arch/ice40/adffs.v | 87 ++++++++++++++++++++++++++++++++++++ tests/arch/ice40/adffs.ys | 11 +++++ tests/arch/ice40/alu.v | 19 ++++++++ tests/arch/ice40/alu.ys | 11 +++++ tests/arch/ice40/counter.v | 17 +++++++ tests/arch/ice40/counter.ys | 11 +++++ tests/arch/ice40/dffs.v | 37 ++++++++++++++++ tests/arch/ice40/dffs.ys | 10 +++++ tests/arch/ice40/div_mod.v | 13 ++++++ tests/arch/ice40/div_mod.ys | 9 ++++ tests/arch/ice40/dpram.v | 23 ++++++++++ tests/arch/ice40/dpram.ys | 15 +++++++ tests/arch/ice40/fsm.v | 73 ++++++++++++++++++++++++++++++ tests/arch/ice40/fsm.ys | 13 ++++++ tests/arch/ice40/ice40_opt.ys | 26 +++++++++++ tests/arch/ice40/latches.v | 58 ++++++++++++++++++++++++ tests/arch/ice40/latches.ys | 12 +++++ tests/arch/ice40/logic.v | 18 ++++++++ tests/arch/ice40/logic.ys | 7 +++ tests/arch/ice40/macc.v | 47 ++++++++++++++++++++ tests/arch/ice40/macc.ys | 25 +++++++++++ tests/arch/ice40/memory.v | 21 +++++++++ tests/arch/ice40/memory.ys | 15 +++++++ tests/arch/ice40/mul.v | 11 +++++ tests/arch/ice40/mul.ys | 7 +++ tests/arch/ice40/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++++ tests/arch/ice40/mux.ys | 8 ++++ tests/arch/ice40/rom.v | 18 ++++++++ tests/arch/ice40/rom.ys | 8 ++++ tests/arch/ice40/run-test.sh | 20 +++++++++ tests/arch/ice40/shifter.v | 22 ++++++++++ tests/arch/ice40/shifter.ys | 9 ++++ tests/arch/ice40/tribuf.v | 23 ++++++++++ tests/arch/ice40/tribuf.ys | 9 ++++ tests/arch/ice40/wrapcarry.ys | 22 ++++++++++ 38 files changed, 861 insertions(+) create mode 100644 tests/arch/ice40/.gitignore create mode 100644 tests/arch/ice40/add_sub.v create mode 100644 tests/arch/ice40/add_sub.ys create mode 100644 tests/arch/ice40/adffs.v create mode 100644 tests/arch/ice40/adffs.ys create mode 100644 tests/arch/ice40/alu.v create mode 100644 tests/arch/ice40/alu.ys create mode 100644 tests/arch/ice40/counter.v create mode 100644 tests/arch/ice40/counter.ys create mode 100644 tests/arch/ice40/dffs.v create mode 100644 tests/arch/ice40/dffs.ys create mode 100644 tests/arch/ice40/div_mod.v create mode 100644 tests/arch/ice40/div_mod.ys create mode 100644 tests/arch/ice40/dpram.v create mode 100644 tests/arch/ice40/dpram.ys create mode 100644 tests/arch/ice40/fsm.v create mode 100644 tests/arch/ice40/fsm.ys create mode 100644 tests/arch/ice40/ice40_opt.ys create mode 100644 tests/arch/ice40/latches.v create mode 100644 tests/arch/ice40/latches.ys create mode 100644 tests/arch/ice40/logic.v create mode 100644 tests/arch/ice40/logic.ys create mode 100644 tests/arch/ice40/macc.v create mode 100644 tests/arch/ice40/macc.ys create mode 100644 tests/arch/ice40/memory.v create mode 100644 tests/arch/ice40/memory.ys create mode 100644 tests/arch/ice40/mul.v create mode 100644 tests/arch/ice40/mul.ys create mode 100644 tests/arch/ice40/mux.v create mode 100644 tests/arch/ice40/mux.ys create mode 100644 tests/arch/ice40/rom.v create mode 100644 tests/arch/ice40/rom.ys create mode 100755 tests/arch/ice40/run-test.sh create mode 100644 tests/arch/ice40/shifter.v create mode 100644 tests/arch/ice40/shifter.ys create mode 100644 tests/arch/ice40/tribuf.v create mode 100644 tests/arch/ice40/tribuf.ys create mode 100644 tests/arch/ice40/wrapcarry.ys (limited to 'tests/arch/ice40') diff --git a/tests/arch/ice40/.gitignore b/tests/arch/ice40/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/ice40/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/ice40/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys new file mode 100644 index 000000000..4a998d98d --- /dev/null +++ b/tests/arch/ice40/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v new file mode 100644 index 000000000..09dc36001 --- /dev/null +++ b/tests/arch/ice40/adffs.v @@ -0,0 +1,87 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre ) + if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffs u_dffs ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnr u_ndffnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys new file mode 100644 index 000000000..548060b66 --- /dev/null +++ b/tests/arch/ice40/adffs.ys @@ -0,0 +1,11 @@ +read_verilog adffs.v +proc +flatten +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNS +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/arch/ice40/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/arch/ice40/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/ice40/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/arch/ice40/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/arch/ice40/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys new file mode 100644 index 000000000..ee7f884b1 --- /dev/null +++ b/tests/arch/ice40/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF +select -assert-count 1 t:SB_DFFE +select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/arch/ice40/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys new file mode 100644 index 000000000..821d6c301 --- /dev/null +++ b/tests/arch/ice40/div_mod.ys @@ -0,0 +1,9 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 59 t:SB_LUT4 +select -assert-count 41 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/arch/ice40/dpram.v b/tests/arch/ice40/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/arch/ice40/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/arch/ice40/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/arch/ice40/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/arch/ice40/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys new file mode 100644 index 000000000..d1e1b3108 --- /dev/null +++ b/tests/arch/ice40/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/arch/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog < Date: Fri, 18 Oct 2019 11:12:03 +0200 Subject: Fix path to yosys --- tests/arch/ice40/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/arch/ice40') diff --git a/tests/arch/ice40/run-test.sh b/tests/arch/ice40/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/ice40/run-test.sh +++ b/tests/arch/ice40/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: Share common tests --- tests/arch/ice40/add_sub.v | 13 ------ tests/arch/ice40/add_sub.ys | 2 +- tests/arch/ice40/adffs.v | 87 -------------------------------------- tests/arch/ice40/adffs.ys | 46 ++++++++++++++++---- tests/arch/ice40/counter.v | 17 -------- tests/arch/ice40/counter.ys | 2 +- tests/arch/ice40/dffs.v | 37 ---------------- tests/arch/ice40/dffs.ys | 19 ++++++--- tests/arch/ice40/fsm.v | 73 -------------------------------- tests/arch/ice40/fsm.ys | 6 +-- tests/arch/ice40/latches.v | 58 ------------------------- tests/arch/ice40/latches.ys | 33 ++++++++++++--- tests/arch/ice40/logic.v | 18 -------- tests/arch/ice40/logic.ys | 2 +- tests/arch/ice40/mul.v | 11 ----- tests/arch/ice40/mul.ys | 2 +- tests/arch/ice40/mux.v | 100 -------------------------------------------- tests/arch/ice40/mux.ys | 40 ++++++++++++++++-- tests/arch/ice40/shifter.v | 22 ---------- tests/arch/ice40/shifter.ys | 2 +- tests/arch/ice40/tribuf.v | 23 ---------- tests/arch/ice40/tribuf.ys | 8 ++-- 22 files changed, 127 insertions(+), 494 deletions(-) delete mode 100644 tests/arch/ice40/add_sub.v delete mode 100644 tests/arch/ice40/adffs.v delete mode 100644 tests/arch/ice40/counter.v delete mode 100644 tests/arch/ice40/dffs.v delete mode 100644 tests/arch/ice40/fsm.v delete mode 100644 tests/arch/ice40/latches.v delete mode 100644 tests/arch/ice40/logic.v delete mode 100644 tests/arch/ice40/mul.v delete mode 100644 tests/arch/ice40/mux.v delete mode 100644 tests/arch/ice40/shifter.v delete mode 100644 tests/arch/ice40/tribuf.v (limited to 'tests/arch/ice40') diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/ice40/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys index 4a998d98d..578ec0803 100644 --- a/tests/arch/ice40/add_sub.ys +++ b/tests/arch/ice40/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v deleted file mode 100644 index 09dc36001..000000000 --- a/tests/arch/ice40/adffs.v +++ /dev/null @@ -1,87 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre ) - if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys index 548060b66..e5dbabb43 100644 --- a/tests/arch/ice40/adffs.ys +++ b/tests/arch/ice40/adffs.ys @@ -1,11 +1,39 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff proc -flatten -equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNS -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFS -select -assert-count 2 t:SB_LUT4 -select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-none t:SB_DFFR %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFSS +select -assert-none t:SB_DFFSS %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNSR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/ice40/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index c65c21622..f112eb97d 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/arch/ice40/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys index ee7f884b1..b28a5a91f 100644 --- a/tests/arch/ice40/dffs.ys +++ b/tests/arch/ice40/dffs.ys @@ -1,10 +1,19 @@ -read_verilog dffs.v -hierarchy -top top +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFFE -select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D +select -assert-none t:SB_DFFE %% t:* %D \ No newline at end of file diff --git a/tests/arch/ice40/fsm.v b/tests/arch/ice40/fsm.v deleted file mode 100644 index 0605bd102..000000000 --- a/tests/arch/ice40/fsm.v +++ /dev/null @@ -1,73 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - -endmodule diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 4cc8629d6..5aacc6c73 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -1,10 +1,10 @@ -read_verilog fsm.v -hierarchy -top top +read_verilog ../common/fsm.v +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 2 t:SB_DFFESR select -assert-count 2 t:SB_DFFSR diff --git a/tests/arch/ice40/latches.v b/tests/arch/ice40/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/arch/ice40/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys index 708734e44..b06dd630b 100644 --- a/tests/arch/ice40/latches.ys +++ b/tests/arch/ice40/latches.ys @@ -1,12 +1,33 @@ -read_verilog latches.v +read_verilog ../common/latches.v +design -save read +hierarchy -top latchp proc -flatten # Can't run any sort of equivalence check because latches are blown to LUTs -#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +synth_ice40 +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + -#design -load preopt +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ice40 -cd top -select -assert-count 4 t:SB_LUT4 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/logic.v b/tests/arch/ice40/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/ice40/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/ice40/logic.ys b/tests/arch/ice40/logic.ys index fc5e5b1d8..7432f5b1f 100644 --- a/tests/arch/ice40/logic.ys +++ b/tests/arch/ice40/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/mul.v b/tests/arch/ice40/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/arch/ice40/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 8a0822a84..9891b77d6 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/mux.v b/tests/arch/ice40/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/arch/ice40/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 182b49499..99822391d 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -1,8 +1,40 @@ -read_verilog mux.v +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 19 t:SB_LUT4 +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v deleted file mode 100644 index c55632552..000000000 --- a/tests/arch/ice40/shifter.v +++ /dev/null @@ -1,22 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin -`ifndef BUG - out <= out >> 1; - out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif - end - -endmodule diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys index 47d95d298..08ea64f3d 100644 --- a/tests/arch/ice40/shifter.ys +++ b/tests/arch/ice40/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/arch/ice40/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys index d1e1b3108..10cded954 100644 --- a/tests/arch/ice40/tribuf.ys +++ b/tests/arch/ice40/tribuf.ys @@ -1,9 +1,11 @@ -read_verilog tribuf.v -hierarchy -top top +read_verilog ../common/tribuf.v +hierarchy -top tristate proc +tribuf flatten +synth equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 477702b8c91bb7780ac80b25c8ad659cd40b445d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:20:35 +0200 Subject: Remove not needed tests --- tests/arch/ice40/alu.v | 19 ------------------- tests/arch/ice40/alu.ys | 11 ----------- tests/arch/ice40/div_mod.v | 13 ------------- tests/arch/ice40/div_mod.ys | 9 --------- 4 files changed, 52 deletions(-) delete mode 100644 tests/arch/ice40/alu.v delete mode 100644 tests/arch/ice40/alu.ys delete mode 100644 tests/arch/ice40/div_mod.v delete mode 100644 tests/arch/ice40/div_mod.ys (limited to 'tests/arch/ice40') diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/arch/ice40/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/arch/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/arch/ice40/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/arch/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D -- cgit v1.2.3 From 12383f37b2e1d72784e01db0431efc8882f25430 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:33:35 +0200 Subject: Common memory test now shared --- tests/arch/ice40/memory.v | 21 --------------------- tests/arch/ice40/memory.ys | 2 +- 2 files changed, 1 insertion(+), 22 deletions(-) delete mode 100644 tests/arch/ice40/memory.v (limited to 'tests/arch/ice40') diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ice40/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys index a66afbae6..c356e67fb 100644 --- a/tests/arch/ice40/memory.ys +++ b/tests/arch/ice40/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap -- cgit v1.2.3 From 3e0ffe05a79d3196b3644cddf422edb927673b04 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Nov 2019 15:41:33 +0100 Subject: Fixed tests --- tests/arch/ice40/fsm.ys | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'tests/arch/ice40') diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 5aacc6c73..223ba070e 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -2,12 +2,15 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check + +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module +select -assert-count 4 t:SB_DFF select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 15 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D -- cgit v1.2.3