From d45869855c6fc86dc6a0225018a8e383866dacb4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Dec 2019 16:44:57 -0800
Subject: Add #1598 testcase

---
 tests/arch/ice40/bug1598.ys | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 tests/arch/ice40/bug1598.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys
new file mode 100644
index 000000000..8438cb979
--- /dev/null
+++ b/tests/arch/ice40/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+        input clk,
+        output ledc
+    );
+ 
+    reg [6:0] led_counter = 0;
+    always @( posedge clk ) begin
+            led_counter <= led_counter + 1;
+    end
+    assign ledc = !led_counter[ 6:3 ];
+ 
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9
-- 
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