From 477e43d921d204c6bc6403109fea6506802c948c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Dec 2019 13:18:44 +0100 Subject: Fix xilinx tests, when iopads are default --- tests/arch/xilinx/add_sub.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/arch/xilinx/add_sub.ys') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 9dbddce47..920717a3d 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -7,5 +7,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 select -assert-count 6 t:MUXCY select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D +select -assert-none t:LUT2 t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D -- cgit v1.2.3 From 509da7ed1a1e27066451f57868108b473cf516a0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Dec 2019 16:12:45 +0100 Subject: Revert "Fix xilinx tests, when iopads are default" This reverts commit 477e43d921d204c6bc6403109fea6506802c948c. --- tests/arch/xilinx/add_sub.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/arch/xilinx/add_sub.ys') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 920717a3d..9dbddce47 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -7,5 +7,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 select -assert-count 6 t:MUXCY select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D -- cgit v1.2.3 From a82c701668d8197c01e54cb68bc45f2278f3172f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Dec 2019 16:22:24 +0100 Subject: Make test without iopads --- tests/arch/xilinx/add_sub.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/arch/xilinx/add_sub.ys') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 9dbddce47..313948cc5 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 -- cgit v1.2.3 From af852a0ea8d7a5671f24afce8118aa7a04dab129 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 10 Jan 2020 14:48:01 +0100 Subject: Fix tests --- tests/arch/xilinx/add_sub.ys | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tests/arch/xilinx/add_sub.ys') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 313948cc5..70cfe81a3 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -4,8 +4,8 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 14 t:LUT2 -select -assert-count 6 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D +stat +select -assert-count 16 t:LUT2 +select -assert-count 2 t:CARRY4 +select -assert-none t:LUT2 t:CARRY4 %% t:* %D -- cgit v1.2.3