From 7764d0ba1dcf064ae487ee985c43083a0909e7f4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 Jan 2013 11:13:26 +0100 Subject: initial import --- tests/asicworld/code_hdl_models_gray_counter.v | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 tests/asicworld/code_hdl_models_gray_counter.v (limited to 'tests/asicworld/code_hdl_models_gray_counter.v') diff --git a/tests/asicworld/code_hdl_models_gray_counter.v b/tests/asicworld/code_hdl_models_gray_counter.v new file mode 100644 index 000000000..bc1e740ab --- /dev/null +++ b/tests/asicworld/code_hdl_models_gray_counter.v @@ -0,0 +1,33 @@ +//----------------------------------------------------- +// Design Name : gray_counter +// File Name : gray_counter.v +// Function : 8 bit gray counterS +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module gray_counter ( + out , // counter out + enable , // enable for counter + clk , // clock + rst // active hight reset + ); + + //------------Input Ports-------------- + input clk, rst, enable; + //----------Output Ports---------------- + output [ 7:0] out; + //------------Internal Variables-------- + wire [7:0] out; + reg [7:0] count; + //-------------Code Starts Here--------- + always @ (posedge clk) + if (rst) + count <= 0; + else if (enable) + count <= count + 1; + + assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ + count[5]),(count[5] ^ count[4]), (count[4] ^ + count[3]),(count[3] ^ count[2]), (count[2] ^ + count[1]),(count[1] ^ count[0]) }; + +endmodule -- cgit v1.2.3