From 9ef078848a5b121336b83043c565ce47433eb2d8 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 5 Dec 2018 04:50:38 +0000 Subject: gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. --- tests/lut/map_or.v | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 tests/lut/map_or.v (limited to 'tests/lut/map_or.v') diff --git a/tests/lut/map_or.v b/tests/lut/map_or.v new file mode 100644 index 000000000..8b8c55188 --- /dev/null +++ b/tests/lut/map_or.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a|b; +endmodule -- cgit v1.2.3